CN105591839A - Device, method and system of testing network exchange chip - Google Patents
Device, method and system of testing network exchange chip Download PDFInfo
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- CN105591839A CN105591839A CN201510975480.8A CN201510975480A CN105591839A CN 105591839 A CN105591839 A CN 105591839A CN 201510975480 A CN201510975480 A CN 201510975480A CN 105591839 A CN105591839 A CN 105591839A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/50—Testing arrangements
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
Abstract
The invention provides a device, method and system of testing a network exchange chip. The device comprises an FPGA chip, a JTAG interface, a PCIE interface, a test result determination device, a code memory and at least one network input interface. The JTAG interface is used for receiving the network exchange chip logic code transmitted by the outside and sending the network exchange chip logic code to the code memory; the code memory is used for storing the network exchange chip logic code; the network input interface is used for receiving the data packet transmitted through an external network, and transmitting the data packet to the FPGA chip; the FPGA chip is used for performing traffic forwarding on the data packet according to the network exchange chip logic code, and transmitting the formed forwarding result to the PCIE interface; the PCIE interface is used for sending the received forwarding result to the test result determination device; the test result determination device is used for determining whether the network exchange chip logic code is up to standard according to the forwarding result. The scheme can improve the efficiency of testing a network exchange chip.
Description
Technical field
The present invention relates to field of computer technology, particularly a kind of device of test network exchange chip,Method and system.
Background technology
Along with the development of computer technology, network has become the requisite composition of computer technology portionPoint, can realize between user and user by network, and data mutual between user and server,User can obtain the various network resources such as video, audio frequency, document, application program by network, also canTo communicate by letter in time with other users by network, thereby network becomes more the function of computerPowerful, for user's life and work provide great convenience.
Along with the continuous increase of computer network user data, computer network also becomes and becomes increasingly complex,Need to realize the communication between heterogeneous networks node by the network switch, and network exchanging chip is networkThe core component of switch, the performance of network exchanging chip, by directly affecting the performance of the network switch, is enteredThe performance of the one step network switch can affect stability and the reliability of computer network, thereby needs networkThe performance of exchange chip is tested, and the key of network exchanging chip checking is that network exchanging chip is patrolledCollecting code verifies.
At present, after the network switch chip that network switch chip producer makes new advances in exploitation, will developNetwork exchanging chip logical code be encapsulated in phy chip, then phy chip is connected to specificallyOn mainboard, thus to newly developed go out the performance of network exchanging chip test.
Be directed to the method for prior art test network exchange chip, need to be by the network exchange core of developingSheet logical code is encapsulated in phy chip, tests after making complete network exchanging chip, ifPerformance does not meet the demands, and needs to revise Reseal test after network exchanging chip logical code, netThe efficiency that cross winding changes chip testing is lower.
Summary of the invention
The device, the method and system that the invention provides a kind of test network exchange chip, can improve networkThe efficiency of exchange chip test.
The embodiment of the present invention provides a kind of device of test network exchange chip, comprising: field-programmableGate array FPGA chip, joint test working group jtag interface, quick peripheral component interconnect standard PCIEInterface, test result determining device, code memory and at least one network input interface;
Described jtag interface, is connected with described fpga chip, hands over for receiving the outside network sendingChange chip logic code, and through described fpga chip, described network exchanging chip logical code is sent toDescribed code memory;
Described code memory, is connected with described fpga chip, for storing described network exchanging chipLogical code;
Described network input interface, is connected with described fpga chip, sends out by external network for receivingThe packet sending, and by extremely described fpga chip of described Packet Generation;
Described FPAG chip, for the network exchanging chip logic of storing according to described code memoryCode, carries out forwarded to described packet, and the forwarding result of formation is sent to described PCIEInterface;
Described PCIE interface, one end is connected with described fpga chip, the other end and described test resultDetermining device is connected, the described forwarding result sending for receiving described fpga chip, and by described forwardingResult is sent to described test result determining device;
Described test result determining device, for according to described forwarding result, judges described network exchanging chipLogical code whether up to standard.
Preferably, described network input interface comprises: PHY chip and/or can plug SFP lightNetwork interface;
Described PHY chip, one end is connected with described fpga chip, and the other end connects by legacy networkMouth is connected with outside legacy network, for receiving the packet sending by described legacy network, and willThe Packet Generation receiving is to described fpga chip;
Described SFP optical network interface, one end is connected with described fpga chip, the other end and outside lightNetwork is connected, and for receiving the packet sending by described optical-fiber network, and the packet receiving is sent outDeliver to described fpga chip;
Preferably, this device further comprises: data buffer;
Described data buffer, is connected with described fpga chip, for judging described network input interfaceReceive the speed whether speed of packet is greater than described fpga chip packet is carried out forwarded,If so, temporarily store described fpga chip and have little time to carry out the described packet of forwarded.
Preferably, described test result determining device, for being directed to each packet, by this packetForwarding result and the target of this packet forward result and contrast, judge the forwarding result of this packetContent and form whether forward and come to the same thing with the target of this packet, if exist any one or manyThe forwarding result of individual packet is different from corresponding target forwarding result, judges described network exchanging chipLogical code is not up to standard, if the forwarding result of any one packet forwards result all with corresponding targetIdentical, judge that described network exchanging chip logical code is up to standard.
Preferably, described code memory, for receiving described jtag interface through described fpga chipAfter the network exchanging chip logical code sending, judge in described code memory, whether to store other netsCross winding changes chip logic code, if so, and by the legacy network exchange of storing in described code memoryChip logic code deletion, and store the network exchanging chip logical code newly receiving, otherwise directly depositThe network exchanging chip logical code that Chu Xin receives.
The embodiment of the present invention also provides a kind of method of test network exchange chip, comprising:
Receive the outside network exchanging chip logical code sending, and store;
Receive the packet that external network sends;
According to described network exchanging chip logical code, described packet is carried out to forwarded, formation turnsSend out result;
According to described forwarding result, judge that whether described network exchanging chip logical code is up to standard.
Preferably, the packet that described reception external network sends comprises:
By the PHY chip being connected with legacy network, receive the packet sending by outside legacy network;
And/or,
By the SFP optical network interface being connected with optical-fiber network, receive the data that send by exterior light networkBag.
Preferably, after the packet sending at described reception external network, further comprise:
Judge that receiving external network sends the speed of packet and whether be greater than packet is carried out to forwardedSpeed, if so, temporarily stores the packet that has little time to carry out forwarded.
Preferably, described according to described forwarding result, whether judge described network exchanging chip logical codeUp to standard comprising:
Be directed to each packet, the target of the forwarding result of this packet and this packet is forwarded to knotFruit contrasts, judge the content of forwarding result of this packet and form whether with the target of this packetForwarding comes to the same thing, if exist the forwarding result of any one or more packets to turn with corresponding targetSend out result difference, judge that described network exchanging chip logical code is not up to standard, if any one dataThe forwarding result of bag is all identical with corresponding target forwarding result, judges described network exchanging chip logicCode is up to standard.
Preferably, describedly receive the outside network exchanging chip logical code sending, and store and comprise:
Receive after the outside network exchanging chip logical code sending, judge that storage networking exchange chip patrolsIn the code memory of volume code, whether store other network exchanging chip logical codes, if so,The legacy network exchange chip logical code of storing in described code memory is deleted, and will newly be receivedNetwork exchange logical code store in described code memory, otherwise directly by the network newly receivingExchange logic code storage is in described code memory.
The embodiment of the present invention also provides a kind of system of test network exchange chip, comprising: at least twoThe device of any one test network exchange chip that above-described embodiment provides and the serial ports of equal numberSATA interface;
Fpga chip phase in the device of each described SATA interface and a described test network chipConnect, wherein, in the device of different described SATA interfaces and different described test network exchange chipsFpga chip be connected;
Described in each, SATA interface is connected successively, to realize the dress of test network exchange chip described in eachPut successively and be connected;
Described SATA interface, for transmitting described data between two described fpga chips being connectedBag and forwarding result.
The embodiment of the present invention provides a kind of device, method and system of test network exchange chip, this dressPut and comprise fpga chip, jtag interface, PCIE interface, test result determining device, code memoryAnd at least one network input interface, in the time that needs are tested network exchanging chip, pass through JTAGInterface stores the network exchanging chip logical code of network exchanging chip to be measured in code memory into, logicalCross network input interface and send packet to fpga chip, fpga chip is according to depositing in code memoryThe network exchanging chip logical code of storage, carries out forwarded to the packet receiving, and forms forwardingAs a result, by PCIE interface, forwarding result is sent to test result determining device, test result determining deviceJudge that according to the forwarding result receiving whether network exchanging chip logical code is up to standard, like this, need to surveyWhen examination network exchanging chip, after being encapsulated in phy chip, enters again network exchanging chip logical codeRow test, only need be sent to network exchanging chip logical code in fpga chip, just can complete netThe test of network exchange chip, saved by network exchanging chip logical code be encapsulated in phy chip timeBetween, improve the efficiency of network exchanging chip test.
Brief description of the drawings
Fig. 1 is the device schematic diagram of a kind of test network exchange chip of providing of one embodiment of the invention;
Fig. 2 is the system schematic of a kind of test network exchange chip of providing of one embodiment of the invention;
Fig. 3 is the device schematic diagram of a kind of test network exchange chip of providing of another embodiment of the present invention;
Fig. 4 is the method flow diagram of a kind of test network exchange chip of providing of one embodiment of the invention.
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried outDescribe clearly and completely. Obviously, described embodiment is only the present invention's part embodiment, and notWhole embodiment. Based on the embodiment in the present invention, those of ordinary skill in the art are not makingThe every other embodiment obtaining under creative work prerequisite, belongs to the scope of protection of the invention.
As shown in Figure 1, one embodiment of the invention provides a kind of device of test network exchange chip,Comprise: on-site programmable gate array FPGA chip 101, joint test working group jtag interface 102,Peripheral component interconnect standard PCIE interface 103, test result determining device 104, code memory 105 fastAnd at least one network input interface 106;
Described jtag interface 102, is connected with described fpga chip 101, for receiving outside transmissionNetwork exchanging chip logical code, and through described fpga chip 101, described network exchanging chip is patrolledCollect code and be sent to described code memory 105;
Described code memory 105, is connected with described fpga chip 101, for storing described networkExchange chip logical code;
Described network input interface 106, is connected with described fpga chip 101, outside passing through for receptionThe packet that portion's network sends, and by extremely described fpga chip 101 of described Packet Generation;
Described fpga chip 101, for the network exchange of storing according to described code memory 105Chip logic code, carries out forwarded to described packet, and the forwarding result of formation is sent to instituteState PCIE interface 103;
Described PCIE interface 103, one end is connected with described fpga chip 101, the other end and described surveyTest result determining device 104 is connected, the described forwarding result sending for receiving described fpga chip 101,And described forwarding result is sent to described test result determining device 104;
Described test result determining device 104, for according to described forwarding result, judges described network exchangeWhether chip logic code is up to standard.
The embodiment of the present invention provides a kind of device of test network exchange chip, and this device comprises FPGAChip, jtag interface, PCIE interface, test result determining device, code memory and at least one netNetwork input interface, in the time that needs are tested network exchanging chip, will treat survey grid by jtag interfaceThe network exchanging chip logical code of network exchange chip stores in code memory, connects by network inputMouth sends packet to fpga chip, and fpga chip is according to the network exchange of storing in code memoryChip logic code, carries out forwarded to the packet receiving, and forms forwarding result, passes through PCIEForwarding result is sent to test result determining device by interface, and test result determining device is according to the forwarding receivingResult judges that whether network exchanging chip logical code is up to standard, like this, and while needing test network exchange chip,After being encapsulated in phy chip, tests again network exchanging chip logical code, and only need be by networkExchange chip logical code is sent in fpga chip, just can complete the test of network exchanging chip,Save network exchanging chip logical code has been encapsulated into the time in phy chip, improved network exchangeThe efficiency of chip testing.
In one embodiment of the invention, network input interface comprises PHY chip and/or SFP optical-fiber networkInterface, PHY chip is connected with legacy network by legacy network interface, can be from by PHY chipLegacy network sends packet to fpga chip, and SFP optical network interface is connected with optical-fiber network, passes through SFPOptical network interface can send packet to fpga chip from optical-fiber network, and like this, fpga chip canAccording to network exchanging chip logical code, the packet sending by legacy network and by optical-fiber network is carried outForwarded, has improved the applicability of the device of this test network exchange chip, has improved tested simultaneouslyThe accuracy of examination network exchanging chip test.
In one embodiment of the invention, the device of this test network exchange chip also comprises data buffer,Data buffer is connected with fpga chip, is passing through network input interface from external network to FPGA coreSheet sends in the process of packet, and data buffer judges that the speed of network input interface reception packet isThe no speed that is greater than fpga chip packet is carried out forwarded, if so, carrys out fpga chipTemporarily store in data buffer not as good as the packet that carries out forwarded, when network input interface receivesThe speed of packet is less than fpga chip when packet is carried out to the speed of forwarded, by data buffer storagePacket in device reads out and carries out forwarded, like this, in the time that data traffic is large, passes through data buffer storageDevice carries out buffer memory to the packet that has little time to process, and avoids because data traffic causes greatly data-bag lost pairThe test result of network exchanging chip impacts, and has improved the accuracy of network exchanging chip test.
In one embodiment of the invention, test result determining device passes through PCIE receiving fpga chipAfter the forwarding result that interface sends, be directed to each packet, test result determining device is by this packetForwarding result and the target of predetermined this packet forward result and contrast, judge this packetForwarding resultant content and form whether forward and come to the same thing with the target of this packet, if all numbersContent and form according to the forwarding result of wrapping all forward and come to the same thing with corresponding target, judge network friendshipChange chip logic code up to standard, if there is the interior perhaps form of the forwarding result of one or more packetsTo forward result different from corresponding target, judge that network exchanging chip logical code is not up to standard, by withTarget transformation result compares, can accurately judge to the forwarding result of packet whether with predetermined orderMark identical, thereby judge that whether network exchanging chip logical code up to standard, improved network exchanging chipThe accuracy of test.
In one embodiment of the invention, code memory receives after exchange chip logical code, judgementIn code memory, whether store other network exchanging chip logical code, if so, first will generationIn code memory, original network exchanging chip logical code is deleted, then by the network exchange newly receivingChip logic code storage is in code memory, if not, direct by the network exchange newly receivingChip logic code storage, in code memory, like this, just can realize to fpga chip repeatedlyProgramming, when judging that network exchanging chip logical code is not up to standard, after revising accordingly, can will repairNetwork exchanging chip logical code after changing stores in code memory again, and covers legacy network friendshipChange chip logic code, amended network exchanging chip logical code is tested, make this Test NetworkThe device of network exchange chip can be reused, and avoids repeating to encapsulate phy chip, has reduced test networkThe cost of exchange chip.
As shown in Figure 2, one embodiment of the invention provides a kind of system of test network exchange chip,Comprise: the device 201 of any one test network exchange chip that at least two above-described embodiments provide andThe serial ports SATA interface 202 of respective amount;
In the device 201 of each described SATA interface 202 and a described test network exchange chipFpga chip is connected, wherein, and different described SATA interfaces 202 and different described test networksFpga chip in the device 201 of exchange chip is connected;
Described in each, SATA interface 202 is connected successively, to realize test network exchange chip described in eachDevice 201 be successively connected;
Described SATA interface 202, described in transmission between two described fpga chips being connectedPacket and forwarding result.
The embodiment of the present invention provides a kind of system of test network exchange chip, comprise at least two above-mentionedThe device of the test network exchange chip that embodiment provides, by SATA interface by two adjacent testsThe device of network exchanging chip couples together, thereby the device of all test network exchange chips is connected successivelyConnect, can be mutual between the fpga chip in the device of two adjacent test network exchange chipsTransmission packet and forwarding result, like this, can provide turning for network of sufficient amount by this systemSend out resource and for receiving the network input interface of packet, to meet, diverse network exchange chip is enteredThe demand of row test.
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with the net shown in Fig. 3The device of network exchange chip, is described in further detail the method for test network exchange chip.
As shown in Figure 3, one embodiment of the invention provides a kind of method of test network exchange chip,Comprise:
Step 401: the network exchanging chip logic that receives network exchanging chip to be measured by jtag interfaceCode.
In one embodiment of the invention, as shown in Figure 3, FTAG interface 304 one end and FPGA coreSheet 301 is connected, and the other end is connected with outside computer, and user exchanges to test network by computerThe device of chip sends the network exchanging chip logical code of network exchanging chip to be tested, FTAG interface304 receive after the network exchanging chip logical code of outer computer transmission, and the network receiving is handed overChange chip logic code and send to fpga chip 301, fpga chip 301 is handed over the network receivingChange chip logic code and send to code memory 305, wherein, code memory 305 can be 64MBFLASH chip.
Step 402: store the network exchanging chip logical code receiving all into code memory.
In one embodiment of the invention, as shown in Figure 3, code memory 305 receives treats FPGA coreAfter the network exchanging chip logical code that sheet 301 sends, first judge in code memory 305 and whether depositContain other network exchanging chip logical code, if so, by original net in code memory 305Cross winding changes chip logic code deletion, and stores the network exchanging chip logical code newly receiving into generationIn code memory 305, if there is no network exchanging chip logical code in code memory, directly willThe new network exchanging chip logical code receiving all stores in code memory 305. For example network is handed overChange chip logic code storage in 64MBFLASH chip.
Step 403: by PHY chip and SFP optical network interface end data packet, and will receivePacket Generation is to fpga chip.
In one embodiment of the invention, the device of test network exchange chip as shown in Figure 3,4SPY chip 303 is connected with legacy network interface, and legacy network interface is connected with legacy network, surveyingThe device of examination network exchanging chip is connected with legacy network, 4 SFP optical network interface 302 and optical-fiber networkBe connected, so that the device of test network exchange chip is connected with optical-fiber network. Start legacy network and optical-fiber networkAfter, legacy network sends packet by 4 PHY chips 303 to fpga chip 301, meanwhile,Optical-fiber network sends packet by 4 SFP optical network interface 302 to fpga chip 301, PHY coreSheet 303 and SFP optical network interface 302 receive after packet, by the Packet Generation receiving extremelyFpga chip 301. Wherein, PHY chip 303 can be 1GbPHY chip, and SFP optical-fiber network connectsMouth 302 can be 10GbSFP interface.
It should be noted that, the fpga chip of different model can connect the PHY chip of different numbersAnd SFP optical network interface, according to the demand of test, can select flexibly the FPGA core of suitable typesSheet or be chosen in flexibly the quantity that connects PHY chip and SFP optical network interface on fpga chip.In addition, if an independent fpga chip can not meet the demand of test, can pass through SATA interface308 are connected multiple fpga chips, the system of composition test network exchange chip, thus obtain enoughThe PHY chip of quantity and the connected node of SFP optical network interface.
Step 404:FPGA chip, according to network exchanging chip logical code, carries out network to packetForward, form and forward result.
In one embodiment of the invention, as shown in Figure 3, fpga chip 301 receives each PHYThe packet mouth that chip 303 and each SFP optical network interface 302 send, from code memory 305Read network exchanging chip logical code, according to the network exchanging chip logical code reading, right successivelyThe packet receiving carries out forwarded, obtains form corresponding with network exchanging chip logical codeForward result.
At fpga chip 301, packet is carried out in forwarded process, if 4 PHY chipsThe speed that 303 and 4 SFP optical network interface 302 send packet to fpga chip 301 is greater thanFpga chip 301 carries out the speed of forwarded to packet, fpga chip 301 will have little timeThe packet that carries out forwarded temporarily stores in data buffer 309, treats 4 PHY chips 303And the speed that 4 SFP optical network interface 302 send packet to fpga chip 301 is less than FPGAWhen chip 301 carries out the speed of forwarded to packet, again by data buffer 309 storagePacket reads out and carries out forwarded. Wherein, data buffer 309 can be 256MBDDR3SDRAM。
Forwarding result is sent to test result determining device by step 405:FPGA chip.
In one embodiment of the invention, as shown in Figure 3, fpga chip 301 forms and forwards after result,Forwarding result is sent to PCIE interface 306 by fpga chip 301, PCIE interface 306 one end and FPGAChip 301 is connected, and the other end is connected with test result determining device 307, and PCIE interface 306 receives and turnsSend out after result, forwarding result is sent to test result determining device 307. Wherein, test result determining device307 can be computer, corresponding, can be same meter for the computer being connected with jtag interfaceCalculation machine.
Step 406: test result determining device, according to forwarding result, judges network exchanging chip logical codeWhether up to standard.
In one embodiment of the invention, as shown in Figure 3, test result determining device 307 receives PCIEInterface send forwarding result after, for each packet, by the forwarding result of this packet with in advanceTarget corresponding to this packet of determining forward result and contrast, and judges the forwarding result of this packetThe target whether content and form be corresponding with this packet forwards and comes to the same thing, and all forwarding results are carried outAfter judgement, if the content of all forwarding results and form all forward and come to the same thing with corresponding target,Illustrate that network exchanging chip logical code is up to standard, the performance of network exchanging chip logical code and reliable is describedProperty up to standard, the performance of the network exchanging chip of corresponding this network exchanging chip logical code of explanation encapsulation andReliability is also up to standard, the flow of can dispatching from the factory. If there is the perhaps interior of one or more forwarding resultsForm is different from corresponding target forwarding result, illustrates that network exchanging chip logical code is not up to standard, phasePerformance and reliability that the judgement of answering encapsulates the network exchanging chip of this network exchanging chip logical code are alsoNot up to standard.
After judging that network exchanging chip logical code is not up to standard, need to be to this network exchanging chip logic generationCode is modified, and after having revised, again network exchanging chip is patrolled by step 401 to step 406Collect code and test, until up to standard.
According to such scheme, the device of a kind of test network exchange chip that embodiments of the invention provide,Method and system, at least have following beneficial effect:
1,, in the embodiment of the present invention, the device of this test network exchange chip comprises fpga chip, JTAGInterface, PCIE interface, test result determining device, code memory and at least one network input interface,In the time that needs are tested network exchanging chip, by jtag interface by network exchanging chip to be measuredNetwork exchanging chip logical code stores in code memory, by network input interface to FPGA coreSheet sends packet, and fpga chip is according to the network exchanging chip logical code of storing in code memory,The packet receiving is carried out to forwarded, and form forwarding result, will forward by PCIE interfaceResult is sent to test result determining device, and test result determining device judges net according to the forwarding result receivingWhether cross winding changes chip logic code up to standard, like this, and while needing test network exchange chip, without by netCross winding changes after chip logic code is encapsulated in phy chip and tests, only need be by network exchanging chipLogical code is sent in fpga chip, just can complete the test of network exchanging chip, and having saved willNetwork exchanging chip logical code is encapsulated into the time in phy chip, has improved network exchanging chip testEfficiency.
2,, in the embodiment of the present invention, the device of this test network exchange chip comprises PHY chip and SFPOptical network interface, can realize the device and legacy network phase of test network exchange chip by PHY chipConnect, receive the packet that legacy network sends, can realize Test Network cross winding by SFP optical network interfaceThe device that changes chip is connected with optical-fiber network, receives the packet that optical-fiber network sends, thereby can realize passingThe test of system network and optical network data bag, has improved the applicability of the device of this test network exchange chipAnd the credibility of test result.
3,, in the embodiment of the present invention, the device of this test network exchange chip also comprises data buffer, whenThe excessive velocities of legacy network or optical network data transmission bag, receives the device of test network exchange chipWhen the speed of packet is greater than the speed of forwarded packet, fpga chip can be had little time carry outThe packet of forwarded temporarily stores in data buffer, treats that fpga chip has the rich energy that forwardsAfter power, again the packet in data buffer is taken out and carries out forwarded, avoid data-bag lost impact to surveyTest result, has improved the accuracy that network exchanging chip is tested.
4, in the embodiment of the present invention, in the time of storage networking exchange chip logical code in code memory,First judge in code memory whether store other network exchanging chip logical codes, if had,The network exchanging chip logic that after original network exchanging chip logical code is deleted, storage newly receives againCode, so just can realize repetition to programming network exchanging chip logical code in fpga chip, realThe now recycling of the device of this test network exchange chip, has reduced the cost of test network exchange chip.
It should be noted that, in this article, the relational terms such as first and second be only used for byEntity or operation and another entity or operating space separate, and not necessarily require or imply thisBetween a little entities or operation, there is relation or the order of any this reality. And term " comprises "," comprise " or its any other variant is intended to contain comprising of nonexcludability, thereby make to comprise that one isProcess, method, article or the equipment of row key element not only comprise those key elements, but also comprise do not have brightOther key elements of really listing, or it is intrinsic to be also included as this process, method, article or equipment instituteKey element. In the situation that there is no more restrictions, " comprise one " by statement and limitKey element, and be not precluded within process, method, article or the equipment that comprises described key element also exist anotherOuter same factor.
One of ordinary skill in the art will appreciate that: all or part of step that realizes said method embodimentCan complete by the relevant hardware of programmed instruction, aforesaid program can be stored in embodied on computer readableStorage medium in, this program, in the time carrying out, is carried out and is comprised the step of said method embodiment; And it is aforementionedStorage medium comprise: various Jie that can be program code stored such as ROM, RAM, magnetic disc or CDIn matter.
Finally it should be noted that: the foregoing is only preferred embodiment of the present invention, only for this is describedThe technical scheme of invention, is not intended to limit protection scope of the present invention. All in spirit of the present invention and formerAny amendment of making, be equal to replacement, improvement etc., be all included in protection scope of the present invention.
Claims (10)
1. a device for test network exchange chip, is characterized in that, comprising: field-programmable gate arrayRow fpga chip, joint test working group jtag interface, quick peripheral component interconnect standard PCIEInterface, test result determining device, code memory and at least one network input interface;
Described jtag interface, is connected with described fpga chip, hands over for receiving the outside network sendingChange chip logic code, and through described fpga chip, described network exchanging chip logical code is sent toDescribed code memory;
Described code memory, is connected with described fpga chip, for storing described network exchanging chipLogical code;
Described network input interface, is connected with described fpga chip, sends out by external network for receivingThe packet sending, and by extremely described fpga chip of described Packet Generation;
Described FPAG chip, for the network exchanging chip logic of storing according to described code memoryCode, carries out forwarded to described packet, and the forwarding result of formation is sent to described PCIEInterface;
Described PCIE interface, one end is connected with described fpga chip, the other end and described test resultDetermining device is connected, the described forwarding result sending for receiving described fpga chip, and by described forwardingResult is sent to described test result determining device;
Described test result determining device, for according to described forwarding result, judges described network exchanging chipLogical code whether up to standard.
2. device according to claim 1, is characterized in that,
Described network input interface comprises: PHY chip and/or can plug SFP optical network interface;
Described PHY chip, one end is connected with described fpga chip, and the other end connects by legacy networkMouth is connected with outside legacy network, for receiving the packet sending by described legacy network, and willThe Packet Generation receiving is to described fpga chip;
Described SFP optical network interface, one end is connected with described fpga chip, the other end and outside lightNetwork is connected, and for receiving the packet sending by described optical-fiber network, and the packet receiving is sent outDeliver to described fpga chip.
3. device according to claim 1, is characterized in that, further comprises: data buffer;
Described data buffer, is connected with described fpga chip, for judging described network input interfaceReceive the speed whether speed of packet is greater than described fpga chip packet is carried out forwarded,If so, temporarily store described fpga chip and have little time to carry out the described packet of forwarded.
4. device according to claim 1, is characterized in that,
Described test result determining device, for being directed to each packet, by the forwarding knot of this packetFruit forwards result with the target of this packet and contrasts, judge this packet forwarding result content andWhether form forwards and comes to the same thing with the target of this packet, if there are any one or more packetsForwarding result and corresponding target to forward result different, judge described network exchanging chip logical codeNot up to standard, if the forwarding result of any one packet is all identical with corresponding target forwarding result,Judge that described network exchanging chip logical code is up to standard.
5. according to arbitrary described device in claim 1 to 4, it is characterized in that,
Described code memory, the net sending through described fpga chip for receiving described jtag interfaceCross winding changes after chip logic code, judges in described code memory, whether to store other network exchange coresSheet logical code, if so, by the legacy network exchange chip logic of storing in described code memoryCode deletion, and store the network exchanging chip logical code newly receiving, receive otherwise directly storage is newThe network exchanging chip logical code arriving.
6. a method for test network exchange chip, is characterized in that, comprising:
Receive the outside network exchanging chip logical code sending, and store;
Receive the packet that external network sends;
According to described network exchanging chip logical code, described packet is carried out to forwarded, formation turnsSend out result;
According to described forwarding result, judge that whether described network exchanging chip logical code is up to standard.
7. method according to claim 6, is characterized in that, described reception external network sendsPacket comprises:
By the PHY chip being connected with legacy network, receive the packet sending by outside legacy network;
And/or,
By the SFP optical network interface being connected with optical-fiber network, receive the data that send by exterior light networkBag.
8. method according to claim 6, is characterized in that,
After the packet sending at described reception external network, further comprise: judgement receives external networkWhether the speed that sends packet is greater than the speed of packet being carried out to forwarded, if so, and in the future notAnd the packet that carries out forwarded is temporarily stored;
And/or,
Described according to described forwarding result, judge whether described network exchanging chip logical code is up to standard to comprise:Be directed to each packet, the target of the forwarding result of this packet and this packet forwarded to result and enterRow contrast, judges whether content and the form of the forwarding result of this packet forwards with the target of this packetCome to the same thing, if exist the forwarding result of any one or more packets to forward knot with corresponding targetFruit is different, judges that described network exchanging chip logical code is not up to standard, if any one packetForward result all identical with corresponding target forwarding result, judge described network exchanging chip logical codeUp to standard.
9. according to the arbitrary described method of claim 6 to 8, it is characterized in that, described reception is outside to be sent outThe network exchanging chip logical code sending, and store and comprise:
Receive after the outside network exchanging chip logical code sending, judge that storage networking exchange chip patrolsIn the code memory of volume code, whether store other network exchanging chip logical codes, if so,The legacy network exchange chip logical code of storing in described code memory is deleted, and will newly be receivedNetwork exchange logical code store in described code memory, otherwise directly by the network newly receivingExchange logic code storage is in described code memory.
10. a system for test network exchange chip, is characterized in that, comprising: at least two rightsRequire the arbitrary described device of test network exchange chip and the serial ports SATA of equal number in 1 to 5Interface;
Fpga chip phase in the device of each described SATA interface and a described test network chipConnect, wherein, in the device of different described SATA interfaces and different described test network exchange chipsFpga chip be connected;
Described in each, SATA interface is connected successively, to realize the dress of test network exchange chip described in eachPut successively and be connected;
Described SATA interface, for transmitting described data between two described fpga chips being connectedBag and forwarding result.
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