CN108075949A - A kind of VPWS environment realizes the method and apparatus of RFC2544 - Google Patents
A kind of VPWS environment realizes the method and apparatus of RFC2544 Download PDFInfo
- Publication number
- CN108075949A CN108075949A CN201711324839.0A CN201711324839A CN108075949A CN 108075949 A CN108075949 A CN 108075949A CN 201711324839 A CN201711324839 A CN 201711324839A CN 108075949 A CN108075949 A CN 108075949A
- Authority
- CN
- China
- Prior art keywords
- vpws
- fpga
- exchange chip
- test
- rfc2544
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/74—Address processing for routing
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
- H04L43/0823—Errors, e.g. transmission errors
- H04L43/0829—Packet loss
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
- H04L43/0852—Delays
Abstract
A kind of VPWS environment realizes the method and apparatus of RFC2544, including multi-core CPU the core as control plane, various control face agreement is run, generation forwards the VPWS needed during surface treatment data packet and the various list items of RFC2544, and multi-core CPU is additionally operable to the data packet of generation RFC2544 drive end tests；The RFC2544 test data bags that forwarding surface is worked in coordination by exchange chip and FPGA realizations, exchange chip and FPGA under processing VPWS environment；Give out a contract for a project for RFC2544 drive ends, multi-core CPU generation test data bag write-in FPGA, FPGA send test flow to exchange chip, and exchange chip sends test flow；For RFC2544 Partner, after exchange chip packet receiving processing, test flow is sent to FPGA, test flow is sent to exchange chip again after FPGA processing, exchange chip sends test flow；For RFC2544 drive end packet receivings, after exchange chip packet receiving processing, test flow is sent to FPGA, FPGA does test flow the last calculating of RFC2544 test parameters；It can realize the surface speed forwarding of device port, ensure the forwarding performance of device port.
Description
Technical field
The present invention relates to computer network data fields of communication technology, and in particular to a kind of VPWS environment realizes RFC2544
Method and apparatus.
Background technology
VPWS (Virtual Private Wire Service) refers to construction on the infrastructure of MPLS network,
Two layers of transparent transmission of high speed are provided between a pair of of port of two routers, it can be saturating by the original ether network packet of local end PE equipment
It is bright to be transmitted to far-end PE equipment, it is a kind of two layers of VPN agreements.
RFC2544 agreements be RFC tissues propose for evaluating and testing network interconnection device (fire wall, IDS, Switch etc.)
International standard.The submission form of specific test method, result mainly to the performance evaluating parameter defined in RFC1242 is made
More detailed regulation.The parameter of many test heterogeneous networks equipment is defined in RFC2544, mainly including throughput
(Throughput), packet loss (Lost Rate), time delay (Latency) and back-to-back (Back-to-Back) 4 it is mostly important
Parameter.Throughput reflection is devices under to handle the maximum data traffic of (not lost data packets)；Packet loss is anti-
Reflect the ability that equipment under test bears certain loads；The speed of time delay reflection equipment under test processing data packet；Reflection is tested back-to-back
Equipment handles the ability (data buffer storage ability) of bursty data.
The most basic most common business of PTN (Packet Transport Network, Packet Transport Network) equipment is exactly
VPWS, PTN device networking certification have to pass through RFC2544 performance tests under VPWS networkings.The exchange chip of industry mainstream at present
Such as broadcom or Marvel, do not possess the abilities of generation RFC2544 test data streams, if with CPU soft forwarding next life
Into test data stream, although source code flexible, transfer capability is too poor, port can not linear speed, and the CPU data flows measured
Time delay error is larger.
It is therefore desirable to provide a kind of VPWS environment to realize the method and apparatus of RFC2544, and it can guarantee forwarding
Can, surface speed forwarding is realized in port.
The content of the invention
A kind of VPWS environment proposed by the present invention realizes the method and apparatus of RFC2544, is used as control plane by multi-core CPU
Core writes VPWS various forwarding-table items related to RFC2544 to forwarding surface, and exchange chip and FPGA work in coordination as forwarding surface
The test VPWS flows of RFC2544 are handled, the surface speed forwarding of device port can be realized, ensure that the forwarding of device port
Energy.
To achieve the above object, present invention employs following technical schemes：
A kind of method that VPWS environment realizes RFC2544, including core multi-core CPU as control plane, runs a variety of controls
Face agreement processed, generation forward the VPWS needed during surface treatment data packet and the various list items of RFC2544, multi-core CPU to be additionally operable to generate
The data packet of RFC2544 drive ends test；Forwarding surface realized by exchange chip and FPGA, and exchange chip and FPGA work in coordination place
Manage the RFC2544 test data bags under VPWS environment；Give out a contract for a project for RFC2544 drive ends, multi-core CPU generation test data bag is write
Enter FPGA, FPGA sends test flow to exchange chip, and exchange chip sends test flow；It is passive for RFC2544
Test flow after exchange chip packet receiving processing, is sent to FPGA, test flow is sent to exchange again after FPGA processing by end
Chip, exchange chip send test flow；For RFC2544 drive end packet receivings, after exchange chip packet receiving processing, survey
Examination flow is sent to FPGA, and FPGA does test flow the last calculating of RFC2544 test parameters；Specifically include following steps：
Give out a contract for a project for RFC2544 drive ends：
Step 1, multi-core CPU does the first processing, and testing the information such as corresponding UNI of VPWS examples according to user configuration connects
Mouthful, get the NNI mouths of corresponding VPWS examples and PW labels, TE labels, the MAC Address of next-hop P equipment, and according to
The test data bag target MAC (Media Access Control) address of family configuration, source MAC etc., generation need the data packet tested under VPWS environment, and
Bag is write FPGA；
Step 2, FPGA does second processing, according to the VPWS examples of configuration, long data packet, packet sending speed, burst-length, survey
Examination duration, test data stream type, data current test enable, be inserted into each bag VPWS instance numbers, stream ID, sequence number and
Test flow is sent to exchange chip by timestamp etc.；
Step 3, exchange chip does the 3rd processing, and directly NNI mouthfuls of transparent transmissions of test flow slave device are gone out.
For RFC2544 Partner：
Step 4, equipment is from NNI interface test data flows, and exchange chip does fourth process, outside peel test flow
Purpose MAC, source MAC, TE label, the PW labels of layer, stamp the VLANID for representing VPWS examples in load, and test flow is sent out
Give FPGA；
Step 5, FPGA does the 5th processing, and after exchange chip receives test flow, the VLANID peeled off in bag is used in combination
VLANID searches vlan table, encapsulates PW labels, TE labels, source MAC and target MAC (Media Access Control) address successively outside load, and
Test flow is sent to exchange chip；Multi-core CPU according to the environment of VPWS, can first generation represent the vlan tables of VPWS examples and write
Enter FPGA, content is from PW labels, TE labels, source MAC and the purpose for needing to encapsulate when going out for passive end equipment NNI mouthfuls
MAC Address；
Step 6, exchange chip does the 6th processing, and directly NNI mouthfuls of transparent transmissions of test flow slave device are gone out.
For RFC2544 drive end packet receivings：
Step 7, equipment is from NNI interface test data flows, and exchange chip does the 7th and handles, outside peel test flow
Test flow, is sent to FPGA by purpose MAC, source MAC, TE label, the PW labels of layer；
Step 8, FPGA does the 8th processing, and after exchange chip receives test flow, the VPWS in test flow is real
Example number, stream ID, sequence number and timestamp calculate handling capacity, delay, the frame loss of every stream of each VPWS examples of RFC2544
Rate waits test parameters with back-to-back.
The equipment that a kind of VPWS environment realizes RFC2544, the equipment include：
Service protocol module for running Routing Protocol, LDP agreements, ARP protocol etc., will realize far-end PE equipment and this
Routing between ground PE equipment is got through, on the NNI interfaces of two PE equipment run LDP agreements, mutual phase partitioning PW labels to pair
Side.Each PE equipment also needs to the study between direct-connected P equipment and arrives to side mac address.Service protocol module is to these agreements
After data processing, by treated, business forwarding information hair message gives forwarding table management module；
For receiving the business forwarding information, the integration of these business forwarding informations is converted to for forwarding table management module
The form that exchange chip processing module and FPGA processing modules need is written to exchange chip processing module and FPGA processing moulds
Block；And according to the test information of user configuration, generation needs the data packet tested under VPWS environment, and at bag write-in FPGA
Manage module；
Exchange chip processing module after the test data bag processing of the NNI entrances to PE equipment, sends data packet
To FPGA processing modules and after FPGA processing modules receive test data bag, sent from the NNI mouths of PE equipment.It hands over
The various businesses forwarding table that chip processing module processing data packet requires to look up is changed to be write by forwarding table management module；
FPGA processing modules, for according to configuration information, actively sending test data flow and giving exchange chip processing module,
And receive the data packet that exchange chip processing module sends over and data packet is further processed, then it is then forwarded to friendship
It changes chip processing module and calculates the various test parameters of RFC2544 after receiving test flow from exchange chip processing module.
The various businesses forwarding table that FPGA processing modules processing data packet requires to look up is write by forwarding table management module；
Give out a contract for a project as previously mentioned, for RFC2544 drive ends：
In step 1, the forwarding table management module of multi-core CPU does the first processing, and information is tested for example according to user configuration
The uni interface of the corresponding PE equipment of VPWS examples, get corresponding VPWS examples NNI mouths and PW labels, TE labels, under
One jumps the MAC Address of P equipment, and according to the test data bag target MAC (Media Access Control) address of user configuration, source MAC etc., generation needs
The data packet tested under VPWS environment, and bag is write FPGA processing modules.After the completion of VPWS environmental structures, forwarding table pipe
Reason module can generate the relevant list items of VPWS, such as generated in multi-core CPU in UNI inbound port attribute lists and stamp VPWS attribute marks
Will and the VPNID to represent VPWS examples generate VPWS forwarding tables by key assignments of VPNID, and VPWS forwarding tables content includes NNI mouthfuls
And PW labels, TE labels, the IP address of next-hop P equipment.Forwarding table management module can be also generated with NNI mouthfuls and next-hop P
The IP address of equipment is the ARP table of key assignments, and content is the MAC Address of next-hop P equipment.The table generated in advance according to these
, when the corresponding uni interface of user configuration test information binding VPWS examples, forwarding table management module is with regard to that can get correspondence
VPWS examples NNI mouths and PW labels, TE labels, the MAC Address etc. of next-hop P equipment, generation need in VPWS environment
The data packet of lower test, and bag is write FPGA processing modules.
In step 2, FPGA processing modules do second processing, according to the VPWS examples of configuration, long data packet, packet sending speed,
Burst-length, length of testing speech, test data stream type, data current test enable, and VPWS instance numbers, stream are inserted into each bag
Test flow is sent to exchange chip processing module by ID, sequence number and timestamp etc..
In step 3, exchange chip processing module does the 3rd processing, and directly test flow is gone out from NNI mouthfuls of transparent transmissions of PE equipment
It goes.
For RFC2544 Partner：
In step 4, PE equipment does fourth process from NNI interface test data flows, exchange chip processing module, stripping
Target MAC (Media Access Control) address, source MAC, TE labels, PW labels from test flow outer layer, stamp in load and represent VPWS examples
VLANID, test flow is sent to FPGA processing modules.Forwarding table management module needs to write MPLS label forwarding table to friendship
Change chip processing module so that data traffic can remove TE labels and PW labels.The present invention supports more VPWS examples, forwarding table
Management module needs are established into PW and the correspondence for going out PW, are realized by being inserted into VLANID in data traffic.
In step 5, FPGA processing modules do the 5th processing, after exchange chip processing module receives test flow, peel off
VLANID in bag simultaneously searches vlan table with VLANID, outside the load successively in encapsulation with going out PW labels, TE labels, source MAC
Location and target MAC (Media Access Control) address, and test flow is sent to exchange chip processing module.Forwarding table management module is real according to VPWS
Example, is established into PW and the correspondence for going out PW, can generate the vlan table write-in FPGA processing modules for representing VPWS examples, and content is
The PW labels, TE labels, source MAC and the target MAC (Media Access Control) address that encapsulate are needed when going out from passive end equipment NNI mouthfuls；
In step 6, exchange chip processing module does the 6th processing, and directly test flow is gone out from NNI mouthfuls of transparent transmissions of PE equipment
It goes.
For RFC2544 drive end packet receivings：
In step 7, for PE equipment from NNI interface test data flows, exchange chip processing module does the 7th processing, stripping
Test flow, is sent to FPGA processing by target MAC (Media Access Control) address, source MAC, TE labels, PW labels from test flow outer layer
Module.Forwarding table management module needs to write MPLS label forwarding table to exchange chip processing module so that data traffic can shell
From TE labels and PW labels.
In step 8, FPGA processing modules do the 8th processing, after exchange chip processing module receives test flow, according to
VPWS instance numbers, stream ID, sequence number and the timestamp in flow are tested, calculates every stream of each VPWS examples of RFC2544
Handling capacity, delay, frame loss rate and back-to-back etc. test parameters.
The beneficial effects of the invention are as follows：In the present invention program, core of the multi-core CPU as control plane, generation forwarding surface needs
The various list items wanted.Forwarding surface is realized that the list item of exchange chip and FPGA forwarding foundations is all by multinuclear by exchange chip and FPGA
CPU write enters.Give out a contract for a project for RFC2544 drive ends, multi-core CPU does the first processing, and bag is write FPGA according to configuration；FPGA does
Test flow according to give out a contract for a project bag long, packet sending speed and duration of giving out a contract for a project etc. of configuration, is sent to exchange chip by two processing, and
VPWS instance numbers, stream ID, sequence number and timestamp are inserted into each bag；Exchange chip does the 3rd processing, test flow transparent transmission
Go out NNI mouthfuls of equipment.For RFC2544 Partner, exchange chip does fourth process, the purpose MAC of peel test flow outer layer
Location, source MAC, TE labels, PW labels, stamp the VLANID for representing VPWS examples in load, and test flow is sent to
FPGA；Vlan table is write FPGA by multi-core CPU, and content is PW labels, TE labels, source MAC and target MAC (Media Access Control) address；FPGA
The 5th processing is done, after exchange chip receives test flow, the VLANID in bag is peeled off and searches vlan table with VLANID, carrying
Upper PW labels, TE labels, source MAC and target MAC (Media Access Control) address are encapsulated outside lotus successively, and test flow is sent to exchange core
Piece；Exchange chip does the 6th processing, and test flow transparent transmission is gone out NNI mouthfuls of equipment.For RFC2544 drive end packet receivings, core is exchanged
Piece does the 7th processing, and target MAC (Media Access Control) address, source MAC, TE labels, the PW labels of peel test flow outer layer send load
To FPGA；FPGA does the 8th processing, according to VPWS instance numbers, stream ID, sequence number and the timestamp in test flow, calculates
The handling capacity of the stream of each VPWS examples of RFC2544 every, delay, frame loss rate and the test parameters such as back-to-back.The present invention passes through
Multi-core CPU writes VPWS various forwarding-table items related to RFC2544 as control plane core to forwarding surface, and exchange chip and FPGA make
It works in coordination for forwarding surface and handles the test VPWS flows of RFC2544, can realize the surface speed forwarding of device port, ensure that and set
The forwarding performance of standby port.
Description of the drawings
Fig. 1 is that the VPWS environment of the present invention realizes the method and step flow chart of RFC2544；
Fig. 2 is the hardware connection structure figure of the present invention；
Fig. 3 is the structure diagram of the equipment of the present invention；
Fig. 4 is the first process chart of forwarding table management module of the present invention；
Fig. 5 is the FPGA processing module second processing flow charts of the present invention；
Fig. 6 is the exchange chip processing module fourth process flow chart of the present invention；
Fig. 7 is the 5th process chart of FPGA processing modules of the present invention；
Fig. 8 is the 7th process chart of exchange chip processing module of the present invention；
Fig. 9 is the 8th process chart of FPGA processing modules of the present invention.
Specific embodiment
The present invention will be further described below in conjunction with the accompanying drawings：
As shown in Figure 1, the method that the VPWS environment described in the present embodiment realizes RFC2544, including for RFC2544 actives
Give out a contract for a project at end：
Step S101, multi-core CPU does the first processing, and bag is write FPGA according to configuration；
Step S102, FPGA does second processing, according to give out a contract for a project bag length, packet sending speed and duration of giving out a contract for a project etc. of configuration, survey
Examination flow is sent to exchange chip, and VPWS instance numbers, stream ID, sequence number and timestamp are inserted into each bag；
Step S103, exchange chip does the 3rd processing, and test flow transparent transmission is gone out NNI mouthfuls of equipment.
For the processing of RFC2544 Partner：
Step S104, exchange chip does fourth process, the target MAC (Media Access Control) address of peel test flow outer layer, source MAC,
TE labels, PW labels, stamp the VLANID for representing VPWS examples in load, and test flow is sent to FPGA；
Step S105, FPGA does the 5th processing, and after exchange chip receives test flow, the VLANID peeled off in bag is used in combination
VLANID searches vlan table, encapsulates PW labels, TE labels, source MAC and target MAC (Media Access Control) address successively outside load, and
Test flow is sent to exchange chip；
Step S106, exchange chip does the 6th processing, and test flow transparent transmission is gone out NNI mouthfuls of equipment.
For RFC2544 drive end packet receivings：
Step S107, exchange chip does the 7th processing, the target MAC (Media Access Control) address of peel test flow outer layer, source MAC,
Load, is sent to FPGA by TE labels, PW labels；
Step S108, FPGA does the 8th processing, according to VPWS instance numbers, stream ID, sequence number and the time in test flow
Stamp calculates the handling capacity of the stream of each VPWS examples of RFC2544 every, delay, frame loss rate and the test parameters such as back-to-back.
As shown in Fig. 2, core of the multi-core CPU as control plane, carries the operation of entire control plane software systems, and it is raw
The various list items needed into forwarding surface, forwarding surface realize that exchange chip and FPGA forward foundation with exchange chip and FPGA
List item all write by multi-core CPU.
According to the other side of the embodiment of the present invention, the equipment that a kind of VPWS environment realizes RFC2544 is provided, is such as schemed
Shown in 3, wherein, thin arrow represents forwarding table information in figure, and block arrow represents converting flow, and the equipment includes：
Service protocol module for running Routing Protocol, LDP agreements, ARP protocol etc., will realize far-end PE equipment and this
Routing between ground PE equipment is got through, on the NNI interfaces of two PE equipment run LDP agreements, mutual phase partitioning PW labels to pair
Side.Each PE equipment also needs to the study between the P equipment of direct-connected next-hop and arrives to side mac address.Service protocol module is to this
After a little protocol data processing, by treated, business forwarding information hair message gives forwarding table management module；
For receiving the business forwarding information, the integration of these business forwarding informations is converted to for forwarding table management module
The form that exchange chip processing module and FPGA processing modules need is written to exchange chip processing module and FPGA processing moulds
Block；And according to the test information of user configuration, generation needs the data packet tested under VPWS environment, and at bag write-in FPGA
Manage module；
Exchange chip processing module after the test data bag processing of the NNI entrances to PE equipment, sends data packet
To FPGA processing modules and after FPGA processing modules receive test data bag, sent from the NNI mouths of PE equipment.It hands over
The various businesses forwarding table that chip processing module processing data packet requires to look up is changed to be write by forwarding table management module；
FPGA processing modules, for according to configuration information, actively sending test data flow and giving exchange chip processing module,
And receive the data packet that exchange chip processing module sends over and data packet is further processed, then it is then forwarded to friendship
It changes chip processing module and calculates the various test parameters of RFC2544 after receiving test flow from exchange chip processing module.
The various businesses forwarding table that FPGA processing modules processing data packet requires to look up is write by forwarding table management module；
To further appreciate that step flow that test data bag provided in an embodiment of the present invention forwards in a device, below will
It is described in detail.
In step S101, the forwarding table management module of multi-core CPU does the first processing, and information example is tested according to user configuration
Such as the uni interface of the corresponding PE equipment of VPWS examples, get corresponding VPWS examples NNI mouths and PW labels, TE labels,
The MAC Address of next-hop P equipment, and according to the test data bag target MAC (Media Access Control) address of user configuration, source MAC etc., generation needs
The data packet to be tested under VPWS environment, and bag is write FPGA processing modules.After the completion of VPWS environmental structures, forwarding table
Management module can generate the relevant list items of VPWS, such as generated in multi-core CPU in UNI inbound port attribute lists and stamp VPWS attributes
Mark and the VPNID to represent VPWS examples generate VPWS forwarding tables by key assignments of VPNID, and VPWS forwarding tables content includes NNI
Mouth and PW labels, TE labels, the IP address of next-hop P equipment.Forwarding table management module can be also generated with NNI mouthfuls and next-hop
The IP address of P equipment is the ARP table of key assignments, and content is the MAC Address of next-hop P equipment.It has been generated in advance according to these
List item, when the user configuration test information binding corresponding uni interface of VPWS examples, forwarding table management module can just be got pair
The NNI mouths and PW labels of the VPWS examples answered, TE labels, the MAC Address etc. of next-hop P equipment, generation is needed in VPWS rings
The data packet tested under border, and bag is write FPGA processing modules.Forwarding table management module does the first process flow such as Fig. 4 institutes
Show：
Step S401, the uni interface of user configuration test information binding VPWS examples；
Step S402, forwarding table management module read uni interface inbound port attribute list obtain VPWS bindings mark and
VPNID；
Step S403, forwarding table management module is using VPNID as key assignments, reads VPWS forwarding tables, obtain out NNI mouthfuls, it is next
Jump IP address, PW labels and the TE labels of P equipment；
Step S404, forwarding table management module reads ARP table using the IP address of NNI mouthfuls and next-hop P equipment as key assignments,
Obtain the MAC Address of next-hop P equipment；
Step S405, with reference to information above, forwarding table management module is further according to the test data payload package of user configuration
Target MAC (Media Access Control) address and source MAC generate the test bag under VPWS environment；
Step S406, bag is write FPGA processing modules.
In step s 102, FPGA processing modules do second processing, according to the VPWS examples of configuration, long data packet, give out a contract for a project
Rate, burst-length, length of testing speech, test data stream type, data current test enable, and VPWS examples are inserted into each bag
Number, stream ID, sequence number and timestamp etc., test flow is sent to exchange chip processing module.FPGA processing modules do second
Process flow is as shown in Figure 5：
Step S501, according to the VPWS examples of configuration, long data packet, packet sending speed, burst-length, length of testing speech, test
Data stream type, data current test enable, and VPWS instance numbers, stream ID, sequence number and timestamp are inserted into each bag；
Step S502, test flow is sent to exchange chip processing module；
In step s 103, exchange chip processing module does the 3rd processing, directly that test flow is saturating from NNI mouthfuls of PE equipment
It spreads out of, exports the outlet form for stamping the identification of exchange chip processing module before data packet by FPGA processing modules.
In step S104, for PE equipment from NNI interface test data flows, exchange chip processing module does everywhere
Reason, target MAC (Media Access Control) address, source MAC, TE labels, the PW labels of peel test flow outer layer are stamped in load and represent VPWS
Test flow is sent to FPGA processing modules by the VLANID of example.Forwarding table management module needs to write MPLS label forwarding table
To exchange chip processing module so that data traffic can remove TE labels and PW labels.The present invention supports more VPWS examples, turns
It delivers management module needs to establish into PW and the correspondence for going out PW, be realized by being inserted into VLANID in data traffic.It hands over
Changing chip processing module, to do fourth process flow as shown in Figure 6：
Step S601, PE equipment is from NNI interface test data flows；
Step S602, the target MAC (Media Access Control) address of peel test flow outer layer, source MAC, TE labels, PW labels, in load
In stamp the VLANID for representing VPWS examples；
Step S603, test flow is sent to FPGA processing modules；
In step S105, FPGA processing modules do the 5th processing, after exchange chip processing module receives test flow,
It peels the VLANID in bag off and searches vlan table with VLANID, encapsulated successively outside load and PW labels, TE labels, source
MAC Address and target MAC (Media Access Control) address, and test flow is sent to exchange chip processing module.Forwarding table management module according to
VPWS examples are established into PW and the correspondence for going out PW, can generate the vlan table write-in FPGA processing modules for representing VPWS examples,
Content is from PW labels, TE labels, source MAC and the target MAC (Media Access Control) address for needing to encapsulate when going out for passive end equipment NNI mouthfuls.
It is as shown in Figure 7 that FPGA processing modules do the 5th process flow：
Step S701, test flow is received from exchange chip processing module；
Step S702, peel the VLANID in bag off and search vlan table with VLANID, obtain outer layer target MAC (Media Access Control) address, source
MAC Address, TE labels and PW labels；
Step S703, encapsulated successively with PW labels, TE labels, source MAC and purpose MAC outside test load
Test flow is sent to exchange chip processing module by location；
In step s 106, exchange chip processing module does the 6th processing, directly that test flow is saturating from NNI mouthfuls of PE equipment
It spreads out of, exports the outlet form for stamping the identification of exchange chip processing module before data packet by FPGA processing modules.
In step s 107, PE equipment is done from NNI interface test data flows, exchange chip processing module at the 7th
Reason, test flow is sent to FPGA by target MAC (Media Access Control) address, source MAC, TE labels, the PW labels of peel test flow outer layer
Processing module.Forwarding table management module needs to write MPLS label forwarding table to exchange chip processing module so that data traffic energy
Enough remove TE labels and PW labels.It is as shown in Figure 8 that exchange chip processing module does the 7th process flow：
Step S801, PE equipment is from NNI interface test data flows；
Step S802, the target MAC (Media Access Control) address of peel test flow outer layer, source MAC, TE labels, PW labels；
Step S803, test flow is sent to FPGA processing modules.
In step S108, FPGA processing modules do the 8th processing, after exchange chip processing module receives test flow,
According to VPWS instance numbers, stream ID, sequence number and the timestamp in test flow, each VPWS examples every of RFC2544 are calculated
The handling capacity of stream, delay, frame loss rate and the test parameters such as back-to-back.FPGA processing modules do the 8th process flow such as Fig. 9 institutes
Show：
Step S901, test flow is received from exchange chip processing module；
Step S902, VPWS instance numbers, stream ID, sequence number and the timestamp in test flow, calculates RFC2544
The handling capacity of each every stream of VPWS examples, delay, frame loss rate and the test parameters such as back-to-back.
Embodiment described above is only that the preferred embodiment of the present invention is described, not to the model of the present invention
It encloses and is defined, on the premise of design spirit of the present invention is not departed from, those of ordinary skill in the art are to the technical side of the present invention
The various modifications and improvement that case is made, should all fall within the scope of protection of the present invention.
Claims (6)
1. a kind of method that VPWS environment realizes RFC2544, it is characterised in that：Specifically include following steps：
Give out a contract for a project for RFC2544 drive ends：
Step 1, multi-core CPU does the first processing, tests the corresponding uni interface of information VPWS examples according to user configuration, gets
NNI mouths and PW labels, TE labels, the MAC Address of next-hop P equipment of corresponding VPWS examples, and according to user configuration
Test data bag target MAC (Media Access Control) address, source MAC, generation needs the data packet tested under VPWS environment, and bag is write
FPGA；
Step 2, FPGA does second processing, according to the VPWS examples of configuration, long data packet, packet sending speed, burst-length, test when
Length, test data stream type, data current test enable, and VPWS instance numbers, stream ID, sequence number and time are inserted into each bag
Test flow, is sent to exchange chip by stamp；
Step 3, exchange chip does the 3rd processing, and directly NNI mouthfuls of transparent transmissions of test flow slave device are gone out；
For RFC2544 Partner：
Step 4, equipment is from NNI interface test data flows, and exchange chip does fourth process, peel test flow outer layer
Purpose MAC, source MAC, TE label, PW labels, the VLANID for representing VPWS examples is stamped in load, test flow is sent to
FPGA；
Step 5, FPGA does the 5th processing, after exchange chip receives test flow, peels the VLANID in bag off and uses VLANID
Vlan table is searched, encapsulates PW labels, TE labels, source MAC and target MAC (Media Access Control) address successively outside load, and test
Flow is sent to exchange chip；Multi-core CPU can first generate the vlan table write-in for representing VPWS examples according to the environment of VPWS
FPGA, content are from PW labels, TE labels, source MAC and the purpose MAC for needing to encapsulate when going out for passive end equipment NNI mouthfuls
Address；
Step 6, exchange chip does the 6th processing, and directly NNI mouthfuls of transparent transmissions of test flow slave device are gone out；
For RFC2544 drive end packet receivings：
Step 7, equipment is from NNI interface test data flows, and exchange chip does the 7th processing, peel test flow outer layer
Test flow, is sent to FPGA by purpose MAC, source MAC, TE label, PW labels；
Step 8, FPGA do the 8th processing, from exchange chip receive test flow after, according to test flow in VPWS instance numbers,
Stream ID, sequence number and timestamp calculate the test parameter of every stream of each VPWS examples of RFC2544.
2. the method that VPWS environment according to claim 1 realizes RFC2544, it is characterised in that：The step 1 further includes
After the completion of VPWS environmental structures, forwarding table management module can generate the relevant list items of VPWS, and UNI is generated in multi-core CPU and is entered
VPWS attribute marks and the VPNID to represent VPWS examples are stamped in port attribute table, VPWS forwardings are generated by key assignments of VPNID
Table, VPWS forwarding tables content include NNI mouthfuls and PW labels, TE labels, the IP address of next-hop P equipment；Forwarding table manages mould
Block can also generate the ARP table using the IP address of NNI mouthfuls and next-hop P equipment as key assignments, content for next-hop P equipment MAC
Location, the list item generated in advance according to these, when the corresponding uni interface of user configuration test information binding VPWS examples,
Forwarding table management module is with regard to that can get the NNI mouths of corresponding VPWS examples and PW labels, TE labels, next-hop P equipment
MAC Address, generation needs the data packet tested under VPWS environment, and bag is write FPGA processing modules.
3. the method that VPWS environment according to claim 2 realizes RFC2544, it is characterised in that：The step 4 further includes
Forwarding table management module needs to write MPLS label forwarding table to exchange chip processing module so that data traffic can remove TE marks
Label and PW labels.
4. the method that VPWS environment according to claim 3 realizes RFC2544, it is characterised in that：The step 7 further includes
Forwarding table management module needs to write MPLS label forwarding table to exchange chip processing module so that data traffic can remove TE marks
Label and PW labels.
5. the method that the VPWS environment according to claim 1-4 any one realizes RFC2544, it is characterised in that：It is described
Test parameter is handling capacity, retardation, frame loss rate and is worth back-to-back in step 8.
6. a kind of equipment that VPWS environment realizes RFC2544, it is characterised in that：Including service protocol module, forwarding table management mould
Block, exchange chip processing module and FPGA processing modules；
Service protocol module for running Routing Protocol, LDP agreements, ARP protocol, will realize that far-end PE equipment is set with local PE
Routing between standby is got through, and runs LDP agreements on the NNI interfaces of two PE equipment, and mutual phase partitioning PW labels are to other side, each
PE equipment also needs to the study between direct-connected P equipment and arrives to side mac address, and service protocol module is to the processing of these protocol datas
Afterwards, by treated, business forwarding information hair message gives forwarding table management module；
The integration of these business forwarding informations for receiving the business forwarding information, is converted to exchange by forwarding table management module
The form that chip processing module and FPGA processing modules need, is written to exchange chip processing module and FPGA processing modules；And
According to the test information of user configuration, generation needs the data packet tested under VPWS environment, and bag write-in FPGA processing moulds
Block；
Exchange chip processing module after the test data bag processing of the NNI entrances to PE equipment, is sent to data packet
FPGA processing modules and after FPGA processing modules receive test data bag, send from the NNI mouths of PE equipment, exchange
The various businesses forwarding table that chip processing module processing data packet requires to look up is write by forwarding table management module；
FPGA processing modules, for according to configuration information, actively send test data flow to exchange chip processing module and
It receives the data packet that exchange chip processing module sends over and data packet is further processed, be then then forwarded to exchange core
Piece processing module and from exchange chip processing module receive test flow after calculate the various test parameters of RFC2544, FPGA
The various businesses forwarding table that processing module processing data packet requires to look up is write by forwarding table management module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711324839.0A CN108075949B (en) | 2017-12-13 | 2017-12-13 | Method and equipment for realizing RFC2544 in VPWS environment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711324839.0A CN108075949B (en) | 2017-12-13 | 2017-12-13 | Method and equipment for realizing RFC2544 in VPWS environment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108075949A true CN108075949A (en) | 2018-05-25 |
| CN108075949B CN108075949B (en) | 2021-03-23 |
Family
ID=62158338
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711324839.0A Active CN108075949B (en) | 2017-12-13 | 2017-12-13 | Method and equipment for realizing RFC2544 in VPWS environment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108075949B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111490907A (en) * | 2019-01-25 | 2020-08-04 | 华为技术有限公司 | Method and device for determining VX L AN network performance parameters |
| CN111683307A (en) * | 2020-05-22 | 2020-09-18 | 烽火通信科技股份有限公司 | Method and system for service access under OLT (optical line terminal) multi-stage exchange |
| CN113037859A (en) * | 2021-03-24 | 2021-06-25 | 新华三技术有限公司 | Session information management method, device, exchange equipment and medium |
| CN113765862A (en) * | 2020-06-05 | 2021-12-07 | 腾讯科技(成都)有限公司 | Method, device and equipment for testing game protocol and computer readable storage medium |
| WO2022056798A1 (en) * | 2020-09-18 | 2022-03-24 | Intel Corporation | Improving remote traffic performance on cluster-aware processors |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090198483A1 (en) * | 2008-02-06 | 2009-08-06 | Sezen Uysal | Apparatus and method for network emulation by using hardware accelerated network interface cards |
| CN102143080A (en) * | 2011-03-29 | 2011-08-03 | 福建星网锐捷网络有限公司 | Label allocation method, system and device for multi-protocol label switching network |
| US20120207171A1 (en) * | 2007-08-10 | 2012-08-16 | Hamid Ould Brahim | Method and Apparatus for Interworking VPLS and Ethernet Networks |
| CN103179036A (en) * | 2011-12-21 | 2013-06-26 | 上海博达数据通信有限公司 | Method for achieving Linktrace of multi-protocol label switching-transmission parameter (MPLS-TP) operation, administration and maintenance (OAM) on basis of field programmable gata array (FPGA) |
| CN103490969A (en) * | 2013-09-17 | 2014-01-01 | 烽火通信科技股份有限公司 | System and method for achieving VPWS redundancy protection rapid convergence |
| CN203708279U (en) * | 2013-12-31 | 2014-07-09 | 唯栎电子科技（上海）有限公司 | Special-purpose management type industrial Ethernet switch device for rail traffic |
| CN105591839A (en) * | 2015-12-23 | 2016-05-18 | 浪潮集团有限公司 | Device, method and system of testing network exchange chip |
-
2017
- 2017-12-13 CN CN201711324839.0A patent/CN108075949B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120207171A1 (en) * | 2007-08-10 | 2012-08-16 | Hamid Ould Brahim | Method and Apparatus for Interworking VPLS and Ethernet Networks |
| US20090198483A1 (en) * | 2008-02-06 | 2009-08-06 | Sezen Uysal | Apparatus and method for network emulation by using hardware accelerated network interface cards |
| CN102143080A (en) * | 2011-03-29 | 2011-08-03 | 福建星网锐捷网络有限公司 | Label allocation method, system and device for multi-protocol label switching network |
| CN103179036A (en) * | 2011-12-21 | 2013-06-26 | 上海博达数据通信有限公司 | Method for achieving Linktrace of multi-protocol label switching-transmission parameter (MPLS-TP) operation, administration and maintenance (OAM) on basis of field programmable gata array (FPGA) |
| CN103490969A (en) * | 2013-09-17 | 2014-01-01 | 烽火通信科技股份有限公司 | System and method for achieving VPWS redundancy protection rapid convergence |
| CN203708279U (en) * | 2013-12-31 | 2014-07-09 | 唯栎电子科技（上海）有限公司 | Special-purpose management type industrial Ethernet switch device for rail traffic |
| CN105591839A (en) * | 2015-12-23 | 2016-05-18 | 浪潮集团有限公司 | Device, method and system of testing network exchange chip |
Non-Patent Citations (2)
| Title |
|---|
| WOUTER TAVERNIER*, DIMITRI PAPADIMITRIOU†, DIDIER COLLE*: "Emulation of GMPLS-controlled Ethernet Label Switching", 《2009 5TH INTERNATIONAL CONFERENCE ON TESTBEDS AND RESEARCH INFRASTRUCTURES FOR THE DEVELOPMENT OF NETWORKS & COMMUNITIES AND WORKSHOPS》 * |
| 金燕，陈佳彬，陈尔言，王卫静: "基于RFC2544的千兆以太网性能测试的实现", 《浙江工业大学学报》 * |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111490907A (en) * | 2019-01-25 | 2020-08-04 | 华为技术有限公司 | Method and device for determining VX L AN network performance parameters |
| CN111490907B (en) * | 2019-01-25 | 2021-10-15 | 华为技术有限公司 | Method and device for determining VXLAN network performance parameters |
| CN111683307A (en) * | 2020-05-22 | 2020-09-18 | 烽火通信科技股份有限公司 | Method and system for service access under OLT (optical line terminal) multi-stage exchange |
| CN111683307B (en) * | 2020-05-22 | 2022-05-20 | 烽火通信科技股份有限公司 | Method and system for accessing service under OLT (optical line terminal) multi-stage exchange |
| CN113765862A (en) * | 2020-06-05 | 2021-12-07 | 腾讯科技(成都)有限公司 | Method, device and equipment for testing game protocol and computer readable storage medium |
| CN113765862B (en) * | 2020-06-05 | 2024-02-09 | 腾讯科技(成都)有限公司 | Game protocol testing method, device, equipment and computer readable storage medium |
| WO2022056798A1 (en) * | 2020-09-18 | 2022-03-24 | Intel Corporation | Improving remote traffic performance on cluster-aware processors |
| CN113037859A (en) * | 2021-03-24 | 2021-06-25 | 新华三技术有限公司 | Session information management method, device, exchange equipment and medium |
| CN113037859B (en) * | 2021-03-24 | 2022-04-22 | 新华三技术有限公司 | Session information management method, device, exchange equipment and medium |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108075949B (en) | 2021-03-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108075949A (en) | A kind of VPWS environment realizes the method and apparatus of RFC2544 | |
| CN104243270B (en) | A kind of method and apparatus for establishing tunnel | |
| CN104380667B (en) | The method for routing and equipment of a kind of data message | |
| CN104022953B (en) | Message forwarding method and device based on open flows Openflow | |
| CN101076972B (en) | Obtaining path information related to a virtual private lan services (vpls) based network | |
| CN109861926A (en) | The transmission of message, processing method and processing device, PE node, node | |
| CN100542127C (en) | A kind of method of realizing group broadcasting based on multiservice transport platform | |
| CN103391296B (en) | A kind of controller, transponder and Path Setup method and system | |
| CN107181663A (en) | A kind of message processing method, relevant device and computer-readable recording medium | |
| CN101110745A (en) | Method, device and system for engaging second layer network and third layer network | |
| CN100555999C (en) | A kind of method and apparatus of realizing edge-to-edge pseudo-line simulation | |
| WO2008092357A1 (en) | A method and device for establishing a pseudo wire tunnel and transmitting message using it | |
| CN104365066B (en) | Method and apparatus for ether Virtual Private Network | |
| CN108040135B (en) | Method and device for VPWS message to pass through three-layer IP network | |
| CN104092684B (en) | A kind of OpenFlow agreements support VPN method and apparatus | |
| CN107888401A (en) | A kind of method and system of the monitoring regarding networked terminals cpu busy percentage in real time | |
| CN105141538B (en) | A kind of across a network pile system and its processing method to message | |
| CN110392044A (en) | A kind of information transferring method and device based on view networking | |
| CN106961400A (en) | A kind of method and system for realizing cloud platform virtual port mirror image | |
| CN109788369A (en) | Terminal control method and device | |
| CN103841026B (en) | VPN route managing system and method of router IP protocol stack | |
| CN105429901B (en) | Uplink data packet forwarding method and device, downlink data packet forwarding method and device | |
| CN103873369B (en) | Gateway and method for supporting interaction of heterogeneous network | |
| CN102710510B (en) | Information processing method, apparatus and system | |
| Burakowski et al. | Virtualized network infrastructure supporting co-existence of Parallel Internets |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |