CN108075949B - Method and equipment for realizing RFC2544 in VPWS environment - Google Patents

Method and equipment for realizing RFC2544 in VPWS environment Download PDF

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CN108075949B
CN108075949B CN201711324839.0A CN201711324839A CN108075949B CN 108075949 B CN108075949 B CN 108075949B CN 201711324839 A CN201711324839 A CN 201711324839A CN 108075949 B CN108075949 B CN 108075949B
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vpws
test
fpga
rfc2544
processing module
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CN108075949A (en
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魏立军
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Anhui Wantong Post And Telecommunications Co ltd
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Anhui Wantong Post And Telecommunications Co ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/74—Address processing for routing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
    • H04L43/0823—Errors, e.g. transmission errors
    • H04L43/0829—Packet loss
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
    • H04L43/0852—Delays

Abstract

A method and apparatus for realizing RFC2544 in VPWS environment, including the core that the multicore CPU is regarded as the control surface, run many control surface agreement, produce and transmit surface VPWS and RFC2544 various table entries that need while processing the data packet, the multicore CPU is also used for producing the data packet that RFC2544 initiative end tests; the forwarding plane is realized by a switching chip and an FPGA (field programmable gate array), and the switching chip and the FPGA are matched with each other to process an RFC2544 test data packet in a VPWS (virtual private Web services) environment; for an RFC2544 active terminal sending packet, a multi-core CPU generates a test data packet and writes the test data packet into an FPGA (field programmable gate array), the FPGA sends test flow to a switching chip, and the switching chip sends the test flow out; for the RFC2544 passive end, after packet receiving processing of the switching chip, sending the test flow to the FPGA, after processing of the FPGA, sending the test flow to the switching chip again, and sending the test flow out by the switching chip; for the packet receiving of the active end of the RFC2544, after the packet receiving processing of the switching chip, the testing flow is sent to the FPGA, and the FPGA performs the final calculation of the RFC2544 testing parameters on the testing flow; the line speed forwarding of the equipment port can be realized, and the forwarding performance of the equipment port is ensured.

Description

Method and equipment for realizing RFC2544 in VPWS environment
Technical Field
The invention relates to the technical field of computer network data communication, in particular to a method and equipment for realizing RFC2544 in a VPWS environment.
Background
Vpws (virtual Private Wire service), which is built on the infrastructure of MPLS network, provides high-speed two-layer transparent transmission between a pair of ports of two routers, and can transparently transmit the original ethernet packet of the local PE device to the remote PE device, and is a two-layer VPN protocol.
The RFC2544 protocol is an international standard proposed by the RFC organization for evaluating network-connected devices (firewalls, IDS, Switch, etc.). The method mainly provides more detailed specification for the specific test method of the performance evaluation parameters defined in RFC1242 and the submission form of the results. Many parameters for testing different network devices are specified in RFC2544, mainly including 4 most important parameters, namely Throughput (Throughput), packet loss Rate (Lost Rate), delay (Latency), and Back-to-Back (Back-to-Back). The throughput rate reflects the maximum data traffic that the device under test can handle (without losing packets); the packet loss rate reflects the capability of the tested device to bear a specific load; the time delay reflects the speed of the tested equipment for processing the data packet; the back-to-back reflects the capability of the device under test to process bursty data (data buffering capability).
The most basic and commonly used service of a PTN (Packet Transport Network) device is VPWS, and the Network access authentication of the PTN device must pass RFC2544 performance test under VPWS networking. At present, a switching chip, such as a broadcom or Marvel, which is mainstream in the industry does not have the capability of generating RFC2544 test data stream, if the test data stream is generated by CPU soft forwarding, although the code is flexible, the forwarding capability is too poor, the port cannot be used for line speed, and the delay error of the data stream measured by the CPU is large.
Therefore, there is a need to provide a method and apparatus for implementing RFC2544 in a VPWS environment, and to ensure forwarding performance, a port implements wire-speed forwarding.
Disclosure of Invention
According to the method and the device for realizing the RFC2544 in the VPWS environment, the multi-core CPU is used as a control surface core to write various forwarding table items related to the VPWS and the RFC2544 to a forwarding surface, and the switching chip and the FPGA are used as the forwarding surface to be matched with each other to process the VPWS flow for testing the RFC2544, so that the line speed forwarding of a device port can be realized, and the forwarding performance of the device port is ensured.
In order to achieve the purpose, the invention adopts the following technical scheme:
a method for realizing RFC2544 in VPWS environment comprises a multi-core CPU as the core of a control surface, running a plurality of control surface protocols, generating various table items of VPWS and RFC2544 required by a forwarding surface for processing a data packet, wherein the multi-core CPU is also used for generating the data packet tested by an active end of the RFC 2544; the forwarding plane is realized by a switching chip and an FPGA (field programmable gate array), and the switching chip and the FPGA are matched with each other to process an RFC2544 test data packet in a VPWS (virtual private Web services) environment; for an RFC2544 active terminal sending packet, a multi-core CPU generates a test data packet and writes the test data packet into an FPGA (field programmable gate array), the FPGA sends test flow to a switching chip, and the switching chip sends the test flow out; for the RFC2544 passive end, after packet receiving processing of the switching chip, sending the test flow to the FPGA, after processing of the FPGA, sending the test flow to the switching chip again, and sending the test flow out by the switching chip; for the packet receiving of the active end of the RFC2544, after the packet receiving processing of the switching chip, the testing flow is sent to the FPGA, and the FPGA performs the final calculation of the RFC2544 testing parameters on the testing flow; the method specifically comprises the following steps:
for RFC2544 primary side packet transmission:
step 1, a multi-core CPU performs first processing, acquires an NNI port and PW labels of corresponding VPWS instances, TE labels and MAC addresses of next-hop P equipment according to user configuration test information such as UNI interfaces corresponding to the VPWS instances, generates a data packet needing to be tested in a VPWS environment according to destination MAC addresses, source MAC addresses and the like of test data packets configured by a user, and writes the packet into an FPGA;
step 2, the FPGA carries out second processing, and a VPWS instance number, a stream ID, a serial number, a time stamp and the like are inserted into each packet according to the configured VPWS instance, the data packet length, the packet sending rate, the burst length, the test duration, the test data stream type, the data stream test enabling and the like, and test flow is sent to the exchange chip;
and 3, performing third processing by the exchange chip, and directly transmitting the test flow out from the NNI port of the equipment.
For RFC2544 passive end:
step 4, the equipment receives the test data flow from the NNI, the exchange chip carries out fourth processing, a target MAC address, a source MAC address, a TE label and a PW label on the outer layer of the test flow are stripped, a VLANID representing a VPWS example is marked in a load, and the test flow is sent to the FPGA;
step 5, the FPGA carries out fifth processing, after receiving the test flow from the exchange chip, the VLANID in the packet is stripped, the VLAN table is searched by the VLANID, a PW label, a TE label, a source MAC address and a destination MAC address are sequentially packaged outside the load, and the test flow is sent to the exchange chip; the multi-core CPU generates a VLAN table representing a VPWS instance to be written into the FPGA according to the environment of the VPWS, and the content is a PW label, a TE label, a source MAC address and a destination MAC address which need to be encapsulated when the VPWS goes out from an NNI port of passive end equipment;
and 6, the exchange chip carries out sixth processing and directly transmits the test flow out from the NNI port of the equipment.
For RFC2544 active end receive packet:
step 7, the equipment receives the test data flow from the NNI, the exchange chip performs seventh processing, a target MAC address, a source MAC address, a TE label and a PW label on the outer layer of the test flow are stripped, and the test flow is sent to the FPGA;
and 8, performing eighth processing by the FPGA, and calculating test parameters such as throughput, delay, frame loss rate, back-to-back and the like of each flow of each VPWS instance in RFC2544 according to the VPWS instance number, the flow ID, the sequence number and the timestamp in the test flow after receiving the test flow from the switching chip.
An apparatus for implementing RFC2544 in a VPWS environment, the apparatus comprising:
and the service protocol module is used for operating a routing protocol, an LDP protocol, an ARP protocol and the like, operating the LDP protocol on NNI interfaces of the two PE devices and mutually distributing PW labels to the opposite side to realize routing communication between the remote PE device and the local PE device. Each PE device also needs to learn the MAC address of the other party with the directly connected P device. After the service protocol module processes the protocol data, the service protocol module sends the processed service forwarding information to the forwarding table management module;
the forwarding table management module is used for receiving the service forwarding information, integrating and converting the service forwarding information into a format required by the switching chip processing module and the FPGA processing module, and writing the format into the switching chip processing module and the FPGA processing module; generating a data packet to be tested in the VPWS environment according to the test information configured by the user, and writing the packet into the FPGA processing module;
and the switching chip processing module is used for processing the test data packet at the NNI inlet of the PE equipment, sending the data packet to the FPGA processing module, and sending the test data packet out from the NNI inlet of the PE equipment after receiving the test data packet from the FPGA processing module. The switching chip processing module processes various service forwarding tables to be searched for by the data packet and writes the various service forwarding tables into the forwarding table management module;
and the FPGA processing module is used for actively sending the test data flow to the switching chip processing module according to the configuration information, receiving the data packet sent by the switching chip processing module, further processing the data packet, then sending the data packet to the switching chip processing module, and calculating various test parameters of RFC2544 after receiving the test flow from the switching chip processing module. Various service forwarding tables to be searched for processing the data packets by the FPGA processing module are written in by the forwarding table management module;
as described above, for RFC2544 primary peer packet transmission:
in step 1, a forwarding table management module of a multi-core CPU performs a first process, acquires an NNI port of a corresponding VPWS instance, a PW label, a TE label, and an MAC address of a next-hop P device according to user configuration test information, for example, a UNI interface of a PE device corresponding to the VPWS instance, generates a data packet to be tested in the VPWS environment according to a destination MAC address, a source MAC address, and the like of a test data packet configured by a user, and writes the packet into an FPGA processing module. After the VPWS environment is built, the forwarding table management module generates a VPWS-related entry, for example, a VPWS attribute flag and a VPNID representing a VPWS instance are marked on a UNI ingress port attribute table generated in the multi-core CPU, and a VPWS forwarding table is generated with the VPNID as a key value, where the content of the VPWS forwarding table includes an NNI port, a PW label, a TE label, and an IP address of a next hop P device. The forwarding table management module also generates an ARP table with the IP addresses of the NNI port and the next hop P device as key values, and the content of the ARP table is the MAC address of the next hop P device. According to the table entries which are generated in advance, when a user configures the UNI interface corresponding to the test information binding VPWS instance, the forwarding table management module can acquire the NNI port, the PW label, the TE label, the MAC address of the next-hop P device and the like of the corresponding VPWS instance, generate a data packet which needs to be tested in the VPWS environment, and write the packet into the FPGA processing module.
In step 2, the FPGA processing module performs a second process, and inserts a VPWS instance number, a stream ID, a serial number, a timestamp, and the like into each packet according to the configured VPWS instance, a data packet length, a packet sending rate, a burst length, a test duration, a test data stream type, a data stream test enable, and the like, and sends the test traffic to the switch chip processing module.
And in the step 3, the exchange chip processing module carries out third processing and directly transmits the test flow out from the NNI port of the PE equipment.
For RFC2544 passive end:
in step 4, the PE device receives the test data traffic from the NNI interface, the switching chip processing module performs a fourth process, peels off the destination MAC address, the source MAC address, the TE tag, and the PW tag of the outer layer of the test traffic, marks the vlan id representing the VPWS instance in the load, and sends the test traffic to the FPGA processing module. The forwarding table management module needs to write the MPLS label forwarding table to the switching chip processing module, so that the data traffic can be stripped of the TE label and the PW label. The invention supports multiple VPWS examples, the forwarding table management module needs to establish the corresponding relation between the PW input and the PW output, and the forwarding table management module is realized by inserting the VLANID into the data flow.
In step 5, the FPGA processing module performs a fifth process, and after receiving the test traffic from the switch chip processing module, strips the VLAN id in the packet and searches the VLAN table using the VLAN id, sequentially encapsulates the PW label, the TE label, the source MAC address, and the destination MAC address outside the load, and sends the test traffic to the switch chip processing module. The forwarding table management module establishes a corresponding relation between an incoming PW and an outgoing PW according to a VPWS example, generates a VLAN table representing the VPWS example, writes the VLAN table into the FPGA processing module, and has contents of a PW label, a TE label, a source MAC address and a destination MAC address which need to be encapsulated when the VPWS example goes out from an NNI port of passive end equipment;
and 6, performing sixth processing by the switching chip processing module, and directly transmitting the test flow from the NNI port of the PE equipment.
For RFC2544 active end receive packet:
in step 7, the PE device receives the test data traffic from the NNI interface, the switching chip processing module performs a seventh process, strips the destination MAC address, the source MAC address, the TE tag, and the PW tag of the outer layer of the test traffic, and sends the test traffic to the FPGA processing module. The forwarding table management module needs to write the MPLS label forwarding table to the switching chip processing module, so that the data traffic can be stripped of the TE label and the PW label.
In step 8, the FPGA processing module performs an eighth process, and after receiving the test traffic from the switch chip processing module, calculates test parameters such as throughput, delay, frame loss rate, back-to-back, and the like of each flow of each VPWS instance in RFC2544 according to the VPWS instance number, the flow ID, the sequence number, and the timestamp in the test traffic.
The invention has the beneficial effects that: in the scheme of the invention, the multi-core CPU is used as the core of the control plane to generate various table entries required by the forwarding plane. The forwarding plane is realized by a switching chip and an FPGA, and the table entries of the forwarding basis of the switching chip and the FPGA are written by the multi-core CPU. For the RFC2544 active terminal to send a packet, the multi-core CPU performs first processing and writes the packet into the FPGA according to configuration; the FPGA carries out second processing, sends the test flow to the switching chip according to the configured packet sending length, the packet sending rate, the packet sending duration and the like, and inserts a VPWS instance number, a flow ID, a serial number and a timestamp into each packet; and the exchange chip performs third processing to transmit the test flow out of the NNI port of the equipment. For the RFC2544 passive end, the exchange chip carries out fourth processing, a target MAC address, a source MAC address, a TE label and a PW label of the outer layer of the test flow are peeled off, a VLANID representing a VPWS example is marked in the load, and the test flow is sent to the FPGA; writing the VLAN table into the FPGA by the multi-core CPU, wherein the contents are PW label, TE label, source MAC address and destination MAC address; the FPGA carries out fifth processing, after receiving the test flow from the exchange chip, the VLANID in the packet is stripped, the VLAN table is searched by the VLANID, a PW label, a TE label, a source MAC address and a destination MAC address are sequentially packaged outside the load, and the test flow is sent to the exchange chip; and the exchange chip carries out sixth processing and transmits the test flow out of the NNI port of the equipment. For the packet receiving of the active end of the RFC2544, the switching chip performs seventh processing, peels off a target MAC address, a source MAC address, a TE label and a PW label of the outer layer of the test flow and sends the load to the FPGA; and performing eighth processing by the FPGA, and calculating test parameters of throughput, delay, frame loss rate, back-to-back and the like of each flow of each VPWS instance in the RFC2544 according to the VPWS instance number, the flow ID, the sequence number and the timestamp in the test flow. According to the invention, the multi-core CPU is used as a control surface core to write various forwarding table items related to VPWS and RFC2544 to the forwarding surface, the switching chip and the FPGA are used as the forwarding surfaces to be matched with each other to process the VPWS flow test of the RFC2544, the linear speed forwarding of the equipment port can be realized, and the forwarding performance of the equipment port is ensured.
Drawings
FIG. 1 is a flow chart of the method steps for implementing RFC2544 in VPWS environment according to the present invention;
FIG. 2 is a diagram of the hardware connection architecture of the present invention;
FIG. 3 is a block diagram of the apparatus of the present invention;
FIG. 4 is a flow chart of a first process of a forwarding table management module according to the present invention;
FIG. 5 is a second process flow diagram of the FPGA processing module of the present invention;
FIG. 6 is a fourth processing flow diagram of the processing module of the switch chip according to the present invention;
FIG. 7 is a fifth process flow diagram of the FPGA processing module of the present invention;
FIG. 8 is a seventh processing flow diagram of a switch chip processing module of the present invention;
fig. 9 is an eighth processing flow diagram of the FPGA processing module of the present invention.
Detailed Description
The invention is further described below with reference to the accompanying drawings:
as shown in fig. 1, the method for implementing RFC2544 in the VPWS environment according to this embodiment includes, for RFC2544, sending a packet at the active end:
s101, a multi-core CPU performs first processing and writes a packet into an FPGA according to configuration;
step S102, the FPGA carries out second processing, the test flow is sent to a switching chip according to the configured packet sending length, the packet sending rate, the packet sending duration and the like, and a VPWS instance number, a flow ID, a serial number and a timestamp are inserted into each packet;
and step S103, the exchange chip performs third processing to transmit the test flow out of the NNI port of the equipment.
For RFC2544 passive end processing:
step S104, the exchange chip carries out fourth processing, a target MAC address, a source MAC address, a TE label and a PW label on the outer layer of the test flow are stripped, a VLANID representing a VPWS example is marked in the load, and the test flow is sent to the FPGA;
step S105, the FPGA carries out fifth processing, after receiving the test flow from the exchange chip, the VLANID in the packet is stripped, the VLAN table is searched by the VLANID, a PW label, a TE label, a source MAC address and a destination MAC address are sequentially packaged outside the load, and the test flow is sent to the exchange chip;
and step S106, the exchange chip carries out sixth processing to transmit the test flow out of the NNI port of the equipment.
For RFC2544 active end receive packet:
step S107, the exchange chip carries out seventh processing, a target MAC address, a source MAC address, a TE label and a PW label on the outer layer of the test flow are stripped, and the load is sent to the FPGA;
and step S108, performing eighth processing by the FPGA, and calculating test parameters such as throughput, delay, frame loss rate, back-to-back and the like of each stream of each VPWS instance of RFC2544 according to the VPWS instance number, the stream ID, the sequence number and the timestamp in the test flow.
As shown in fig. 2, the multicore CPU is used as a core of the control plane, and carries the operation of the whole control plane software system, and generates various entries required by the forwarding plane, where the forwarding plane is implemented by the switching chip and the FPGA in cooperation, and the entries according to the forwarding of the switching chip and the FPGA are written by the multicore CPU.
According to another aspect of the embodiments of the present invention, there is provided an apparatus for implementing RFC2544 in a VPWS environment, as shown in fig. 3, where thin arrows in the diagram represent forwarding table information, and thick arrows represent forwarding traffic, the apparatus including:
and the service protocol module is used for operating a routing protocol, an LDP protocol, an ARP protocol and the like, operating the LDP protocol on NNI interfaces of the two PE devices and mutually distributing PW labels to the opposite side to realize routing communication between the remote PE device and the local PE device. Each PE device also needs to learn the MAC address of the other party with the P device directly connected to the next hop. After the service protocol module processes the protocol data, the service protocol module sends the processed service forwarding information to the forwarding table management module;
the forwarding table management module is used for receiving the service forwarding information, integrating and converting the service forwarding information into a format required by the switching chip processing module and the FPGA processing module, and writing the format into the switching chip processing module and the FPGA processing module; generating a data packet to be tested in the VPWS environment according to the test information configured by the user, and writing the packet into the FPGA processing module;
and the switching chip processing module is used for processing the test data packet at the NNI inlet of the PE equipment, sending the data packet to the FPGA processing module, and sending the test data packet out from the NNI inlet of the PE equipment after receiving the test data packet from the FPGA processing module. The switching chip processing module processes various service forwarding tables to be searched for by the data packet and writes the various service forwarding tables into the forwarding table management module;
and the FPGA processing module is used for actively sending the test data flow to the switching chip processing module according to the configuration information, receiving the data packet sent by the switching chip processing module, further processing the data packet, then sending the data packet to the switching chip processing module, and calculating various test parameters of RFC2544 after receiving the test flow from the switching chip processing module. Various service forwarding tables to be searched for processing the data packets by the FPGA processing module are written in by the forwarding table management module;
to further understand the flow of the steps for forwarding the test packet in the device according to the embodiment of the present invention, the following description will be made in detail.
In step S101, a forwarding table management module of the multi-core CPU performs a first process, acquires an NNI port and a PW label of a corresponding VPWS instance, a TE label of the VPWS instance, and an MAC address of a next-hop P device according to user configuration test information, for example, a UNI interface of a PE device corresponding to the VPWS instance, and generates a data packet to be tested in the VPWS environment according to a destination MAC address, a source MAC address, and the like of the test data packet configured by the user, and writes the packet into the FPGA processing module. After the VPWS environment is built, the forwarding table management module generates a VPWS-related entry, for example, a VPWS attribute flag and a VPNID representing a VPWS instance are marked on a UNI ingress port attribute table generated in the multi-core CPU, and a VPWS forwarding table is generated with the VPNID as a key value, where the content of the VPWS forwarding table includes an NNI port, a PW label, a TE label, and an IP address of a next hop P device. The forwarding table management module also generates an ARP table with the IP addresses of the NNI port and the next hop P device as key values, and the content of the ARP table is the MAC address of the next hop P device. According to the table entries which are generated in advance, when a user configures the UNI interface corresponding to the test information binding VPWS instance, the forwarding table management module can acquire the NNI port, the PW label, the TE label, the MAC address of the next-hop P device and the like of the corresponding VPWS instance, generate a data packet which needs to be tested in the VPWS environment, and write the packet into the FPGA processing module. Fig. 4 shows a first processing flow performed by the forwarding table management module:
step S401, configuring a UNI interface of the test information binding VPWS instance by a user;
step S402, the forwarding table management module reads a UNI interface input port attribute table to acquire a VPWS binding mark and a VPNID;
step S403, the forwarding table management module reads the VPWS forwarding table by taking the VPNID as a key value, and acquires an NNI (network interface), an IP (Internet protocol) address of next hop P (peer-to-peer) equipment, a PW (pseudo wire) label and a TE (traffic engineering) label;
step S404, the forwarding table management module reads an ARP table by taking the IP addresses of the NNI port and the next hop P device as key values to obtain the MAC address of the next hop P device;
step S405, combining the above information, the forwarding table management module generates a test packet under VPWS environment according to the destination MAC address and the source MAC address of the test data packet load configured by the user;
and step S406, writing the packet into the FPGA processing module.
In step S102, the FPGA processing module performs a second process, inserts a VPWS instance number, a stream ID, a sequence number, a timestamp, and the like into each packet according to the configured VPWS instance, a packet length, a packet sending rate, a burst length, a test duration, a test data stream type, a data stream test enable, and the like, and sends the test traffic to the switch chip processing module. The second processing flow of the FPGA processing module is shown in fig. 5:
step S501, inserting a VPWS instance number, a stream ID, a sequence number and a timestamp into each packet according to a configured VPWS instance, a data packet length, a packet sending rate, a burst length, a test duration, a test data stream type, data stream test enabling and the like;
step S502, sending the test flow to a switching chip processing module;
in step S103, the switch chip processing module performs a third process to directly transmit the test traffic from the NNI port of the PE device, and the FPGA processing module marks an outlet format identified by the switch chip processing module on the front of the data packet at the outlet.
In step S104, the PE device receives the test data traffic from the NNI interface, the switching chip processing module performs a fourth process, strips the destination MAC address, the source MAC address, the TE tag, and the PW tag of the outer layer of the test traffic, marks the vlan id representing the VPWS instance in the load, and sends the test traffic to the FPGA processing module. The forwarding table management module needs to write the MPLS label forwarding table to the switching chip processing module, so that the data traffic can be stripped of the TE label and the PW label. The invention supports multiple VPWS examples, the forwarding table management module needs to establish the corresponding relation between the PW input and the PW output, and the forwarding table management module is realized by inserting the VLANID into the data flow. Fig. 6 shows a fourth processing flow performed by the switch chip processing module:
step S601, the PE equipment receives test data flow from the NNI;
step S602, stripping a destination MAC address, a source MAC address, a TE label and a PW label of an outer layer of the test flow, and marking a VLANID representing a VPWS example in the load;
step S603, sending the test flow to an FPGA processing module;
in step S105, the FPGA processing module performs a fifth process, and after receiving the test traffic from the switching chip processing module, strips the VLAN id in the packet and searches the VLAN table using the VLAN id, sequentially encapsulates the PW label, the TE label, the source MAC address, and the destination MAC address outside the load, and sends the test traffic to the switching chip processing module. The forwarding table management module establishes a corresponding relation between the incoming PW and the outgoing PW according to the VPWS example, generates a VLAN table representing the VPWS example, writes the VLAN table into the FPGA processing module, and contains a PW label, a TE label, a source MAC address and a destination MAC address which need to be packaged when the VLAN table goes out from an NNI port of the passive end equipment. The fifth processing flow of the FPGA processing module is shown in fig. 7:
step S701, receiving test flow from a switching chip processing module;
step S702, stripping the VLANID in the packet and using the VLANID to look up a VLAN table to obtain an outer layer destination MAC address, a source MAC address, a TE label and a PW label;
step S703, packaging PW label, TE label, source MAC address and destination MAC address in sequence outside the test load, and sending the test flow to the exchange chip processing module;
in step S106, the switching chip processing module performs a sixth process to directly transmit the test traffic from the NNI port of the PE device, and the FPGA processing module marks the outlet format identified by the switching chip processing module on the front of the data packet at the outlet.
In step S107, the PE device receives the test data traffic from the NNI interface, the switching chip processing module performs a seventh process, strips the destination MAC address, the source MAC address, the TE tag, and the PW tag of the outer layer of the test traffic, and sends the test traffic to the FPGA processing module. The forwarding table management module needs to write the MPLS label forwarding table to the switching chip processing module, so that the data traffic can be stripped of the TE label and the PW label. Fig. 8 shows a seventh processing flow performed by the switch chip processing module:
step S801, the PE equipment receives test data flow from the NNI;
s802, stripping a target MAC address, a source MAC address, a TE label and a PW label of an outer layer of the test flow;
and step S803, sending the test flow to the FPGA processing module.
In step S108, the FPGA processing module performs an eighth process, and after receiving the test traffic from the switch chip processing module, calculates test parameters such as throughput, delay, frame loss rate, back-to-back, and the like of each flow of each VPWS instance of RFC2544 according to the VPWS instance number, the flow ID, the sequence number, and the timestamp in the test traffic. Fig. 9 shows an eighth processing flow performed by the FPGA processing module:
step 901, receiving a test flow from a switch chip processing module;
step S902, according to the VPWS instance number, the stream ID, the sequence number and the timestamp in the test traffic, calculates the test parameters of the RFC2544, such as throughput, delay, frame loss rate, back-to-back, and the like, of each stream of each VPWS instance.
The above-mentioned embodiments are merely illustrative of the preferred embodiments of the present invention, and do not limit the scope of the present invention, and various modifications and improvements of the technical solutions of the present invention by those skilled in the art should fall within the protection scope of the present invention without departing from the design spirit of the present invention.

Claims (6)

1. A method for realizing RFC2544 in VPWS environment is characterized in that: the method specifically comprises the following steps:
for RFC2544 primary side packet transmission:
step 1, a multi-core CPU performs first processing, acquires an NNI port and PW labels of corresponding VPWS instances and MAC addresses of TE labels and next hop P equipment according to UNI interfaces corresponding to user configuration test information VPWS instances, generates a data packet needing to be tested in a VPWS environment according to a target MAC address and a source MAC address of a test data packet configured by a user, and writes the packet into an FPGA;
step 2, the FPGA carries out second processing, and a VPWS instance number, a flow ID, a serial number and a timestamp are inserted into each packet according to the configured VPWS instance, the data packet length, the packet sending rate, the burst length, the test duration, the test data flow type and the data flow test enable, and test flow is sent to the switching chip;
step 3, the exchange chip carries out third processing and directly transmits the test flow out from the NNI port of the equipment;
for RFC2544 passive end:
step 4, the equipment receives the test data flow from the NNI, the exchange chip carries out fourth processing, a target MAC address, a source MAC address, a TE label and a PW label on the outer layer of the test flow are stripped, a VLANID representing a VPWS example is marked in a load, and the test flow is sent to the FPGA;
step 5, the FPGA carries out fifth processing, after receiving the test flow from the exchange chip, the VLANID in the packet is stripped, the VLAN table is searched by the VLANID, a PW label, a TE label, a source MAC address and a destination MAC address are sequentially packaged outside the load, and the test flow is sent to the exchange chip; the multi-core CPU generates a VLAN table representing a VPWS instance to be written into the FPGA according to the environment of the VPWS, and the content is a PW label, a TE label, a source MAC address and a destination MAC address which need to be encapsulated when the VPWS goes out from an NNI port of passive end equipment;
step 6, the exchange chip carries out sixth processing and directly transmits the test flow out from the NNI port of the equipment;
for RFC2544 active end receive packet:
step 7, the equipment receives the test data flow from the NNI, the exchange chip performs seventh processing, a target MAC address, a source MAC address, a TE label and a PW label on the outer layer of the test flow are stripped, and the test flow is sent to the FPGA;
and 8, performing eighth processing by the FPGA, and after receiving the test traffic from the switching chip, calculating the test parameters of each flow of each VPWS example in the RFC2544 according to the VPWS example number, the flow ID, the serial number and the timestamp in the test traffic.
2. The method of claim 1, wherein the VPWS environment implements RFC2544, further comprising: step 1 further includes that after the VPWS environment is built, the forwarding table management module generates a VPWS-related entry, marks a VPWS attribute flag and a VPNID representing a VPWS instance in a UNI entry port attribute table generated in the multi-core CPU, and generates a VPWS forwarding table with the VPNID as a key value, where the content of the VPWS forwarding table includes an NNI port, a PW label, a TE label, and an IP address of a next hop P device; the forwarding table management module can also generate an ARP table with the IP addresses of the NNI port and the next hop P device as key values, the content of the ARP table is the MAC address of the next hop P device, according to the items which are generated in advance, when a user configures test information to bind a UNI interface corresponding to a VPWS instance, the forwarding table management module can acquire the NNI port, the PW label, the TE label and the MAC address of the next hop P device corresponding to the VPWS instance, generate a data packet which needs to be tested in the VPWS environment, and write the packet into the FPGA processing module.
3. The method of claim 2 in which the VPWS environment implements RFC2544, wherein: step 4 further includes that the forwarding table management module needs to write the MPLS label forwarding table to the switching chip processing module, so that the data traffic can be stripped of the TE label and the PW label.
4. The method of claim 3 in which the VPWS environment implements RFC2544, wherein: step 7 further includes that the forwarding table management module needs to write the MPLS label forwarding table to the switching chip processing module, so that the data traffic can strip the TE label and the PW label.
5. The method for implementing RFC2544 in VPWS environment according to any of claims 1-4, wherein: the test parameters in step 8 are throughput, delay, frame loss rate and back-to-back values.
6. An apparatus for implementing RFC2544 in VPWS environment, characterized in that: the system comprises a service protocol module, a forwarding table management module, a switching chip processing module and an FPGA processing module;
the service protocol module is used for operating a routing protocol, an LDP (local routing protocol) protocol and an ARP (address resolution protocol), realizing routing communication between the remote PE equipment and the local PE equipment, operating the LDP protocol on NNI (network interconnection interface) interfaces of the two PE equipment, mutually distributing PW (pseudo wire) labels to the opposite side, learning an MAC (media access control) address of the opposite side between each PE equipment and the directly connected P equipment, and sending processed service forwarding information to the forwarding table management module after the service protocol module processes protocol data;
the forwarding table management module is used for receiving the service forwarding information, integrating and converting the service forwarding information into a format required by the switching chip processing module and the FPGA processing module, and writing the format into the switching chip processing module and the FPGA processing module; generating a data packet to be tested in the VPWS environment according to the test information configured by the user, and writing the packet into the FPGA processing module;
the switching chip processing module is used for processing a test data packet at an NNI inlet of the PE equipment, sending the data packet to the FPGA processing module, receiving the test data packet from the FPGA processing module, and sending the test data packet from the NNI inlet of the PE equipment, wherein various service forwarding tables to be searched for when the switching chip processing module processes the data packet are written in by the forwarding table management module;
the FPGA processing module is used for actively sending test data flow to the switching chip processing module according to the configuration information, receiving a data packet sent by the switching chip processing module, further processing the data packet, then sending the data packet to the switching chip processing module, calculating various test parameters of RFC2544 after receiving the test flow from the switching chip processing module, and writing various service forwarding tables to be searched by the FPGA processing module after processing the data packet by the forwarding table management module.
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