CN109587060A - A kind of VPWS message passes through the method and apparatus of three layers of IP network - Google Patents
A kind of VPWS message passes through the method and apparatus of three layers of IP network Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/50—Routing or path finding of packets in data switching networks using label swapping, e.g. multi-protocol label switch [MPLS]
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/74—Address processing for routing
- H04L45/745—Address table lookup; Address filtering
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/70—Admission control; Resource allocation
- H04L47/82—Miscellaneous aspects
- H04L47/825—Involving tunnels, e.g. MPLS
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L61/00—Network arrangements, protocols or services for addressing or naming
- H04L61/09—Mapping addresses
- H04L61/10—Mapping addresses of different types
- H04L61/103—Mapping addresses of different types across network layers, e.g. resolution of network layer into physical layer addresses or address resolution protocol [ARP]
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L61/00—Network arrangements, protocols or services for addressing or naming
- H04L61/09—Mapping addresses
- H04L61/25—Mapping addresses of the same type
- H04L61/2503—Translation of Internet protocol [IP] addresses
- H04L61/2557—Translation policies or rules
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L61/00—Network arrangements, protocols or services for addressing or naming
- H04L61/09—Mapping addresses
- H04L61/25—Mapping addresses of the same type
- H04L61/2503—Translation of Internet protocol [IP] addresses
- H04L61/2592—Translation of Internet protocol [IP] addresses using tunnelling or encapsulation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/46—Interconnection of networks
- H04L12/4633—Interconnection of networks using encapsulation techniques, e.g. tunneling
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/46—Interconnection of networks
- H04L12/4641—Virtual LANs, VLANs, e.g. virtual private networks [VPN]
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2212/00—Encapsulation of packets
Abstract
A kind of VPWS message passes through the method and apparatus of three layers of IP network, including being made of control plane and forwarding surface, core of the master control borad multi-core CPU as control plane, the various list items needed when running Routing Protocol, LDP agreement, GRE protocol, ARP protocol various control face agreement, and generating forwarding surface treatment data packet include routing table, MPLS label table, GRE conversational list, ARP table；Forwarding surface is realized by master control borad exchange chip and interface board FPGA, master control borad exchange chip and interface board FPGA, which work in coordination, handles VPWS data packet, when uni interface packet receiving, master control borad exchange chip is responsible for received data packet, it does and data packet is sent to interface board FPGA after respective handling, FPGA after packet encapsulation processing to sending；When NNI interface packet receiving, interface board FPGA is responsible for received data packet and does decapsulation processing, and data packet is then sent to master control borad exchange chip, and master control borad exchange chip is sent after handling data packet.The surface speed forwarding of VPWS over GRE may be implemented in the present invention, ensure that the forwarding performance of device port.
Description
Technical field
The present invention relates to the computer network data communications fields, and in particular to a kind of VPWS message passes through three layers of IP network
Method and apparatus.
Background technique
VPWS (Virtual Private Wire Service), refer to construction on the infrastructure of mpls network,
Two layers of transparent transmission of high speed are provided between a pair of of port of two routers, it can be saturating by the original ether network packet of local end PE equipment
It is bright to be transmitted to far-end PE equipment, it is a kind of two layers of VPN agreement.
GRE (Generic Routing Encapsulation) i.e. Generic Routing Encapsulation, is VPN third layer tunnel
Agreement uses one kind that is, between protocol layer and is referred to as the technology in (tunnel) Tunnel, be to certain network layer protocols (such as
IP, IPX, MPLS etc.) datagram be packaged, the datagram for keeping these packed another network layer protocol (such as
IP transmission in).When Protocol Type is 0x8847 in definition GRE, subsequent encapsulated message is MPLS type message.
Under normal conditions, VPWS packet is carried on LSP (Label Switching Path) above, is on carrier network
It is exchanged by MPLS label and carries out message transmission.With the development of network technology, some Carrier Requirements VPWS packets can be passed through
Three layers of IP network is gone out from IP public network transparent transmission.For this demand, typically using VPWS encapsulation in GRE, from IP public affairs
It is transmitted in net.The data packet of this PW (Pseudo-Wire pseudo-wire) over GRE is handled, at present the exchange core of industry mainstream
Piece such as broadcom or Marvel can only wrap user and do a PW Tag Packaging or IP encapsulation, cannot wrap and do to user
IP encapsulation is done after PW Tag Packaging again, likewise, exchange chip can not be completed to shell this data packet of PW over GRE
Peel the movement of PW label after falling IP off again；Data packet processing for this PW over GRE, if with the soft forwarding of CPU
It handles, although source code flexible, transfer capability is too poor, port can not linear speed.
It is therefore desirable to provide a kind of VPWS message to pass through the method and apparatus of three layers of IP network, and it can guarantee forwarding
Surface speed forwarding is realized in performance, port.
Summary of the invention
A kind of VPWS message proposed by the present invention passes through the method and apparatus of three layers of IP network, can solve existing network protocol
Transfer capability is too poor, port can not linear speed the technical issues of.
To achieve the above object, the invention adopts the following technical scheme:
A kind of method that VPWS message passes through three layers of IP network, comprising:
It is made of control plane and forwarding surface, core of the master control borad multi-core CPU as control plane, operation Routing Protocol, LDP association
View, GRE protocol, ARP protocol various control face agreement, and generating the various list items needed when forwarding surface treatment data packet includes road
By table, MPLS label table, GRE conversational list, ARP table；Forwarding surface is by master control borad exchange chip and interface board FPGA realization, master control borad
Exchange chip and interface board FPGA, which work in coordination, handles VPWS data packet, and when uni interface packet receiving, master control borad exchange chip is responsible for connecing
Data packet is received, does and data packet is sent to interface board FPGA after respective handling, FPGA after packet encapsulation processing to sending；
When NNI interface packet receiving, interface board FPGA is responsible for received data packet and does decapsulation processing, and data packet is then sent to master control borad and is handed over
Chip is changed, master control borad exchange chip is sent after handling data packet.
Specifically includes the following steps:
When user data package enters the UNI entrance of VPWS network PE,
Step 1, master control borad exchange chip does the first processing, and upper PW label, special vlan, special is successively encapsulated outside packet
Packet is sent to interface board FPGA processing module by source MAC and specific purposes MAC；
Step 2, interface board FPGA processing module does second processing after receiving packet, peels special vlan, the particular source MAC of packet off
With specific purposes MAC, GRE upper, source MAC and purpose MAC is successively encapsulated outside PW label, and packet is sent out from the outlet NNI
This equipment；
When public network data packet reaches the NNI entrance of VPWS network PE,
Step 3, interface board FPGA processing module does third processing, and parsing packet purpose IP address is local address and IP agreement
For GRE, and it is mpls protocol in GRE, peels GRE head off, packet is sent to master control borad exchange chip；
Step 4, master control borad exchange chip does fourth process, according to PW label lookup MPLS label forwarding table in packet, obtains
The outlet UNI, peels purpose MAC, source MAC and the PW label of packet off, user's load is sent from UNI mouthfuls.
A kind of equipment that VPWS message passes through three layers of IP network, the equipment include:
Master control borad service protocol module, for running Routing Protocol, LDP agreement, GRE protocol, ARP protocol；Master control borad industry
Business protocol module runs Routing Protocol, realizes that the routing between far-end PE equipment and local PE equipment is got through；Master control borad business association
View module runs GRE protocol in two PE equipment, forms gre tunneling on two PE equipment；Master control borad service protocol mould
Block runs LDP agreement on the gre tunnel interface of two PE equipment, and mutual phase partitioning PW label is to other side；Master control borad service protocol
Module also needs to run ARP protocol in each PE equipment, makes to learn to other side MAC between PE equipment and direct-connected P equipment
Location；After master control borad service protocol module is to the processing of these protocol datas, by treated, business forwarding information sends out message to master control
Plate forwarding table management module；
Master control borad forwarding table management module integrates these business forwarding informations for receiving the business forwarding information
The format that master control borad exchange chip processing module and interface board FPGA processing module need is converted to, master control borad exchange core is written to
Piece processing module and interface board FPGA processing module；
Master control borad exchange chip processing module sends out data packet after the data packet processing of the UNI entrance to PE equipment
Interface board FPGA processing module is given, and after receiving data packet processing from interface board FPGA processing module, from the UNI of PE equipment
Mouth is sent.The various businesses forwarding table that master control borad exchange chip processing module processing data packet requires to look up is turned by master control borad
Deliver management module write-in；
Interface board FPGA processing module is sealed for receiving the data packet that master control borad exchange chip processing module sends over
It after dress processing, is sent from NNI mouthfuls of equipment, and receives data packet decapsulation processing from NNI mouthfuls, be then then forwarded to master control
Plate exchange chip processing module；The various businesses forwarding table that interface board FPGA processing module processing data packet requires to look up is by master control
The write-in of plate forwarding table management module.
As previously mentioned, when user data package enters the UNI entrance of VPWS network PE,
In step 1, master control borad exchange chip processing module does the first processing, and upper PW label, spy are successively encapsulated outside packet
Packet, is sent to interface board FPGA processing module by different VLAN, particular source MAC and specific purposes MAC.Master control borad forwarding table manages mould
Block needs to stamp VPWS attribute mark to master control borad exchange chip UNI entrance, and the corresponding VPN forwarding table of this VPWS example and
Master control borad exchange chip processing module is written in virtual ARP table.Master control borad exchange chip processing module finds UNI entrance as VPWS category
Property, it will continue to look into VPN forwarding table, upper PW label encapsulated before user data package；Continue to look into ARP table, outside the PW label of packet
Face encapsulates upper special vlan, particular source MAC and specific purposes MAC, and packet is sent to interface board FPGA processing module.It is described special
VLAN, value are equal to GRE session number, do second processing to data packet for interface board FPGA processing module in step 2.Because this
More VPWS examples, more GRE sessions are supported in invention, therefore interface board FPGA processing module needs to know this VPWS example in step 2
Data packet be carried in which GRE session, the present invention carries GRE session number with VLAN in data packet.Particular source MAC is
0x5a5a5aa5a5a5, specific purposes MAC are 0xa5a5a55a5a5a, for interface board FPGA processing module in informing step 2
The packet that this special MAC is received from master control borad exchange chip processing module needs to do the processing of encapsulation GRE.
In step 2, interface board FPGA processing module does second processing after receiving packet, peels special vlan, the particular source of packet off
MAC and specific purposes MAC successively encapsulates GRE upper, source MAC and purpose MAC outside PW label, and packet is sent from NNI interface
It goes out.If interface board FPGA processing module is from the source MAC that master control borad exchange chip processing module receives data packet
0x5a5a5aa5a5a5, purpose MAC are 0xa5a5a55a5a5a, can peel purpose MAC, the source MAC and VLAN of data packet off, be used in combination
VLANID (i.e. GRE session number) searches GRE conversational list.GRE conversational list is written by master control borad forwarding table management module, and master control borad turns
It delivers management module to need to integrate routing table and ARP table, destination IP, the source IP of gre tunneling is obtained from routing table, is obtained from ARP table
Take next-hop device mac address MAC as a purpose, finally with this equipment MAC as source MAC together be integrated into GRE conversational list.It connects
Successively encapsulation is GRE upper outside the PW label of data packet for oralia FPGA processing module, source MAC and purpose MAC, wrapping from NNI
Outlet sends out this equipment.
When public network data packet reaches the NNI entrance of VPWS network PE,
In step 3, interface board FPGA processing module does third processing, and parsing packet purpose IP address is local address and IP is assisted
View is GRE, and is mpls protocol in GRE, peels GRE head off, packet is sent to master control borad exchange chip；If it is other types
Data packet, be transmitted directly to master control borad exchange chip and do other processing.
In step 4, master control borad exchange chip does fourth process, according to PW label lookup MPLS label forwarding table in packet, obtains
It takes UNI to export, peels purpose MAC, source MAC and the PW label of packet off, user's load is sent from UNI mouthfuls.Master control borad forwarding
Table management module needs to write MPLS label forwarding table to master control borad exchange chip processing module, specifies exchange chip outlet.
As shown from the above technical solution, using master control borad multi-core CPU as the core of control plane, generate forwarding surface needs the present invention
The various list items wanted.Forwarding surface realized by master control borad exchange chip and interface board FPGA, master control borad exchange chip and interface board
The list item of FPGA forwarding foundation is all written by master control borad multi-core CPU.When user data package enters the UNI entrance of VPWS network PE
When, master control borad exchange chip does the first processing, and upper PW label, special vlan, particular source MAC and special are successively encapsulated outside packet
Packet is sent to interface board FPGA processing module by purpose MAC；Interface board FPGA processing module does second processing after receiving packet, shells
Special vlan, particular source MAC and the specific purposes MAC of switch successively encapsulate GRE upper, source MAC and purpose outside PW label
Packet is sent out this equipment from the outlet NNI by MAC.When public network data packet reaches the NNI entrance of VPWS network PE, interface board
FPGA processing module does third processing, and parsing packet purpose IP address is local address and IP agreement is GRE, and is in GRE
Mpls protocol peels GRE head off, and packet is sent to master control borad exchange chip；Master control borad exchange chip does fourth process, according in packet
PW label lookup MPLS label forwarding table obtains the outlet UNI, purpose MAC, source MAC and the PW label of packet is peeled off, user's load
It is sent from UNI mouthfuls.It is related to GRE that the present invention by master control borad multi-core CPU writes VPWS to forwarding surface as control plane core
Various forwarding-table items, master control borad exchange chip and interface board FPGA work in coordination as forwarding surface to be handled VPWS message and passes through IP network
The surface speed forwarding of VPWSoverGRE may be implemented in network, ensure that the forwarding performance of device port.
Detailed description of the invention
Fig. 1 is the method and step flow chart that VPWS message of the invention passes through three layers of IP network；
Fig. 2 is hardware connection structure figure of the invention；
Fig. 3 is the structural block diagram of equipment of the invention；
Fig. 4 is master control borad exchange chip the first process flow diagram of processing module of the invention；
Fig. 5 is interface board FPGA processing module second processing flow chart of the invention；
Fig. 6 is interface board FPGA processing module third process flow diagram of the invention；
Fig. 7 is master control borad exchange chip processing module fourth process flow chart of the invention.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.
As shown in Figure 1, the method that VPWS message passes through three layers of IP network described in the present embodiment, comprising:
When user data package enters the UNI entrance of VPWS network PE:
Step S100, master control borad exchange chip does the first processing, successively encapsulated outside packet upper PW label, special vlan,
Packet is sent to interface board FPGA processing module by particular source MAC and specific purposes MAC；
Step S200, interface board FPGA processing module does second processing after receiving packet, peels special vlan, the particular source of packet off
MAC and specific purposes MAC successively encapsulates GRE upper, source MAC and purpose MAC outside PW label, and packet is exported from NNI and is sent
This equipment out；
When public network data packet reaches the NNI entrance of VPWS network PE:
Step S300, interface board FPGA processing module does third processing, and parsing packet purpose IP address is local address and IP
Agreement is GRE, and is mpls protocol in GRE, peels GRE head off, packet is sent to master control borad exchange chip；
Step S400, master control borad exchange chip does fourth process, according to PW label lookup MPLS label forwarding table in packet, obtains
It takes UNI to export, peels purpose MAC, source MAC and the PW label of packet off, user's load is sent from UNI mouthfuls；
As shown in Fig. 2, core of the master control borad multi-core CPU as control plane, carries the fortune of entire control plane software systems
Row, and the various list items of forwarding surface needs are generated, forwarding surface is realized by master control borad exchange chip and interface board FPGA, and master control borad is handed over
The list item for changing chip and interface board FPGA forwarding foundation is all written by master control borad multi-core CPU.
Other side according to an embodiment of the present invention provides a kind of equipment that VPWS message passes through three layers of IP network,
As shown in Figure 3, wherein thin arrow indicates that forwarding table information, block arrow indicate converting flow in figure, and the equipment includes:
Master control borad service protocol module, for running Routing Protocol, LDP agreement, GRE protocol, ARP protocol etc., Yao Shixian
Routing between far-end PE equipment and local PE equipment is got through, and LDP agreement is run on the gre tunnel interface of two PE equipment,
Mutual phase partitioning PW label is to other side.Each PE equipment also needs to learn between the P equipment of direct-connected next-hop to other side MAC.It is main
After plate service protocol module is controlled to the processing of these protocol datas, by treated, business forwarding information hair message gives master control borad to forward
Table management module；
Master control borad forwarding table management module integrates these business forwarding informations for receiving the business forwarding information
The format that master control borad exchange chip processing module and interface board FPGA processing module need is converted to, master control borad exchange core is written to
Piece processing module and interface board FPGA processing module；
Master control borad exchange chip processing module sends out data packet after the data packet processing of the UNI entrance to PE equipment
Interface board FPGA processing module is given, and after receiving data packet processing from interface board FPGA processing module, from the UNI of PE equipment
Mouth is sent.The various businesses forwarding table that master control borad exchange chip processing module processing data packet requires to look up is turned by master control borad
Deliver management module write-in；
Interface board FPGA processing module is sealed for receiving the data packet that master control borad exchange chip processing module sends over
It after dress processing, is sent from NNI mouthfuls of equipment, and receives data packet decapsulation processing from NNI mouthfuls, be then then forwarded to master control
Plate exchange chip processing module；The various businesses forwarding table that interface board FPGA processing module processing data packet requires to look up is by master control
The write-in of plate forwarding table management module.
It, below will be detailed to further appreciate that step process that data packet provided in an embodiment of the present invention forwards in a device
Explanation.
In the step s 100, master control borad exchange chip processing module does the first processing, and upper PW mark is successively encapsulated outside packet
Packet is sent to interface board FPGA processing module by label, special vlan, particular source MAC and specific purposes MAC.Master control borad forwarding table
Management module needs to stamp VPWS attribute mark to master control borad exchange chip UNI entrance, and the corresponding VPN of this VPWS example is turned
It delivers and master control borad exchange chip processing module is written with virtual ARP table.Master control borad exchange chip processing module finds UNI entrance
VPWS attribute will continue to look into VPN forwarding table, and upper PW label is encapsulated before user data package；Continue to look into ARP table, in the PW of packet
Upper special vlan, particular source MAC and specific purposes MAC are encapsulated outside label, and packet is sent to interface board FPGA processing module.Institute
Special vlan is stated, value is equal to GRE session number, does at second for interface board FPGA processing module in step S200 to data packet
Reason.Because the present invention supports more VPWS examples, more GRE sessions, interface board FPGA processing module needs are known in step S200
Which GRE session is the data packet of road this VPWS example be carried in, and the present invention carries GRE session number with VLAN in data packet.
Particular source MAC is 0x5a5a5aa5a5a5, and specific purposes MAC is 0xa5a5a55a5a5a, for interface in informing step S200
Plate FPGA processing module receives the packet of this special MAC from master control borad exchange chip processing module, needs to do the place of encapsulation GRE
Reason.It is as shown in Figure 4 that master control borad exchange chip processing module does the first process flow:
Step S101, data packet enters the uni interface of PE equipment；
Step S102, port attribute table is searched, judges whether port configures VPWS attribute；
Step S103, if it is not, process terminates.If so, searching VPN forwarding table, PW label and purpose outlet are obtained；
Step S104, PW label is encapsulated before data packet；
Step S105, virtual ARP table is searched, special vlan, particular source MAC and specific purposes MAC are obtained；
Step S106, special vlan, particular source MAC and specific purposes MAC are successively encapsulated outside the PW label of data packet,
Packet is sent to interface board FPGA processing module.
In step s 200, interface board FPGA processing module does second processing after receiving packet, peels special vlan, the spy of packet off
Different source MAC and specific purposes MAC, successively encapsulation is GRE upper outside PW label, source MAC and purpose MAC, wrapping from NNI interface
It sends.If interface board FPGA processing module is from the source MAC that master control borad exchange chip processing module receives data packet
0x5a5a5aa5a5a5, purpose MAC are 0xa5a5a55a5a5a, can peel purpose MAC, the source MAC and VLAN of data packet off, be used in combination
VLANID (i.e. GRE session number) searches GRE conversational list.GRE conversational list is written by master control borad forwarding table management module, and master control borad turns
It delivers management module to need to integrate routing table and ARP table, destination IP, the source IP of gre tunneling is obtained from routing table, is obtained from ARP table
Take next-hop device mac address MAC as a purpose, finally with this equipment MAC as source MAC together be integrated into GRE conversational list.It connects
Successively encapsulation is GRE upper outside the PW label of data packet for oralia FPGA processing module, source MAC and purpose MAC, wrapping from NNI
Outlet sends out this equipment.It is as shown in Figure 5 that interface board FPGA processing module does second processing process:
Step S201, data packet is received from exchange chip processing module；
Step S202, judge whether the purpose MAC of data packet is equal to 0xa5a5a55a5a5a；
Step S203, if it is not, process terminates.If so, judging whether the source MAC of data packet is equal to
0x5a5a5aa5a5a5；
Step S204, if it is not, process terminates.If so, peeling the VLAN of data packet, source MAC and purpose MAC off；
Step S205, GRE conversational list is searched with VLANID, obtains destination IP, source IP, source MAC, purpose MAC；
Step S206, GRE, source MAC and purpose MAC are successively encapsulated outside the PW label of data packet, and packet is gone out from NNI
Mouth sends out this equipment.
In step S300, interface board FPGA processing module does third processing, and parsing packet purpose IP address is local address
And IP agreement is GRE, and is mpls protocol in GRE, peels GRE head off, packet is sent to master control borad exchange chip；If it is it
The data packet of its type is transmitted directly to master control borad exchange chip and does other processing.Exchange chip processing module does third processing
Process is as shown in Figure 6:
Step S301, data packet enters the NNI interface of PE equipment；
Step S302, judge data packet whether be IP packet and destination IP whether local ip address；
Step S303, if it is not, process terminates.If so, judging that IP protocol number is GRE and GRE protocol is MPLS；
Step S304, if it is not, process terminates.If so, peeling the GRE head of data packet off, packet is sent to master control borad
Exchange chip processing module.
In step S400, master control borad exchange chip does fourth process, is forwarded according to PW label lookup MPLS label in packet
Table obtains the outlet UNI, peels purpose MAC, source MAC and the PW label of packet off, user's load is sent from UNI mouthfuls.Master control borad
Forwarding table management module needs to write MPLS label forwarding table to master control borad exchange chip processing module, specifies exchange chip outlet.
It is as shown in Figure 7 that master control borad exchange chip processing module does fourth process process:
Step S401, data packet is received from interface board FPGA processing module；
Step S402, according to PW label lookup MPLS label forwarding table in packet, the outlet UNI is obtained；
Step S403, purpose MAC, source MAC and the PW label for peeling packet off, send user's load from UNI mouthfuls.
From the foregoing, it will be observed that the embodiment of the present invention by master control borad multi-core CPU as control plane core to forwarding surface write VPWS and
The related various forwarding-table items of GRE, master control borad exchange chip and interface board FPGA work in coordination as forwarding surface and handle VPWS message
IP network is passed through, the surface speed forwarding of VPWSoverGRE may be implemented, ensure that the forwarding performance of device port.
The above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although with reference to the foregoing embodiments
Invention is explained in detail, those skilled in the art should understand that: it still can be to aforementioned each implementation
Technical solution documented by example is modified or equivalent replacement of some of the technical features；And these modification or
Replacement, the spirit and scope for technical solution of various embodiments of the present invention that it does not separate the essence of the corresponding technical solution.
Claims (6)
1. a kind of method that VPWS message passes through three layers of IP network, characterized by the following steps:
When user data package enters the UNI entrance of VPWS network PE,
S100, master control borad exchange chip do the first processing, and upper PW label, special vlan, particular source MAC are successively encapsulated outside packet
With specific purposes MAC, packet is sent to interface board FPGA processing module；
S200, interface board FPGA processing module do second processing after receiving packet, peel the special vlan, particular source MAC and spy of packet off
Different purpose MAC, successively encapsulates GRE upper, source MAC and purpose MAC outside PW label, and packet is sent out from the outlet NNI and is originally set
It is standby；
S300, when public network data packet reach VPWS network PE NNI entrance when,
Interface board FPGA processing module does third processing, and parsing packet purpose IP address is local address and IP agreement is GRE, and
It is mpls protocol in GRE, peels GRE head off, packet is sent to master control borad exchange chip；
S400, master control borad exchange chip do fourth process, according to PW label lookup MPLS label forwarding table in packet, obtain UNI and go out
Mouthful, it peels purpose MAC, source MAC and the PW label of packet off, user's load is sent from UNI mouthfuls.
2. the method that a kind of VPWS message according to claim 1 passes through three layers of IP network, which is characterized in that the step
S100 further include:
Step S101, data packet enters the uni interface of PE equipment；
Step S102, port attribute table is searched, judges whether port configures VPWS attribute；
Step S103, if it is not, process terminates；If so, searching VPN forwarding table, PW label and purpose outlet are obtained；
Step S104, PW label is encapsulated before data packet；
Step S105, virtual ARP table is searched, special vlan, particular source MAC and specific purposes MAC are obtained；
Step S106, special vlan, particular source MAC and specific purposes MAC are successively encapsulated outside the PW label of data packet, packet
It is sent to interface board FPGA processing module.
3. the method that a kind of VPWS message according to claim 2 passes through three layers of IP network, which is characterized in that the step
S200 further include:
Step S201, data packet is received from exchange chip processing module；
Step S202, judge whether the purpose MAC of data packet is equal to 0xa5a5a55a5a5a；
Step S203, if it is not, process terminates；If so, judging whether the source MAC of data packet is equal to
0x5a5a5aa5a5a5；
Step S204, if it is not, process terminates；If so, peeling the VLAN of data packet, source MAC and purpose MAC off；
Step S205, GRE conversational list is searched with VLANID, obtains destination IP, source IP, source MAC, purpose MAC；
Step S206, GRE, source MAC and purpose MAC are successively encapsulated outside the PW label of data packet, and packet is exported from NNI and is sent out
Send out this equipment.
4. the method that a kind of VPWS message according to claim 3 passes through three layers of IP network, it is characterised in that: the step
S300 further include:
Step S301, data packet enters the NNI interface of PE equipment；
Step S302, judge data packet whether be IP packet and destination IP whether local ip address；
Step S303, if it is not, process terminates；If so, judging that IP protocol number is GRE and GRE protocol is MPLS；
Step S304, if it is not, process terminates；If so, peeling the GRE head of data packet off, packet is sent to master control borad exchange
Chip processing module.
5. the method that a kind of VPWS message according to claim 4 passes through three layers of IP network, it is characterised in that: the step
S400 further include:
Step S401, data packet is received from interface board FPGA processing module；
Step S402, according to PW label lookup MPLS label forwarding table in packet, the outlet UNI is obtained；
Step S403, purpose MAC, source MAC and the PW label for peeling packet off, send user's load from UNI mouthfuls.
6. a kind of equipment that VPWS message passes through three layers of IP network, it is characterised in that: including master control borad service protocol module, master control
Plate forwarding table management module, master control borad exchange chip processing module and interface board FPGA processing module；
Master control borad service protocol module, for running Routing Protocol, LDP agreement, GRE protocol, ARP protocol；
Master control borad service protocol module runs Routing Protocol, realizes that the routing between far-end PE equipment and local PE equipment is got through；
Master control borad service protocol module runs GRE protocol in two PE equipment, forms gre tunneling on two PE equipment；
Master control borad service protocol module runs LDP agreement on the gre tunnel interface of two PE equipment, and mutual phase partitioning PW label is given
Other side；
Master control borad service protocol module also needs to run ARP protocol in each PE equipment, make PE equipment and direct-connected P equipment it
Between study to side mac address；
After master control borad service protocol module is to the processing of these protocol datas, by treated, business forwarding information sends out message to master control
Plate forwarding table management module；
These business forwarding informations are integrated and are converted for receiving the business forwarding information by master control borad forwarding table management module
For the format that master control borad exchange chip processing module and interface board FPGA processing module need, it is written at master control borad exchange chip
Manage module and interface board FPGA processing module；
Master control borad exchange chip processing module is sent to data packet after the data packet processing of the UNI entrance to PE equipment
Interface board FPGA processing module, and from interface board FPGA processing module receive data packet processing after, from UNI mouth of PE equipment hair
It sees off；
The various businesses forwarding table that master control borad exchange chip processing module processing data packet requires to look up is by master control borad forwarding table pipe
Manage module write-in；
Interface board FPGA processing module is done at encapsulation for receiving the data packet that master control borad exchange chip processing module sends over
It after reason, is sent from NNI mouthfuls of equipment, and receives data packet decapsulation processing from NNI mouthfuls, be then then forwarded to master control borad friendship
Change chip processing module；
The various businesses forwarding table that interface board FPGA processing module processing data packet requires to look up manages mould by master control borad forwarding table
Block write-in.
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