CN115659885A - Systems and methods for simulation testing - Google Patents

Abstract

The embodiment of the present application relates to the field of integrated circuits, and provides a system and method for simulation testing. The system includes a stimulus generator and a scheduler implemented on the software side and a general bus model implemented on the hardware side, wherein the stimulus generator is used for Generate stimulus files; the scheduler is used to load the stimulus files into the generic bus model; the generic bus model is used to generate stimulus signals based on the stimulus files and send the stimulus signals to the design under test for simulation testing; the generic bus model is also used to receive responses signal, and determine the result of the simulation test based on the response signal. Through this solution, all simulation behaviors can be completed in the hardware environment, the decoupling of software and hardware can be realized, and the efficiency of simulation testing can be improved.

Description

Systems and methods for simulation testing

technical field

The present application relates to the technical field of integrated circuits, and more specifically, to a system and method for simulation testing.

Background technique

With the development of large-scale integrated circuit (integrated circuit, IC) technology, the logic scale of the chip and the complexity of the circuit are getting higher and higher. In order to ensure the quality of the chip and the time to market, it is necessary to conduct accurate and fast simulation tests on the chip. Hardware emulation acceleration (emulation) technology can improve the logic scale and running speed of the DUT by mapping the design under test (DUT) to the hardware platform of the emulator. However, since the generation of the DUT input signal and the processing of the output signal need to be carried out in the software environment, the speed of the chip simulation test is limited by the running speed of the software side. Therefore, how to improve the efficiency of chip simulation testing has become an urgent technical problem to be solved.

Contents of the invention

Embodiments of the present application provide a system and method for simulation testing, which can enable all simulation behaviors to be completed in a hardware environment, realize decoupling of software and hardware, and improve the efficiency of simulation testing.

In the first aspect, a simulation test system is provided, including a stimulus generator and a scheduler implemented on the software side and a general bus model implemented on the hardware side, wherein the stimulus generator is used to generate stimulus files, and the stimulus files are used for Indicates the operation of the simulation test of the design under test; the scheduler is used to load the stimulus file to the general bus model; the general bus model is used to generate the stimulus signal according to the stimulus file and send the stimulus signal to the design under test for simulation testing ; The general bus model is also used to receive the response signal and determine the result of the simulation test according to the response signal, wherein the response signal is an output signal sent by the design under test according to the excitation signal.

According to the technical solution provided by this application, the simulation test system can realize the generation of the excitation signal and the receiving process of the response signal in the hardware environment, so that all simulation behaviors are completed in the hardware environment, avoiding frequent interaction between hardware and software, and improving simulation testing. At the same time, it realizes the decoupling of software and hardware, increases the logic scale of simulation test, and improves the efficiency of simulation test.

With reference to the first aspect, in some implementations of the first aspect, the stimulus file includes a write stimulus vector for instructing a write operation on the design under test, the stimulus signal includes a write address channel signal and a write data channel signal, and the response signal includes a write Response channel signal, general bus model, including: write stimulus storage module, used to store write stimulus vector; write channel decoding module, used to decode write stimulus vector, to generate write address channel signal and write data channel signal, wherein, write address The channel signal is used to indicate the address of writing data to the design under test, and the write data channel signal is used to indicate the data written to the design under test; the write address control module is used to send the write address channel signal to the design under test; the write data The control module is used to send the write data channel signal to the design under test; the write response recording module is used to receive the write response channel signal, and the write response channel signal is used to indicate whether the write operation is successful.

According to the technical solution provided by this application, the universal bus model can analyze the write stimulus vector in the hardware environment, and use the hardware interface provided by the standard protocol to perform signal interaction with the DUT, thereby realizing the simulation test of the write operation by the hardware and verifying the DUT write operation. correctness.

With reference to the first aspect, in some implementation manners of the first aspect, the write incentive storage module is further configured to: when a trigger condition of the write incentive vector is met, send the write incentive vector to the write channel decoding module.

According to the technical solution provided by the present application, the universal bus model can schedule the timing and order of triggering the write stimulus vector, thereby increasing the diversity and authenticity of the simulatable scenarios and improving the effect of the simulation test.

In combination with the first aspect, in some implementations of the first aspect, the stimulus file includes a read stimulus vector, which is used to indicate the read operation of the design under test, the stimulus signal includes a read address channel signal, and the response signal includes a read response channel signal. The bus model includes: a read stimulus storage module for storing the read stimulus vector; a read channel decoding module for decoding the read stimulus vector to generate a read address channel signal, wherein the read address channel signal is used to indicate the read from the design under test The address for fetching data; the read address control module is used to send the read address channel signal to the design under test; the read response record module is used to receive the read response channel signal, and the read response channel signal is used to indicate whether the read operation is successful.

According to the technical solution provided by this application, the universal bus model can analyze the read stimulus vector in the hardware environment, and use the hardware interface provided by the standard protocol to perform signal interaction with the DUT, thereby realizing the simulation test of the read operation by the hardware and verifying the read operation of the DUT. correctness.

With reference to the first aspect, in some implementation manners of the first aspect, the read stimulus storage module is further configured to: send the read stimulus vector to the read channel decoding module when a trigger condition of the read stimulus vector is satisfied.

According to the technical solution provided by the present application, the universal bus model can schedule the timing and order of triggering the read stimulus vector, thereby increasing the diversity and authenticity of the simulatable scenarios and improving the effect of the simulation test.

In combination with the first aspect, in some implementations of the first aspect, the general bus model further includes a process monitoring module, configured to: determine test result information according to the response signal, and the test result information is used to indicate the result of the simulation test; The device sends the test result information.

According to the technical solution provided by this application, the universal bus model can determine the test result of the stimulus file according to the response result of each read/write stimulus vector in the stimulus file, so as to analyze and transform the signal sent by the system under test into a more intuitive test result Information, easy for testers to understand.

With reference to the first aspect, in some implementation manners of the first aspect, the scheduler is further configured to receive the test result information, and upload the test result information to the server.

According to the technical solution provided by this application, the scheduler can obtain the simulation test results sent by the general bus model, and upload them to the server or user equipment, so that the user can obtain the test results at any time after the simulation test ends.

With reference to the first aspect, in some implementation manners of the first aspect, the scheduler is further configured to monitor the running state of the design under test, so that the user can debug the design under test according to the running state.

According to the technical solution provided by this application, the scheduler can monitor the key signals in the hardware logic operation, so that the user's testers can quickly locate the cause of the problem and debug it when there is a problem in the test, and improve the efficiency of the simulation test.

With reference to the first aspect, in some implementation manners of the first aspect, the scheduler is further configured to send a control signal to the general bus model, and the control signal is used to control the general bus model to start or stop.

According to the technical solution provided by this application, the scheduler can control the state of the general bus model, so that the test process is automatically completed, which improves the user experience, and at the same time can schedule the work of multiple chip systems to be tested, thereby increasing the diversity of simulatable scenarios And authenticity, improve the effect of simulation test.

With reference to the first aspect, in some implementation manners of the first aspect, the scheduler is further configured to send an initialization signal to the design under test, and the initialization signal is used to restore the design under test to a state before the simulation test.

According to the technical solution provided by this application, the scheduler can restore the system under test after one round of testing is over or before the next round of testing starts, so that the entire system can update the stimulus file after a round of simulation testing and automatically start the next round Test, thereby improving the efficiency of simulation testing.

With reference to the first aspect, in some implementations of the first aspect, the stimulus generator includes: a field generation module, configured to generate an instruction field that satisfies the constraint file according to the constraint file, wherein the constraint file is used to indicate the Value range; the field splicing storage module is used for splicing instruction fields to generate instruction information, and the instruction information is used to indicate the operation performed by the general bus model on the design to be tested.

According to the technical solution provided by this application, the stimulus generator can generate stimulus files in batches that meet the test requirements, thereby increasing the data volume of the simulation test and improving the accuracy of the simulation test.

With reference to the first aspect, in some implementation manners of the first aspect, the field splicing module is further configured to determine debugging information according to the instruction information, and the debugging information is used to explain content of the instruction information.

According to the technical solution provided by this application, the stimulus generator can also generate debugging information for explaining the content of instruction information, so that the user's tester can quickly understand the operation of the stimulus file instructing the design to be tested, and facilitate debugging of the design to be tested.

With reference to the first aspect, in some implementation manners of the first aspect, the stimulus generator further includes a preprocessing module, configured to preprocess the instruction field so that it meets the standard protocol used by the general bus model.

According to the technical solution provided by this application, the excitation generator can preprocess the randomly generated instruction fields to avoid the situation that the instruction field does not conform to the bus standard protocol used in the design to be tested, thereby improving the accuracy of the excitation file and improving the simulation test Effect.

With reference to the first aspect, in some implementation manners of the first aspect, the stimulus generator further includes a constraint format self-inspection module, configured to determine whether the format of the constraint file is correct.

According to the technical solution provided by this application, the stimulus generator can first check the correctness of the constraint file to avoid the situation that the test requirements input by the user do not conform to the bus standard protocol used in the design to be tested, thereby improving the accuracy of the stimulus file and improving The effect of the simulation test.

With reference to the first aspect, in some implementation manners of the first aspect, the incentive file generated by the incentive generator includes at least one of the following: random address incentives, continuous address incentives, and weighted address incentives.

According to the technical solution provided by this application, the stimulus generator can generate various types of stimulus files, so that the simulation test system can cover more test scenarios, thereby improving the accuracy of the simulation test.

With reference to the first aspect, in some implementation manners of the first aspect, the general bus model is written by synthesizable code.

According to the technical solution provided by this application, the general bus model is written by synthesizable Verilog code (or other languages that can be realized by real circuits), so that the test platform composed of the general bus model and the design to be tested can be applied to embedded hardware simulation testing method to further improve the efficiency of simulation testing.

In a second aspect, a system for simulation testing is provided, the method is executed by the system for simulation testing, the system includes an excitation generator and a scheduler implemented on the software side and a general bus model implemented on the hardware side, the method includes: The generator generates a stimulus file, and the stimulus file is used to indicate the operation of the simulation test of the design under test; the scheduler loads the stimulus file into the general bus model; the general bus model generates a stimulus signal according to the stimulus file, and sends the stimulus signal to the design under test to carry out the simulation test; the general bus model receives the response signal, and determines the result of the simulation test according to the response signal, wherein the response signal is an output signal sent by the design under test according to the excitation signal.

With reference to the second aspect, in some implementations of the second aspect, the stimulus file includes a write stimulus vector for instructing a write operation on the design under test, the stimulus signal includes a write address channel signal and a write data channel signal, and the response signal includes a write In response to the channel signal, the universal bus model generates an excitation signal according to the excitation file, and sends the excitation signal to the design under test for simulation testing, including: storing the write excitation vector through the write excitation storage module; through the write channel decoding module, decoding Write the stimulus vector to generate the write address channel signal and the write data channel signal, wherein the write address channel signal is used to indicate the address for writing data to the design under test, and the write data channel signal is used to indicate the data written to the design under test Send the write address channel signal to the design under test through the write address control module; send the write data channel signal to the design under test through the write data control module; the general bus model receives the response signal, and determines the result of the simulation test according to the response signal, Including: receiving a write response channel signal through a write response recording module, and the write response channel signal is used to indicate whether the write operation is successful.

In conjunction with the second aspect, in some implementations of the second aspect, the general bus model generates the stimulus signal according to the stimulus file, and sends the stimulus signal to the design under test for simulation testing, and also includes: by writing the stimulus storage module, when When the trigger condition of the write stimulus vector is met, the write stimulus vector is sent to the write channel decoding module.

In conjunction with the second aspect, in some implementations of the second aspect, the stimulus file includes a read stimulus vector, which is used to indicate the read operation of the design under test, the stimulus signal includes a read address channel signal, and the response signal includes a read response channel signal. The bus model generates the stimulus signal according to the stimulus file, and sends the stimulus signal to the design under test for simulation testing, including: storing the read stimulus vector through the read stimulus storage module; decoding the read stimulus vector through the read channel decoding module, and Generate a read address channel signal, wherein the read address channel signal is used to indicate the address of reading data from the design to be tested; send the read address channel signal to the design to be tested through the read address control module; the general bus model receives the response signal, and according to The response signal determines the result of the simulation test, including: receiving a read response channel signal through the read response recording module, and the read response channel signal is used to indicate whether the read operation is successful.

In conjunction with the second aspect, in some implementations of the second aspect, the general bus model generates an excitation signal according to the excitation file, and sends the excitation signal to the design under test for simulation testing, and further includes: by reading the excitation storage module, when When the trigger condition of the read stimulus vector is met, the read stimulus vector is sent to the read channel decoding module.

In combination with the second aspect, in some implementations of the second aspect, the general bus model receives the response signal, and determines the result of the simulation test according to the response signal, and further includes: determining the test result information according to the response signal through the process monitoring module, The test result information is used to indicate the result of the simulation test; the test result information is sent to the scheduler.

With reference to the second aspect, in some implementation manners of the second aspect, the method further includes: the scheduler receives the test result information, and uploads the test result information to the server.

With reference to the second aspect, in some implementation manners of the second aspect, the method further includes: the scheduler monitors the running state of the design under test, so that the user debugs the design under test according to the running state.

With reference to the second aspect, in some implementation manners of the second aspect, the method further includes: the scheduler sends a control signal to the general bus model, and the control signal is used to control the general bus model to start or stop.

With reference to the second aspect, in some implementation manners of the second aspect, the method further includes: the scheduler sends an initialization signal to the design under test, and the initialization signal is used to restore the design under test to a state before the simulation test.

In conjunction with the second aspect, in some implementations of the second aspect, the stimulus generator generates the stimulus file, including: using a field generation module to generate an instruction field that satisfies the constraint file according to the constraint file, wherein the constraint file is used to indicate that the instruction The value range of the field; by splicing the storage module, according to the splicing instruction field, the instruction information is generated, and the instruction information is used to indicate the operation of the general bus model to be tested.

With reference to the second aspect, in some implementations of the second aspect, the stimulus generator generating the stimulus file further includes: determining debugging information according to instruction information by concatenating storage modules, and the debugging information is used to explain the contents of the instruction information.

With reference to the second aspect, in some implementations of the second aspect, the stimulus generator generating the stimulus file further includes: using a preprocessing module to preprocess the instruction field so that it meets the standard protocol used by the general bus model.

With reference to the second aspect, in some implementation manners of the second aspect, the stimulus generator generating the stimulus file further includes: determining whether the format of the constraint file is correct through a constraint format self-check module.

With reference to the second aspect, in some implementation manners of the second aspect, the incentive file generated by the incentive generator includes at least one of the following: random address incentives, continuous address incentives, and weighted address incentives.

With reference to the second aspect, in some implementation manners of the second aspect, the general bus model is written by synthesizable code.

In a third aspect, a system for simulation testing is provided, including: a processor and a memory, the memory is used to store a computer program, and the processor is used to call and run the computer program from the memory, so that the system performs as described in the second aspect or the second A method in any possible implementation of an aspect.

In a fourth aspect, there is provided a computer program product, including: computer program code, when the computer program code is executed by a processor of a computing device, the computing device executes the second aspect or any possible implementation of the second aspect methods in methods.

In a fifth aspect, there is provided a computer-readable storage medium, including a computer program. When the computer program runs on a computer, the computer executes the method in the second aspect or any possible implementation manner of the second aspect.

Description of drawings

FIG. 1 is a schematic diagram of a system architecture of an embodiment of the present application.

Fig. 2 is a schematic diagram of an example of an application scenario of the embodiment of the present application.

Fig. 3 is a schematic structural block diagram of a simulation test system provided by an embodiment of the present application.

Fig. 4 is a schematic structural block diagram of an excitation generator provided by an embodiment of the present application.

Fig. 5 is a schematic structural block diagram of a general bus model provided by an embodiment of the present application.

Fig. 6 is a schematic flowchart of a simulation test method provided by an embodiment of the present application.

Fig. 7 is a schematic structural block diagram of a simulation test system provided by an embodiment of the present application.

Detailed ways

The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings.

The present application presents various aspects, embodiments or features in terms of a system comprising a number of devices, components, modules and the like. It is to be understood and appreciated that the various systems may include additional devices, components, modules, etc. and/or may not include all of the devices, components, modules etc. discussed in connection with the figures. In addition, combinations of these schemes can also be used.

In addition, in the embodiments of the present application, words such as "exemplary" and "for example" are used as examples, illustrations or explanations. Any embodiment or design described herein as "example" is not to be construed as preferred or advantageous over other embodiments or designs. Rather, the use of the word example is intended to present concepts in a concrete manner.

In the embodiments of the present application, "corresponding (corresponding, relevant)" and "corresponding (corresponding)" may sometimes be used interchangeably. It should be noted that when the difference is not emphasized, the meanings they intend to express are consistent.

The network architecture and business scenarios described in the embodiments of the present application are for more clearly illustrating the technical solutions of the embodiments of the present application, and do not constitute limitations on the technical solutions provided by the embodiments of the present application. For the evolution of architecture and the emergence of new business scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

Reference to "one embodiment" or "some embodiments" or the like in this specification means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in other embodiments," etc. in various places in this specification are not necessarily All refer to the same embodiment, but mean "one or more but not all embodiments" unless specifically stated otherwise. The terms "including", "comprising", "having" and variations thereof mean "including but not limited to", unless specifically stated otherwise.

In this application, "at least one" means one or more, and "multiple" means two or more. "And/or" describes the association relationship of associated objects, indicating that there can be three types of relationships, for example, A and/or B, which can mean: including the existence of A alone, the existence of A and B at the same time, and the existence of B alone, among which A, B can be singular or plural. The character "/" generally indicates that the contextual objects are an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, c can be single or multiple .

With the development of large-scale integrated circuit (integrated circuit, IC) technology, the logic scale of the chip and the complexity of the circuit are getting higher and higher. In order to ensure the quality of the chip and the time to market, it is necessary to conduct accurate and fast simulation tests on the chip. Simulation testing can be implemented in a software environment through technologies such as universal verification methodology (UVM). However, software simulation is limited by compilation tools and simulation platforms (server performance), the scale of test logic is small, and limited by the computing power of the software environment, the simulation speed is relatively slow. Hardware emulation acceleration (emulation) technology can improve the logic scale and running speed of the DUT by mapping the design under test (DUT) to the hardware platform of the emulator. However, since the generation of the DUT input signal and the processing of the output signal need to be carried out in the software environment, there are frequent signal interactions between the software test and the hardware side during the test process, so that the speed of the chip simulation test is still limited by the software side. run speed.

In view of this, the embodiment of the present application provides a simulation test system. By realizing the generation of the excitation signal and the reception of the response signal in the hardware environment, all simulation behaviors are completed in the hardware environment, thereby avoiding frequent interaction between hardware and software. , so that the simulation speed is consistent with the running speed of the hardware, and the efficiency of the simulation test is improved. In addition, by realizing the decoupling of software and hardware, the logical scale that can be simulated is only related to hardware resources, and is not limited by the computing power of the software simulation platform, thereby increasing the logical scale that can be simulated and improving the efficiency of simulation testing.

FIG. 1 is a schematic diagram of a system architecture of an embodiment of the present application. As shown in FIG. 1 , the simulation test system 10 includes at least a stimulus generator 11 , a scheduler 12 and a general bus model 13 (general bus model, GBM). Among them, the stimulus generator 11 and the scheduler 12 run in the software side environment (such as the operating system of a server or a personal computer), the stimulus generator 11 is used to generate stimulus files, and the scheduler 12 is used to load the stimulus files to the general bus model 13. The general bus model 13 runs in a hardware-side environment (such as a hardware emulator (emulator) or a field programmable logic gate array (fieldprogrammable gate array, FPGA), etc.), and is used to generate a stimulus signal according to a stimulus file and input it to the design under test 20 ( design under test, DUT), and receive the response signal output by the DUT, so as to simulate the behavior to test the function of the DUT. The DUT is a logic circuit to be tested implemented on a hardware simulation platform, such as a system on chip (SOC), a subsystem or a functional module of a chip, and the like. GBM and DUT perform signal interaction based on bus protocol (such as advanced extensible interface (AXI)).

As shown in Figure 1, the scheduler 12 in the simulation test system 10 can schedule multiple GBMs, and each GBM can correspond to the same DUT as shown in the figure, for example, it is used to test different functional modules of the same chip, or it can correspond to Different DUTs, for example, implement collaborative testing of multiple chips on multiple hardware emulators. Correspondingly, the stimulus generator 11 can also generate a plurality of stimulus files, and the stimulus generator 12 can load one or more stimulus files in the GBM according to the requirements. Different stimulus files that can be loaded in different GBMs can also load the same incentive file.

In the above process, the generation and scheduling of the stimulus file can be completed before the DUT simulation behavior starts, and the scheduler 12 can obtain the test result information from the general bus model 13 after receiving the test end signal sent by the GBM. Therefore, the signal interaction between the DUT and the simulation test system 10 in the simulation behavior can only occur between the GBM and the DUT in the hardware environment, and the running process of the simulation test does not depend on the information interaction between the software part and the hardware part in the system. In this way, the decoupling of hardware and software can be realized, the logic scale that can be simulated and the speed of simulation running can be improved, and the efficiency of simulation testing can be improved.

It should be understood that the system architecture shown in Figure 1 only takes the implementation of software and hardware as an example. In order to illustrate that the simulation test system in the embodiment of the application can realize the decoupling of the software part and the hardware part, it does not limit the occurrence of incentives. The controller 11 and the scheduler 12 can only be implemented in a software environment. The stimulus generator 11 and the scheduler 12 can also be implemented in a hardware environment according to system requirements. For example, the stimulus generator can be integrated into the GBM in the form of a functional module, so that the corresponding functions of the stimulus generator and the scheduler can be realized by hardware.

In order to better understand the solution of the embodiment of the present application, the following briefly introduces possible application scenarios of the embodiment of the present application with reference to FIG. 2 .

Fig. 2 is a schematic diagram of an example of an application scenario of the embodiment of the present application. As shown in Figure 2, the DUT and the GBM of the simulation test system provided by the embodiment of the present application complete the simulation behavior of signal interaction, so the DUT and the GBM of this system constitute a test bench (testbench) in this application scenario. Wherein, the DUT may be the design under test 20 in the system architecture shown in FIG. 1 , and the GBM may be the general bus model 13 in the system architecture shown in FIG. 1 . DUT is written by hardware descriptive language (such as Verilog or SystemVerilog, SV, etc.), GBM is written by synthesizable Verilog code (or other languages that can be realized by real circuits), so the two constitute a synthesizable testbench, that is, the test platform It can be synthesized into a real circuit and realized in a hardware platform. For example, in the application scenario shown in Figure 2, the synthesizable testbench works on a hardware emulator.

It should be understood that the testbench shown in Figure 2 is written by synthesizable code, so it can be applied not only to hardware emulation (emulation) platforms, but also to other platforms, such as software emulation (simulation) platforms or FPGA platforms, etc. This application does not Specific limits. For the sake of brevity, the following describes some embodiments of the present application by taking GBM applied to a hardware acceleration platform as an example, but it is clear to those skilled in the art that this description does not limit the scope of the present application.

In this case, FIG. 3 shows a schematic structural block diagram of a simulation test system 300 provided by an embodiment of the present application.

As shown in FIG. 3 , the system 300 includes: a stimulus generator 310 , a scheduler 320 , and a general bus model 330 . Optionally, the system 300 can be the simulation test system 10 in the architecture shown in Figure 1, the excitation generator 310 can be the excitation generator 11 in the architecture shown in Figure 1, and the scheduler 320 can be the The scheduler 12 and the general bus model 330 may be the GBM in the architecture shown in FIG. 1 . Wherein, the universal bus model 330 is realized by hardware.

Specifically, the stimulus generator 310 is used to generate a stimulus file, and the stimulus file is used to instruct the operation of performing a simulation test on the DUT. For example, the stimulus generator 310 can generate GBM-readable instruction information and corresponding debugging information according to the function of the DUT to be tested, wherein the instruction information uses binary instructions to indicate the operations performed by the GBM on the DUT, such as writing data or reading data, etc. The debug information uses hexadecimal to explain the operation indicated by the instruction information. Wherein, each piece of instruction information may also be referred to as an excitation vector. A file consisting of at least one stimulus vector is called a stimulus file, which is used to describe a series of simulation tests performed on the DUT. It should be understood that the encoding format of instruction information is not limited to binary, and other encoding formats that hardware devices can understand can also be used; similarly, the encoding format of debugging information is not limited to hexadecimal, and other user-friendly testers can be used to read encoding format.

Specifically, the scheduler 320 is used to load the stimulus file to the general bus model. For example, the scheduler 320 can distribute the stimulus files generated by the stimulus generator 310 to corresponding GBMs. For example, the scheduler 320 may interact with a static random access memory (SRAM) of the GBM, and download the stimulus file into the SRAM of the GBM. Optionally, the scheduler 320 may also upload the test result information stored by the GBM in the SRAM to the server or user equipment, so that the user can obtain the test result after the simulation test is completed.

Optionally, the scheduler 320 may also include the following functions according to user requirements. Optionally, the scheduler 320 can monitor key signals in the hardware logic operation, for example, add a probe to monitor the test completion signal of the GBM, and determine that the round of simulation testing ends when all the test completion signals of the GBM are detected; The probe monitors the response error signal of the GBM, so that the GBM that has a problem in the test can be debugged; another example, add a probe to the DUT to monitor the key signal in the DUT operation, so as to locate the cause of the problem when the test occurs. Optionally, the scheduler 320 can control the operation of the entire test platform, for example, initialize the DUT, reset the clock of the DUT, etc. before the simulation test starts; Simulate the scenario; another example, suspend the DUT clock and/or GBM to debug the GBM that has problems running.

Specifically, the universal bus model 330 is used to generate stimulus signals according to the stimulus files to conduct simulation tests on the DUT; receive response signals to determine the results of the simulation tests. Wherein, the excitation signal is an input signal recognizable by the DUT, and the response signal is an output signal sent by the DUT according to the excitation signal. For example, the universal bus model 330 can analyze the stimulus vector to determine the operation of the DUT and the information required for the operation. For example, the write operation needs to determine the write address and write data, and the read operation needs to determine the read address. The universal bus model 330 According to the parsed information, the signal interaction with the DUT is carried out through the corresponding channel stipulated by the standard protocol used by the DUT.

Taking the AXI bus protocol as an example, the write operation uses three channels: the write address channel, the write data channel, and the write response channel. GBM sends a signal indicating the address of the written data to the DUT through the write address channel, and sends a signal to the DUT through the write data channel. The signal indicating the written data receives the response signal of the write operation sent by the DUT through the write response channel. The read operation uses two channels: the read address channel and the read response channel. The GBM sends a signal indicating the address of the read data to the DUT through the read address channel, and receives the response signal of the read operation sent by the DUT and the read data through the write response channel. signal of. Optionally, the GBM may only include channels used for write operations, or only channels used for read operations, or both channels used for write operations and read operations, which is not specifically limited in this application. It should be understood that this application only uses the AXI bus protocol as an example to illustrate the process of signal interaction between the GBM and the DUT, and does not constitute a limitation on the specific interface of the GBM. The GBM can also provide other interfaces required by other bus standard protocols as required. Optionally, GBM can also expand the control signals beyond the bus standard protocol according to the test requirements, for example, the test completion signal (gbm_test_done) is used to indicate the completion of the simulation test, and the response error signal (gbm_error) is used to indicate that the test results are inconsistent with expectations. The above scalable control signal can be monitored in the background through the scheduler 320 , or can be integrated into the interrupt circuit of the SOC, and the test status of the GBM can be monitored through devices such as a central processing unit (CPU).

Through the technical solution of the embodiment of the application, the simulation test system can realize the generation of the excitation signal and the receiving process of the response signal in the hardware environment, so that all simulation behaviors are completed in the hardware environment, and the solution of software and hardware in the simulation process is realized. Coupling avoids frequent interaction between hardware and software, improves the speed of simulation testing and the scale of logic that can be simulated, thereby improving the efficiency of simulation testing.

The simulation test system provided by the embodiment of the present application is described above with reference to FIG. 1 to FIG. 3 , and the implementation methods of the excitation generator 310 and the general bus model 330 in the embodiment of the present application are respectively introduced in detail below.

FIG. 4 shows a schematic structural diagram of an excitation generator 310 provided by an embodiment of the present application. The structure of the excitation generator 310 will be described below with reference to FIG. 4 .

As shown in Figure 4, the incentive file is generated by generating instruction fields and then splicing the instruction fields into instruction information. Correspondingly, the excitation generator 310 may include: a field generation module 312 and a field concatenation storage module 315 .

Specifically, the field generation module 312 is used to generate an instruction field satisfying the constraint file according to the constraint file. For example, a constraint file can constrain four attributes of each field: field type (type), field bit width (width), field constraint list (cons), and field weight list (weight). Among them, the field type (type) is used to indicate the function of the instruction field. Taking the write operation instruction in the AXI protocol as an example, it can include the address field (awaddr), data volume field (awlen), data size field (awsize), etc.; The field bit width (width) is used to indicate the number of bytes occupied by the instruction field in the instruction; the field constraint list (cons) is used to indicate the value range of the instruction field; the field weight list (weight) is used to indicate the The weight of the directive field in the directive.

Optionally, according to the incentive type selected by the user, the way the field generating module 312 generates the instruction field may be different. For example, incentive types may include random address incentives, continuous address incentives, and weighted address incentives. Among them, the continuous address stimulus is generated in such a way that the field generation module 312 determines the initial awaddr, fixed awlen, and fixed awsize according to the corresponding field constraint list (cons), thereby determining at least one stimulus vector with continuous addresses; random address stimulus The stimulus vectors of the stimulus and weighted address stimulus are randomly generated, that is, the field generation module 312 determines random awaddr, awlen and awsize according to the corresponding field constraint list (cons), so as to generate at least one stimulus vector with a random address. Among them, the field constraint list (cons) can be a specific value, such as determined from a random number table, or a range of values, such as any value between two specified values, which is not specifically limited in this application .

Specifically, the field splicing storage module 315 is used to splice instruction fields to generate instruction information, and determine corresponding debugging information according to the instruction information. Still taking the write operation instruction in the AXI protocol as an example, the field splicing storage module 315 can splice the fields such as awaddr, awlen, and awsize generated by the field generation module 312 into a piece of instruction information, which can be decoded by GBM and used to indicate that a specific An amount of data with a specific size is written to a specific address of the DUT. Correspondingly, the field splicing storage module 315 can convert the instruction information into an encoding format that is easy to be read by user testers, so as to generate debugging information, and play a role in explaining the content of the instruction information. A complete instruction information can also be called an incentive vector, and the incentive vector and the corresponding debugging information are temporarily stored in the field splicing storage module 315 until the number of generated incentive vectors meets the requirements of the incentive file, and the stored set of incentive vectors is output as A stimulus file. And store the corresponding debugging information in the user's device or server, so that the user's tester can view it during debugging.

Optionally, the way in which multiple incentive vectors are continuously generated in the incentive file may be different according to the incentive type. The incentive types include but are not limited to: random address incentives, continuous address incentives, and weighted address incentives. For example, after the field splicing storage module 315 generates and stores the first excitation vector, if the number of the stored excitation vectors is less than the number of excitation vectors required by the excitation file, then continue to generate the second excitation vector, for the random address excitation, the second excitation vector The instruction field of the vector is randomly determined from the same field constraint list (cons) as the first stimulus vector; for continuous address stimulus, the awaddr of this second stimulus is consecutive to the address where the first stimulus was suspended, and uses the same fixed awlen and awsize; for weighted address incentives, a group of incentive vectors is further divided into multiple subgroups according to the weight value, the incentive vectors of the same subgroup are randomly determined according to the same field constraint list (cons), and the incentive vectors of different subgroups The vectors are determined randomly according to the different field constraint lists (cons). For example, the number of stimulus vectors predicted by the weighted address stimulus file is N (N is a positive integer greater than 1), wherein the first subgroup has N1 vectors, the second subgroup has N2 stimulus vectors, and the third subgroup has N3 stimulus vectors ( N1, N2 and N3 are positive integers, and N1+N2+N3=N), the corresponding field constraint list (cons) can give 6 values a1 to a6, then the instruction field of the excitation vector in the first subgroup can be Take a random value in the range from a1 to a2, the command field of the stimulus vector in the second subgroup can take a random value in the range from a3 to a4, and the command field of the stimulus vector in the third subgroup can take a value from a5 to a random value in the range a6.

According to the above example, it can be seen that the weighted address stimulus file realizes the generation of random instruction fields with different ranges for the stimulus vectors of different subgroups in the same stimulus file, but because the stimulus vectors are generated sequentially, the stimulus vectors of the same subgroup are adjacent. In order to make the stimulus file simulate the real situation more, the order of the stimulus vectors in the weighted address stimulus file can also be disturbed.

In this case, optionally, the excitation generator 310 may also include an out-of-order processing module 314, configured to perform out-of-order processing on the excitation vectors generated by the field splicing storage module 315 when the excitation type is address weighted, so as to rearrange The order of the stimulus vectors in the stimulus file.

Since each instruction field is independently generated, although the instruction field generated by the field generation module 312 can satisfy the constraint file, it may not conform to the standard protocol used by the DUT when spliced. Therefore, after the instruction field is generated, the instruction can also be Fields are optionally preprocessed. Preprocessing may include address preprocessing and/or preprocessing across 4K boundaries.

In this case, optionally, the stimulus generator 310 may also include a preprocessing module 313 for preprocessing the instruction field so that it meets the standard protocol used by the DUT. Optionally, the preprocessing module 313 includes an address preprocessing module 313 and/or a cross-4K boundary preprocessing module 313 . For example, taking AXI as an example, when the AXI bus performs narrowband transmission, the lower bit of the address field will be assigned a value of 0. For example, when the data bus bit width is 128bit, the size is configured as 3, and the end number of the address field can only be 0, 4, 8, and c values, so if the DUT is for narrowband transmission, the address field generated by the field generation module 312 can be preprocessed. For another example, the address of the AXI bus is generally not allowed to cross the 4K boundary. Although the start address generated by the field generation module 312 can meet the requirements, the randomly generated data amount (len) field may cause the end address to exceed the 4K boundary when the field is too large. Therefore The amount of data (len) field can be preprocessed into two shorter fields. It should be understood that the above two preprocessing situations are only for illustration, and the instruction field may be preprocessed in other ways according to requirements and actual bus protocol conditions, which is not specifically limited in this application.

Since the constraint file can be input by the user according to the test requirements, or it may not conform to the standard protocol used by the DUT, the value and format self-checking of the constraint file can also be optionally performed before the instruction field is generated.

In this case, optionally, the stimulus generator 310 may further include a constraint format self-check module 311, configured to determine whether the format of the constraint file is correct. For example, check that the value in the field constraint list cannot be larger than the expressiveness of the field bit width. For another example, taking the AXI protocol as an example, the AXI protocol specifies the field bit width for some types of fields, so it can be checked whether the field type matches the field bit width. For another example, if the incentive of the address weighting type is selected, it may also be checked whether the field constraint list provides multiple value ranges, etc.

The excitation generator 310 in the system provided by the embodiment of the present application is described above with reference to FIG. 4 , and the structure of the general bus model 330 is described below with reference to FIG. 5 .

FIG. 5 shows a schematic structural diagram of a general bus model provided by an embodiment of the present application. As mentioned above, GBM can process write operations or read operations separately according to the requirements of the simulation test. Therefore, it should be understood that what is shown in Figure 5 is only a case where the GBM handles both write operations and read operations, and is not a limitation on the structure of the GBM. The GBM provided in the embodiment of the present application may only include the Some of the modules in FIG. 5 may also include only some of the modules related to the read operation in FIG. 5 , or include all the modules in FIG. 5 . In the following, the composition of the GBM provided by the implementation of the present application will be introduced respectively according to the write operation and the read operation.

As shown in Figure 5, the DUT write operation is simulated, and the general bus model 330 may include: write channel decoding module 3311, write address control module 3312, write data control module 3313, write response recording module 3314, write stimulus storage module 3315 .

Specifically, the write incentive storage module 3315 is configured to receive the incentive file loaded into the GBM by the scheduler, and store the write incentive vector in the incentive file. Wherein, the stimulus vector indicating the write operation to the DUT in the stimulus file is called a write stimulus vector.

Optionally, when it is necessary to schedule the trigger timing of the write stimulus vector, for example, when there are multiple write stimulus vectors in the stimulus file that need to be executed sequentially, or when the write stimulus vector needs to be triggered at a specific time, etc., the GBM can also store Stimulus vector, trigger the corresponding stimulus vector when the condition is met. In this case, the write stimulus storage module 3315 may also be configured to send the write stimulus vector to the write channel decoding module 3311 when the trigger condition of the write stimulus vector is met. For example, the write incentive storage module 3315 can store the write incentive vector in the incentive file, monitor the operating status of the system at the same time, and decide to send the write vector to the write channel decoding module 3311 according to the downstream status of the system. Taking the AXI bus protocol as an example, the write stimulus vector may include a count (num) field, and when the counter of the write address channel matches the num field of the write stimulus vector, the write stimulus vector is invoked. The write stimulus storage module 3315 can also select other trigger conditions according to the requirements of the simulation test, which are not specifically limited in this application, for example, trigger the corresponding write stimulus vector at a specific time of the DUT clock.

Specifically, the write channel decoding module 3311 is used to decode the write excitation vector to determine the write address channel signal and the write data channel signal. Wherein, the write address channel signal is used to indicate the address for writing data into the DUT, and the write data channel signal is used to indicate the data written into the DUT. For example, the write channel decoding module 3311 can extract the instruction field needed for the write operation from the write stimulus vector according to the bus standard protocol used by the DUT, so as to determine the address and data written into the DUT.

Optionally, the write address channel signal and the write data channel signal may be directly determined according to the value of the corresponding command field, or may be determined briefly according to the value of other command fields. For example, the write stimulus vector may include an address field for indicating the address for writing data to the DUT, and may also include a data field for indicating the data written to the DUT, thereby increasing the decoding speed. For another example, the data field may not be included in the write stimulus vector, and the data written to the DUT may be determined according to the mapping relationship between the identification code (id) field in the write stimulus vector and the pre-stored data in the GBM, or according to the address field in the write stimulus vector Obtained by encoding/decoding, thereby simplifying the content of the excitation vector.

Specifically, the write address control module 3312 is used to send a write address channel signal to the DUT. For example, taking the DUT using the AXI bus protocol as an example, the write address control module 3312 can send signals to the DUT through the write address channel, and control the timing and level of the write address channel signal according to the write address determined by the write channel decoding module 3311, thereby indicating The address where DUT writes data.

Specifically, the write data control module 3313 is used to send a write data channel signal to the DUT. For example, taking the DUT using the AXI bus protocol as an example, the write data control module 3313 can send a signal to the DUT through the write data channel. While the write address channel sends the write address signal to the DUT, the write data control module 3313 can control the timing and level of the write data channel signal according to the write data determined by the write channel decoding module 3311, thereby indicating the data written by the DUT.

Specifically, the write response recording module 3314 is used to receive the write response channel signal sent by the DUT. For example, taking the DUT using the AXI bus protocol as an example, the write response recording module 3314 can receive the response signal returned by the DUT through the write response channel, wherein the write response signal indicates whether the write operation is successful.

Through the technical solution of the embodiment of the present application, GBM can analyze the write stimulus vector in the hardware environment, and use the hardware interface provided by the standard protocol to perform signal interaction with the DUT, thereby realizing the simulation test of the write operation by the hardware, and verifying the correctness of the DUT write operation sex.

The modules required for the simulation of the write operation to the DUT have been described above, and the relevant modules of the simulation of the read operation will be described below. As shown in FIG. 5 , to simulate the read operation of DUT, the general bus model 330 may include: a read channel decoding module 3321 , a read address control module 3322 , a read response record module 3323 , and a read stimulus storage module 3324 .

Specifically, the read stimulus storage module 3324 is configured to receive the stimulus file loaded into the GBM by the scheduler, and store the read stimulus vector in the stimulus file. Wherein, the stimulus vector indicating the read operation on the DUT in the stimulus file is called the read stimulus vector.

Optionally, the read stimulus storage module 3324 may also be configured to send the read stimulus vector to the read channel decoding module 3321 when the trigger condition of the read stimulus vector is satisfied. Optionally, the implementation of the read channel decoding module 3321 may be similar to that of the write channel decoding module 3311, and reference may be made to the above description of the write channel decoding module 3311, which will not be repeated here.

Specifically, the read channel decoding module 3321 is used to decode the read excitation vector to determine the read address channel signal. Wherein, the read address channel signal is used to indicate the address for reading data from the DUT. For example, the read channel decoding module 3321 can extract the instruction field needed for the read operation from the read stimulus vector according to the bus standard protocol used by the DUT, so as to determine the address for reading data from the DUT. Optionally, the implementation of the read channel decoding module 3321 may be similar to that of the write channel decoding module 3311, and reference may be made to the above description of the write channel decoding module 3311, which will not be repeated here.

Specifically, the read address control module 3322 is used to send a read address channel signal to the DUT. For example, taking the DUT using the AXI bus protocol as an example, the read address control module 3322 can send signals to the DUT through the read address channel, and control the timing and level of the read address channel signal according to the read address determined by the read channel decoding module 3321, thereby indicating DUT read data address.

Specifically, the read response recording module 3323 is used to receive the read response channel signal sent by the DUT. For example, taking the DUT using the AXI bus protocol as an example, the read response recording module 3323 can receive the response signal returned by the DUT through the read response channel, wherein the read response signal can indicate whether the read operation is successful. Optionally, the read response recording module 3323 can also be used to receive the read data sent by the DUT through the read response channel, so that in addition to verifying the correctness of the DUT read and write operations, the GBM can also be used to verify the correctness of the read and write data .

Through the technical solution of the embodiment of the present application, GBM can analyze the read stimulus vector in the hardware environment, and use the hardware interface provided by the standard protocol to perform signal interaction with the DUT, thereby realizing the simulation test of the read operation by the hardware, and verifying the correctness of the DUT read operation sex.

The above describes the relevant modules required by GBM for reading and writing operation simulation. In some possible cases, it is also necessary to determine the test result information of the stimulus file according to the response result of each read/write stimulus vector in the stimulus file.

In this case, optionally, the universal bus model 330 may also include a process monitoring module, configured to determine test result information according to the response signal; and send the test result information to the scheduler. The test result information may include but not limited to at least one of the following: number of successful read/write operations, number of failed read/write operations, relevant information of failed read/write operations, response speed of read/write operations, and the like. For example, the process monitoring module can count the number of completed read/write operations according to the operation results reflected by the response signal received from the DUT, and can also count the number of successful read/write operations that are consistent with expectations, and the number of operations that are inconsistent with expectations Failed read/write operands. Further, for failed read/write operations, the process monitoring module can also record relevant information (such as read/write address) in the corresponding stimulus vector, so as to facilitate the determination of the cause of the response error. Optionally, the process monitoring module can also analyze the response signal, for example, determine the delay of the read/write operation according to the time when the read/write address channel sends out the signal and the time interval when the read/write response channel receives the signal, and further The average latency of read/write operations can be determined according to the latency of each read/write operation, so as to analyze the response speed of read/write operations.

Optionally, the process monitoring module can also generate a test completion signal and/or respond to an error signal so that the scheduler 320 can monitor the test status of the GBM. For example, when all the stimulus vectors in the stimulus file are executed, the process monitoring module can generate a test completion signal. For another example, when the received response signal is inconsistent with the expected response, the process monitoring module may generate a response error signal.

The system embodiment of the simulation test provided by the present application is described above with reference to FIG. 1 to FIG. 5 , and the method embodiment of the simulation test provided by the present application is described below with reference to FIG. 6 . It should be understood that the method embodiments correspond to the system embodiments, and similar descriptions may refer to the system embodiments.

Fig. 6 shows a schematic flow chart of a simulation test method provided by an embodiment of the present application. Optionally, the method in FIG. 6 may be executed by the system 300 in FIG. 3 .

As shown in Fig. 6, the method includes the following steps.

S610: The excitation generator generates an excitation file.

Specifically, the stimulus generator is used to generate a stimulus file, and the stimulus file is used to instruct the operation of the simulation test on the DUT. Optionally, step S610 may be performed by the excitation generator 310 in the system shown in FIG. 3 .

S620: The scheduler loads the stimulus file into the general bus model.

Specifically, the scheduler can distribute the stimulus file generated by the stimulus generator to the corresponding GBM. Optionally, step S620 may be executed by the scheduler 320 in the system shown in FIG. 3 .

S630: The general bus model generates stimulus signals according to the stimulus files, and sends the stimulus signals to the design under test for simulation testing.

S640: The general bus model receives the response signal, and determines a simulation test result according to the response signal.

Specifically, the universal bus model generates stimulus signals according to the stimulus files to perform a simulation test on the DUT; receives a response signal to determine the result of the simulation test. Wherein, the excitation signal is an input signal recognizable by the DUT, and the response signal is an output signal sent by the DUT according to the excitation signal. Optionally, steps S630 and S640 may be executed by the general bus model 330 in the system shown in FIG. 3 .

Through the technical solution of the embodiment of the present application, by realizing the generation of the excitation signal and the receiving process of the response signal in the hardware environment, all simulation behaviors are completed in the hardware environment, realizing the decoupling of software and hardware in the simulation process, avoiding The frequent interaction between hardware and software improves the speed of simulation testing and the logic scale that can be simulated, thereby improving the efficiency of simulation testing.

For the above step S610, optionally, the stimulus generator generates the stimulus file, including: using a field generation module to generate an instruction field satisfying the constraint file according to the constraint file, wherein the constraint file is used to indicate the value range of the instruction field; The splicing storage module is used to generate instruction information according to the splicing instruction field, and the instruction information is used to indicate the operation of the general bus model to be tested.

Optionally, the stimulus generator generating the stimulus file further includes: determining debugging information according to instruction information by splicing storage modules, and the debugging information is used to explain the contents of the instruction information.

Optionally, generating the stimulus file by the stimulus generator further includes: preprocessing the instruction field through a preprocessing module so that it meets the standard protocol used by the general bus model.

Optionally, generating the stimulus file by the stimulus generator further includes: determining whether the format of the constraint file is correct through a constraint format self-test module.

For the above steps S630 to S640, optionally, it includes: decoding the write excitation vector through the write channel decoding module to generate the write address channel signal and the write data channel signal, wherein the write address channel signal is used to indicate writing to the design under test The address of the input data, the write data channel signal is used to indicate the data written to the design under test; through the write address control module, send the write address channel signal to the design under test; through the write data control module, send the write data to the design under test A channel signal: through the write response recording module, the write response channel signal is received, and the write response channel signal is used to indicate whether the write operation is successful.

Optionally, the above steps further include: storing the write stimulus vector through the write stimulus storage module; and sending the write stimulus vector to the write channel decoding module when a trigger condition of the write stimulus vector is met.

Optionally, the above steps further include: decoding the read excitation vector through the read channel decoding module to determine the read address channel signal, wherein the read address channel signal is used to indicate the address for reading data from the design under test; through the read address control The module sends the read address channel signal to the design under test; the read response channel signal is received through the read response recording module, and the read response channel signal is used to indicate whether the read operation is successful.

Optionally, the above steps further include: storing the read stimulus vector through the read stimulus storage module; and sending the read stimulus vector to the read channel decoding module when a trigger condition of the read stimulus vector is satisfied.

Optionally, the above steps further include: through the process monitoring module, according to the response signal, determining test result information, the test result information is used to indicate the result of the simulation test; sending the test result information to the scheduler.

Optionally, the above method further includes: the scheduler receives the test result information, and uploads the test result information to the server.

Optionally, the above method further includes: the scheduler monitors the running state of the design under test, so that the user can debug the design under test according to the running state.

Optionally, the above method further includes: the scheduler sends a control signal to the general bus model, and the control signal is used to control the general bus model to start or stop.

Optionally, the above method further includes: the scheduler sends an initialization signal to the design under test, and the initialization signal is used to restore the design under test to a state before the simulation test.

The present application also provides a system 100 for simulation testing. As shown in FIG. 7 , the system 100 includes: a bus 102 , a processor 104 , a memory 106 , a communication interface 108 and a hardware emulation device 110 . The processor 104 , the memory 106 and the communication interface 108 communicate through the bus 102 , and the hardware emulation device 110 communicates with other components of the system through the communication interface 108 . It should be understood that the present application does not limit the number of processors and memories in the system 100 .

The bus 102 may be a peripheral component interconnect standard (peripheral component interconnect, PCI) bus or an extended industry standard architecture (extended industry standard architecture, EISA) bus or the like. The bus can be divided into address bus, data bus, control bus and so on. For ease of representation, only one line is used in FIG. 3 , but it does not mean that there is only one bus or one type of bus. Bus 102 may include pathways for transferring information between various components of system 100 (eg, memory 106 , processor 104 , communication interface 108 ).

The processor 104 may include a central processing unit (central processing unit, CPU), a graphics processing unit (graphics processing unit, GPU), a microprocessor (micro processor, MP) or a digital signal processor (digital signal processor, DSP), etc. Any one or more of them.

The memory 106 may include a volatile memory, such as a random access memory (random access memory, RAM). The processor 104 may also include a non-volatile memory (non-volatile memory), such as a read-only memory (read-only memory, ROM), a flash memory, a mechanical hard disk (hard diskdrive, HDD) or a solid state disk (solid state drive, SSD).

Executable program codes are stored in the memory 106, and the processor 104 executes the executable program codes to respectively realize the functions of the stimulus generator, the scheduler, the general bus model or each module in the aforementioned system, thereby realizing the method for the above-mentioned simulation test . That is, the memory 106 stores instructions for executing the method for the simulation test described above.

The communication interface 108 implements communication between the system 100 and other devices or communication networks by using transceiver modules such as but not limited to network interface cards and transceivers.

The hardware emulation device 110 uses, for example but not limited to, an emulator based on a processor array (CPU-based) or an emulator based on a field programmable gate array (FPGA-based) to perform the above emulation testing method that needs to be executed on the hardware side A step of.

The embodiment of the present application also provides a chip, the chip includes a processor and a data interface, and the processor reads the instructions stored in the memory through the data interface, so as to execute the above simulation test method.

The embodiment of the present application also provides a computer program product including instructions. The computer program product may be a software or program product containing instructions, executable on a computing device or stored on any available medium. When the computer program product is run on at least one computing device, at least one computing device is caused to perform the above-mentioned simulation test method.

The embodiment of the present application also provides a computer-readable storage medium. The computer-readable storage medium may be any available medium that a computing device can store, or a data storage device such as a data center that includes one or more available media. The available medium may be a magnetic medium (for example, a floppy disk, a hard disk, or a magnetic tape), an optical medium (for example, a DVD), or a semiconductor medium (for example, a solid-state hard disk), and the like. The computer-readable storage medium includes instructions, and the instructions instruct a computing device to perform the above simulation test method.

The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, all possible combinations of the technical features in the above-mentioned embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, should be considered as within the scope of this specification.

The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: it can still apply to the foregoing embodiments The recorded technical solutions are modified, or some of the technical features are replaced equivalently; and these modifications or replacements do not make the essence of the corresponding technical solutions depart from the protection scope of the technical solutions of each embodiment of the application.

Claims (34)

1. A system for simulation testing, the system comprising a stimulus generator and a scheduler implemented on a software side and a generic bus model implemented on a hardware side, wherein,

the excitation generator is used for generating an excitation file, and the excitation file is used for indicating the operation of carrying out simulation test on the design to be tested;

the scheduler is used for loading the excitation file to the universal bus model;

the universal bus model is used for generating an excitation signal according to the excitation file and sending the excitation signal to the design to be tested for simulation test;

the universal bus model is further configured to receive a response signal, and determine a result of the simulation test according to the response signal, where the response signal is an output signal sent by the design to be tested according to the excitation signal.

2. The system of claim 1, wherein the stimulus file includes a write stimulus vector for indicating a write operation to the design under test, the stimulus signals include write address channel signals and write data channel signals, the response signals include write response channel signals,

the universal bus model comprises:

a write stimulus storage module for storing the write stimulus vector;

a write channel decoding module, configured to decode the write excitation vector to generate the write address channel signal and the write data channel signal, where the write address channel signal is used to indicate an address for writing data to the design to be tested, and the write data channel signal is used to indicate data written to the design to be tested;

the write address control module is used for sending the write address channel signal to the design to be tested;

the data writing control module is used for sending the data writing channel signal to the design to be tested;

and the write response recording module is used for receiving the write response channel signal, and the write response channel signal is used for indicating whether the write operation is successful or not.

3. The system of claim 2, wherein the write stimulus storage module is further configured to:

and when the trigger condition of the write excitation vector is met, sending the write excitation vector to the write channel decoding module.

4. The system of any of claims 1-3, wherein the stimulus file includes a read stimulus vector for indicating a read operation on the design under test, the stimulus signals include read address channel signals, the response signals include read response channel signals,

the universal bus model comprises:

a read excitation storage module for storing the read excitation vector;

a read channel decoding module, configured to decode the read excitation vector to generate the read address channel signal, where the read address channel signal is used to indicate an address for reading data from the design to be tested;

the read address control module is used for sending the read address channel signal to the design to be tested;

and the read response recording module is used for receiving the read response channel signal, and the read response channel signal is used for indicating whether the read operation is successful or not.

5. The system of claim 4, wherein the read stimulus storage module is further configured to:

and when the trigger condition of the read excitation vector is met, sending the read excitation vector to the read channel decoding module.

6. The system of any one of claims 1 to 3, wherein the generic bus model further comprises a process monitoring module configured to:

determining test result information according to the response signal, wherein the test result information is used for indicating the result of the simulation test;

and sending the test result information to the scheduler.

7. The system of claim 6, wherein the scheduler is further configured to:

and receiving the test result information, and uploading the test result information to a server.

8. The system of any of claims 1-3, wherein the scheduler is further configured to:

and monitoring the running state of the design to be tested so that a user can debug the design to be tested according to the running state.

9. The system of any of claims 1 to 3, wherein the scheduler is further configured to:

and sending a control signal to the universal bus model, wherein the control signal is used for controlling the universal bus model to be started or closed.

10. The system of any of claims 1-3, wherein the scheduler is further configured to:

and sending an initialization signal to the design to be tested, wherein the initialization signal is used for restoring the design to be tested to a state before simulation test.

11. The system of any one of claims 1 to 3, wherein the excitation generator comprises:

the field generating module is used for generating an instruction field meeting the constraint file according to the constraint file, wherein the constraint file is used for indicating the value range of the instruction field;

and the field splicing storage module is used for splicing the instruction field to generate instruction information, and the instruction information is used for indicating the operation of the universal bus model on the design to be tested.

12. The system of claim 11, wherein the field stitching module is further configured to:

and determining debugging information according to the instruction information, wherein the debugging information is used for explaining the content of the instruction information.

13. The system of claim 11, wherein the excitation generator further comprises:

and the preprocessing module is used for preprocessing the instruction field so as to enable the instruction field to meet the standard protocol used by the universal bus model.

14. The system of claim 11, wherein the excitation generator further comprises:

and the constraint format self-checking module is used for determining whether the format of the constraint file is correct or not.

15. The system of any one of claims 1 to 3, wherein the stimulus file generated by the stimulus generator comprises at least one of: random address excitation, continuous address excitation, weighted address excitation.

16. The system of any one of claims 1 to 3, wherein the generic bus model is written in synthesizable code.

17. A method of simulation testing, the method being performed by a system of simulation testing, the system comprising a stimulus generator and scheduler implemented on a software side and a generic bus model implemented on a hardware side, the method comprising:

the excitation generator generates an excitation file, and the excitation file is used for indicating the operation of carrying out simulation test on the design to be tested;

the scheduler loads the stimulus file to the generic bus model;

the universal bus model generates an excitation signal according to the excitation file and sends the excitation signal to the design to be tested to perform simulation test;

and the universal bus model receives a response signal and determines the result of the simulation test according to the response signal, wherein the response signal is an output signal sent by the design to be tested according to the excitation signal.

18. The method of claim 17, wherein the stimulus file includes a write stimulus vector that indicates a write operation to the design under test, wherein the stimulus signals include write address channel signals and write data channel signals, wherein the response signals include write response channel signals,

the general bus model generates an excitation signal according to the excitation file and sends the excitation signal to the design to be tested for simulation test, and the method comprises the following steps:

storing, by a write stimulus storage module, the write stimulus vector;

decoding, by a write channel decoding module, the write excitation vector to generate the write address channel signal and the write data channel signal, where the write address channel signal is used to indicate an address for writing data to the design to be tested, and the write data channel signal is used to indicate data for writing to the design to be tested;

sending the write address channel signal to the design to be tested through a write address control module;

sending the write data channel signal to the design to be tested through a write data control module;

the general bus model receives a response signal and determines the result of the simulation test according to the response signal, and the method comprises the following steps:

and receiving the write response channel signal through a write response recording module, wherein the write response channel signal is used for indicating whether the write operation is successful or not.

19. The method of claim 18, wherein the generic bus model generates excitation signals from the excitation files and sends the excitation signals to the design under test for simulation testing, further comprising:

and sending the write excitation vector to a write channel decoding module through a write excitation storage module when the trigger condition of the write excitation vector is met.

20. The method of any of claims 17 to 19, wherein the stimulus file includes a read stimulus vector for indicating a read operation on the design under test, wherein the stimulus signals include read address channel signals, and wherein the response signals include read response channel signals,

the general bus model generates an excitation signal according to the excitation file and sends the excitation signal to the design to be tested for simulation test, and the method comprises the following steps:

storing, by a read stimulus storage module, the read stimulus vector;

decoding, by a read channel decoding module, the read excitation vector to generate the read address channel signal, wherein the read address channel signal is used to indicate an address at which data is read from the design to be tested;

sending the read address channel signal to the design to be tested through a read address control module;

the general bus model receives a response signal and determines the result of the simulation test according to the response signal, and the method comprises the following steps:

and receiving the read response channel signal through a read response recording module, wherein the read response channel signal is used for indicating whether the read operation is successful or not.

21. The method of claim 20, wherein the generic bus model generates excitation signals from the excitation files and sends the excitation signals to the design under test for simulation testing, further comprising:

and sending the read excitation vector to the read channel decoding module through a read excitation storage module when the trigger condition of the read excitation vector is met.

22. The method of any of claims 17 to 19, wherein the generic bus model receives a response signal and determines the result of the simulation test based on the response signal, further comprising:

determining test result information according to the response signal through a process monitoring module, wherein the test result information is used for indicating the result of the simulation test;

and sending the test result information to the scheduler.

23. The method of claim 22, further comprising:

and the dispatcher receives the test result information and uploads the test result information to a server.

24. The method according to any one of claims 17 to 19, further comprising:

and the scheduler monitors the running state of the design to be tested so that a user can debug the design to be tested according to the running state.

25. The method according to any one of claims 17 to 19, further comprising:

and the scheduler sends a control signal to the universal bus model, and the control signal is used for controlling the universal bus model to be started or closed.

26. The method according to any one of claims 17 to 19, further comprising:

and the scheduler sends an initialization signal to the design to be tested, wherein the initialization signal is used for restoring the design to be tested to a state before simulation testing.

27. The method of any one of claims 17 to 19, wherein the stimulus generator generates a stimulus file comprising:

generating an instruction field meeting a constraint file according to the constraint file through a field generation module, wherein the constraint file is used for indicating a value range of the instruction field;

and generating instruction information by a splicing storage module according to the spliced instruction field, wherein the instruction information is used for indicating the operation of the universal bus model on the design to be tested.

28. The method of claim 27, wherein the stimulus generator generates a stimulus file, further comprising:

and determining debugging information according to the instruction information by a splicing storage module, wherein the debugging information is used for explaining the content of the instruction information.

29. The method of claim 27, wherein the stimulus generator generates a stimulus file, further comprising:

and preprocessing the instruction field by a preprocessing module so as to enable the instruction field to meet the standard protocol used by the universal bus model.

30. The method of claim 27, wherein the stimulus generator generates a stimulus file, further comprising:

and determining whether the format of the constraint file is correct or not through a constraint format self-checking module.

31. The method of any of claims 17 to 19, wherein the stimulus file generated by the stimulus generator comprises at least one of: random address excitation, continuous address excitation, weighted address excitation.

32. The method of any one of claims 17 to 19, wherein the generic bus model is written in synthesizable code.

33. A system for simulation testing, comprising: a processor and a memory for storing a computer program, the processor for invoking and executing the computer program stored in the memory to perform the method of any of claims 17-32.

34. A computer-readable storage medium for storing a computer program which causes a computer to perform the method of any one of claims 17 to 32.

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