CN115659885A

CN115659885A - System and method for simulation test

Info

Publication number: CN115659885A
Application number: CN202211702299.6A
Authority: CN
Inventors: 请求不公布姓名
Original assignee: Moore Threads Technology Co Ltd
Current assignee: Moore Threads Technology Co Ltd
Priority date: 2022-12-29
Filing date: 2022-12-29
Publication date: 2023-01-31
Anticipated expiration: 2042-12-29
Also published as: CN115659885B

Abstract

The embodiment of the application relates to the field of integrated circuits, and provides a system and a method for simulation test, wherein the system comprises an excitation generator and a scheduler which are realized on a software side, and a universal bus model which is realized on a hardware side, wherein the excitation generator is used for generating an excitation file; the scheduler is used for loading the excitation file to the universal bus model; the universal bus model is used for generating an excitation signal according to the excitation file and sending the excitation signal to a design to be tested for simulation test; the universal bus model is also used for receiving the response signal and determining the result of the simulation test according to the response signal. By the scheme, all simulation behaviors can be completed in a hardware environment, decoupling of software and hardware is achieved, and simulation test efficiency is improved.

Description

System and method for simulation test

Technical Field

The present application relates to the field of integrated circuit technology, and more particularly, to a system and method for simulation testing.

Background

With the development of large-scale Integrated Circuit (IC) technology, the logic scale of a chip and the complexity of a circuit are higher and higher, and in order to ensure the quality of the chip and the time to market, an accurate and fast simulation test needs to be performed on the chip. The hardware simulation acceleration (emulation) technology can improve the logic scale and the operation speed of a Design Under Test (DUT) by mapping the DUT onto a hardware platform of a hardware simulator (emulator). However, since the generation of DUT input signals and the processing of output signals need to be performed in a software environment, the speed of chip simulation testing is limited by the operating speed of the software side. Therefore, how to improve the efficiency of the chip simulation test becomes an urgent technical problem to be solved.

Disclosure of Invention

The embodiment of the application provides a system and a method for simulation testing, which can enable all simulation behaviors to be completed in a hardware environment, realize decoupling of software and hardware and improve the efficiency of the simulation testing.

In a first aspect, a system for simulation testing is provided, which includes an excitation generator and a scheduler implemented on a software side, and a universal bus model implemented on a hardware side, where the excitation generator is configured to generate an excitation file, and the excitation file is used to indicate an operation of simulation testing on a design to be tested; a scheduler for loading the stimulus file into the generic bus model; the universal bus model is used for generating an excitation signal according to the excitation file and sending the excitation signal to a design to be tested for simulation test; and the universal bus model is also used for receiving a response signal and determining the result of the simulation test according to the response signal, wherein the response signal is an output signal sent by the design to be tested according to the excitation signal.

According to the technical scheme provided by the application, the simulation test system can realize the processes of generating the excitation signal and receiving the response signal in a hardware environment, so that all simulation behaviors are completed in the hardware environment, frequent interaction between hardware and software is avoided, the operation speed of the simulation test is improved, decoupling of the software and the hardware is realized, the logic scale of the simulation test is improved, and the efficiency of the simulation test is improved.

With reference to the first aspect, in some implementations of the first aspect, the stimulus file includes a write stimulus vector for instructing a write operation on the design under test, the stimulus signals include write address channel signals and write data channel signals, the response signals include write response channel signals, and the generic bus model includes: the write excitation storage module is used for storing write excitation vectors; the write channel decoding module is used for decoding the write excitation vector to generate a write address channel signal and a write data channel signal, wherein the write address channel signal is used for indicating an address for writing data into the design to be tested, and the write data channel signal is used for indicating the data written into the design to be tested; the write address control module is used for sending a write address channel signal to the design to be tested; the data writing control module is used for sending a data writing channel signal to the design to be tested; and the write response recording module is used for receiving a write response channel signal, and the write response channel signal is used for indicating whether the write operation is successful or not.

According to the technical scheme provided by the application, the universal bus model can analyze the write excitation vector in a hardware environment, and the hardware interface provided by a standard protocol is utilized to perform signal interaction with the DUT, so that the hardware is used for realizing the simulation test of write operation, and the correctness of the write operation of the DUT is verified.

With reference to the first aspect, in certain implementations of the first aspect, the write stimulus storage module is further configured to: and when the trigger condition of the write excitation vector is met, sending the write excitation vector to a write channel decoding module.

According to the technical scheme provided by the application, the universal bus model can schedule the trigger time and sequence of the write excitation vector, so that the diversity and authenticity of a simulation scene are improved, and the simulation test effect is improved.

With reference to the first aspect, in certain implementations of the first aspect, the stimulus file includes a read stimulus vector for instructing a read operation on the design under test, the stimulus signal includes a read address channel signal, the response signal includes a read response channel signal, and the generic bus model includes: the read excitation storage module is used for storing read excitation vectors; the read channel decoding module is used for decoding the read excitation vector to generate a read address channel signal, wherein the read address channel signal is used for indicating an address for reading data from the design to be tested; the read address control module is used for sending a read address channel signal to the design to be tested; and the read response recording module is used for receiving a read response channel signal, and the read response channel signal is used for indicating whether the read operation is successful or not.

According to the technical scheme provided by the application, the universal bus model can analyze the read excitation vector in a hardware environment and perform signal interaction with the DUT by using a hardware interface provided by a standard protocol, so that the hardware realizes simulation test of read operation and verifies the correctness of the read operation of the DUT.

With reference to the first aspect, in certain implementations of the first aspect, the read stimulus storage module is further configured to: and when the trigger condition of the read excitation vector is met, sending the read excitation vector to a read channel decoding module.

According to the technical scheme provided by the application, the universal bus model can schedule the trigger time and sequence of the read excitation vector, so that the diversity and the authenticity of a simulation scene are improved, and the effect of simulation test is improved.

With reference to the first aspect, in certain implementations of the first aspect, the generic bus model further includes a process monitoring module configured to: determining test result information according to the response signal, wherein the test result information is used for indicating the result of the simulation test; and sending the test result information to the scheduler.

According to the technical scheme provided by the application, the universal bus model can determine the test result of the excitation file according to the response result of each read/write excitation vector in the excitation file, so that the signal sent by the system to be tested is analyzed and converted into more visual test result information, and the signal is convenient for a tester to understand.

With reference to the first aspect, in some implementations of the first aspect, the scheduler is further configured to receive test result information and upload the test result information to the server.

According to the technical scheme provided by the application, the scheduler can obtain the simulation test result sent by the universal bus model and upload the simulation test result to the server or the user equipment, so that a user can obtain the test result at any time after the simulation test is finished.

With reference to the first aspect, in some implementations of the first aspect, the scheduler is further configured to monitor a running state of the design to be tested, so that a user debugs the design to be tested according to the running state.

According to the technical scheme provided by the application, the scheduler can monitor key signals in the hardware logic operation, so that a tester of a user can quickly locate the cause of the problem and debug the problem when the problem occurs in the test, and the efficiency of the simulation test is improved.

With reference to the first aspect, in certain implementations of the first aspect, the scheduler is further configured to send a control signal to the universal bus model, where the control signal is used to control the universal bus model to be turned on or off.

According to the technical scheme provided by the application, the scheduler can control the state of the universal bus model, so that the test process is automatically completed, the use experience of a user is improved, a plurality of chip systems to be tested can be scheduled to work simultaneously, the diversity and the authenticity of a simulation scene are improved, and the simulation test effect is improved.

With reference to the first aspect, in some implementations of the first aspect, the scheduler is further configured to send an initialization signal to the design to be tested, where the initialization signal is used to restore the design to be tested to a state before the simulation test.

According to the technical scheme provided by the application, the scheduler can restore the system to be tested after one round of test is finished or before the next round of test is started, so that the whole system can update the excitation file after one round of simulation test is finished and automatically start the next round of test, and the efficiency of the simulation test is improved.

With reference to the first aspect, in certain implementations of the first aspect, the excitation generator includes: the field generating module is used for generating an instruction field meeting the constraint file according to the constraint file, wherein the constraint file is used for indicating the value range of the instruction field; and the field splicing storage module is used for splicing the instruction fields to generate instruction information, and the instruction information is used for indicating the operation of the universal bus model on the design to be tested.

According to the technical scheme provided by the application, the excitation generator can generate the excitation files meeting the test requirements in batch, so that the data volume of the simulation test is increased, and the accuracy of the simulation test is improved.

With reference to the first aspect, in some implementations of the first aspect, the field splicing module is further configured to determine debugging information according to the instruction information, where the debugging information is used to interpret content of the instruction information.

According to the technical scheme provided by the application, the excitation generator can also generate debugging information for explaining the content of the instruction information, so that a tester of a user can quickly understand the operation of the excitation file indicating the design to be tested, and the debugging of the design to be tested is facilitated.

With reference to the first aspect, in certain implementations of the first aspect, the stimulus generator further includes a preprocessing module, configured to preprocess the instruction field to meet a standard protocol used by a universal bus model.

According to the technical scheme provided by the application, the excitation generator can be used for preprocessing the randomly generated instruction field, so that the condition that the instruction field does not conform to the bus standard protocol used by the design to be tested is avoided, the accuracy of the excitation file is improved, and the effect of simulation test is improved.

With reference to the first aspect, in certain implementations of the first aspect, the stimulus generator further includes a constraint format introspection module configured to determine whether a format of the constraint file is correct.

According to the technical scheme provided by the application, the excitation generator can firstly test the correctness of the constraint file, and the condition that the test requirement input by a user does not conform to the bus standard protocol used by the design to be tested is avoided, so that the accuracy of the excitation file is improved, and the simulation test effect is improved.

With reference to the first aspect, in certain implementations of the first aspect, the excitation file generated by the excitation generator includes at least one of: random address excitation, continuous address excitation, weighted address excitation.

According to the technical scheme provided by the application, the excitation generator can generate various types of excitation files, so that the simulation test system can cover more test scenes, and the accuracy of the simulation test is improved.

With reference to the first aspect, in certain implementations of the first aspect, the generic bus model is written in synthesizable code.

According to the technical scheme provided by the application, the universal bus model is compiled by comprehensive Verilog codes (or other languages which can be realized by real circuits), so that the test platform formed by the universal bus model and the design to be tested can be applied to an embedded hardware simulation test method, and the simulation test efficiency is further improved.

In a second aspect, there is provided a system for simulation testing, the method being performed by the system for simulation testing, the system comprising a stimulus generator and a scheduler implemented on a software side and a generic bus model implemented on a hardware side, the method comprising: the excitation generator generates an excitation file, and the excitation file is used for indicating the operation of carrying out simulation test on the design to be tested; the dispatcher loads the excitation file to the universal bus model; the universal bus model generates an excitation signal according to the excitation file and sends the excitation signal to a design to be tested to perform simulation test; and the universal bus model receives the response signal and determines the result of the simulation test according to the response signal, wherein the response signal is an output signal sent by the design to be tested according to the excitation signal.

With reference to the second aspect, in some implementations of the second aspect, the stimulus file includes a write stimulus vector for instructing a write operation on the design under test, the stimulus signals include write address channel signals and write data channel signals, the response signals include write response channel signals, the universal bus model generates the stimulus signals according to the stimulus file and sends the stimulus signals to the design under test for simulation testing, including: storing, by a write stimulus storage module, the write stimulus vector; decoding the write excitation vector through a write channel decoding module to generate a write address channel signal and a write data channel signal, wherein the write address channel signal is used for indicating an address for writing data into the design to be tested, and the write data channel signal is used for indicating the data written into the design to be tested; sending a write address channel signal to the design to be tested through a write address control module; sending a write data channel signal to the design to be tested through the write data control module; the general bus model receives the response signal and determines the result of the simulation test according to the response signal, and the method comprises the following steps: receiving, by a write response recording module, a write response channel signal, the write response channel signal for indicating whether the write operation was successful.

With reference to the second aspect, in some implementation manners of the second aspect, the generating, by the universal bus model, an excitation signal according to the excitation file, and sending the excitation signal to the design to be tested for simulation testing, further includes: and sending the write excitation vector to a write channel decoding module through the write excitation storage module when the trigger condition of the write excitation vector is met.

With reference to the second aspect, in some implementations of the second aspect, the excitation file includes a read excitation vector for instructing a read operation on the design to be tested, the excitation signal includes a read address channel signal, the response signal includes a read response channel signal, the universal bus model generates the excitation signal according to the excitation file, and sends the excitation signal to the design to be tested for the simulation test, including: storing, by a read stimulus storage module, the read stimulus vector; decoding the read excitation vector through a read channel decoding module to generate a read address channel signal, wherein the read address channel signal is used for indicating an address for reading data from the design to be tested; sending a read address channel signal to the design to be tested through a read address control module; the general bus model receives the response signal and determines the result of the simulation test according to the response signal, and the method comprises the following steps: a read response channel signal is received by the read response recording module, the read response channel signal indicating whether the read operation was successful.

With reference to the second aspect, in some implementations of the second aspect, the generating, by the universal bus model, an excitation signal according to the excitation file, and sending the excitation signal to the design to be tested for the simulation test, further includes: and sending the read excitation vector to a read channel decoding module through the read excitation storage module when the trigger condition of the read excitation vector is met.

With reference to the second aspect, in some implementations of the second aspect, the receiving, by the universal bus model, the response signal and determining a result of the simulation test according to the response signal further include: determining test result information according to the response signal through a process monitoring module, wherein the test result information is used for indicating the result of the simulation test; and sending the test result information to the scheduler.

With reference to the second aspect, in certain implementations of the second aspect, the method further includes: and the dispatcher receives the test result information and uploads the test result information to the server.

With reference to the second aspect, in certain implementations of the second aspect, the method further includes: the scheduler monitors the running state of the design to be tested, so that a user can debug the design to be tested according to the running state.

With reference to the second aspect, in certain implementations of the second aspect, the method further includes: and the scheduler sends a control signal to the universal bus model, and the control signal is used for controlling the universal bus model to be started or closed.

With reference to the second aspect, in certain implementations of the second aspect, the method further includes: and the scheduler sends an initialization signal to the design to be tested, and the initialization signal is used for restoring the design to be tested to the state before the simulation test.

With reference to the second aspect, in some implementations of the second aspect, the stimulus generator generates the stimulus file, including: generating an instruction field meeting the constraint file according to the constraint file through a field generating module, wherein the constraint file is used for indicating the value range of the instruction field; and generating instruction information by the splicing storage module according to the splicing instruction field, wherein the instruction information is used for indicating the operation of the universal bus model on the design to be tested.

With reference to the second aspect, in some implementations of the second aspect, the generating the stimulus file by the stimulus generator further includes: and determining debugging information according to the instruction information by the splicing storage module, wherein the debugging information is used for explaining the content of the instruction information.

With reference to the second aspect, in some implementations of the second aspect, the generating the stimulus file by the stimulus generator further includes: the instruction field is preprocessed by the preprocessing module to meet the standard protocol used by the universal bus model.

With reference to the second aspect, in some implementations of the second aspect, the generating the stimulus file by the stimulus generator further includes: and determining whether the format of the constraint file is correct or not through a constraint format self-checking module.

With reference to the second aspect, in some implementations of the second aspect, the stimulus file generated by the stimulus generator includes at least one of: random address excitation, continuous address excitation, weighted address excitation.

In combination with the second aspect, in some implementations of the second aspect, the universal bus model is written in synthesizable code.

In a third aspect, a system for simulation testing is provided, including: a processor and a memory, the memory being adapted to store a computer program, the processor being adapted to invoke and run the computer program from the memory such that the system performs the method as in the second aspect or any of the possible implementations of the second aspect.

In a fourth aspect, there is provided a computer program product comprising: computer program code which, when executed by a processor of a computing device, causes the computing device to perform the method as in the second aspect or any of the possible implementations of the second aspect.

In a fifth aspect, a computer-readable storage medium is provided, comprising a computer program which, when run on a computer, causes the computer to perform the method as in the second aspect or any one of the possible implementations of the second aspect.

Drawings

Fig. 1 is a schematic system architecture diagram according to an embodiment of the present application.

Fig. 2 is a schematic diagram of an example of an application scenario according to an embodiment of the present application.

Fig. 3 is a schematic structural block diagram of a system for simulation testing according to an embodiment of the present application.

Fig. 4 is a schematic structural block diagram of an excitation generator according to an embodiment of the present application.

Fig. 5 is a schematic structural block diagram of a general bus model provided in an embodiment of the present application.

Fig. 6 is a schematic flow chart diagram of a method for simulation testing according to an embodiment of the present application.

Fig. 7 is a schematic structural block diagram of a simulation test system according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings.

This application is intended to present various aspects, embodiments or features around a system comprising a number of devices, components, modules, and the like. It is to be understood and appreciated that the various systems may include additional devices, components, modules, etc. and/or may not include all of the devices, components, modules etc. discussed in connection with the figures. Furthermore, a combination of these schemes may also be used.

In addition, in the embodiments of the present application, words such as "exemplary", "for example", etc. are used to mean serving as examples, illustrations or explanations. Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, the word using examples is intended to present concepts in a concrete fashion.

In the embodiments of the present application, "corresponding" and "corresponding" may be sometimes used in a mixed manner, and it should be noted that, when differences are not emphasized, intended meanings thereof are consistent.

The network architecture and the service scenario described in the embodiment of the present application are for more clearly illustrating the technical solution of the embodiment of the present application, and do not form a limitation on the technical solution provided in the embodiment of the present application, and it can be known by a person skilled in the art that the technical solution provided in the embodiment of the present application is also applicable to similar technical problems along with the evolution of the network architecture and the appearance of a new service scenario.

Reference throughout this specification to "one embodiment" or "some embodiments," or the like, means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," or the like, in various places throughout this specification are not necessarily all referring to the same embodiment, but rather "one or more but not all embodiments" unless specifically stated otherwise. The terms "comprising," "including," "having," and variations thereof mean "including, but not limited to," unless expressly specified otherwise.

In the present application, "at least one" means one or more, "a plurality" means two or more. "and/or" describes the association relationship of the associated object, indicating that there may be three relationships, for example, a and/or B, which may indicate: including the presence of a alone, a and B together, and B alone, where a and B may be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "at least one of the following" or similar expressions refer to any combination of these items, including any combination of the singular or plural items. For example, at least one (one) of a, b, or c, may represent: a, b, c, a-b, a-c, b-c, or a-b-c, wherein a, b, c may be single or multiple.

With the development of large-scale Integrated Circuit (IC) technology, the logic scale of a chip and the complexity of a circuit are higher and higher, and in order to ensure the quality of the chip and the time to market, an accurate and fast simulation test needs to be performed on the chip. Simulation (simulation) testing can be realized in a software environment by using a Universal Verification Methodology (UVM) technology and the like. However, software simulation is limited by compiling tools and simulation platforms (server performance), the test logic scale is small, the software environment computing capacity is limited, and the simulation speed is slow. The hardware simulation acceleration (emulation) technology can improve the logic scale and the running speed of a Design Under Test (DUT) by mapping the DUT onto a hardware platform of a hardware simulator (emulator). However, since the generation of DUT input signals and the processing of DUT output signals need to be performed in a software environment, there is frequent signal interaction between the software side and the hardware side during the test process, so that the speed of chip simulation test is still limited by the operating speed of the software side.

In view of this, the embodiment of the present application provides a simulation test system, which implements the processes of generating the excitation signal and receiving the response signal in the hardware environment, and completes all simulation behaviors in the hardware environment, thereby avoiding frequent interaction between hardware and software, enabling the simulation speed to be consistent with the hardware running speed, and improving the efficiency of the simulation test. In addition, decoupling of software and hardware is realized, so that the simulative logic scale is only related to hardware resources and is not limited by the computing capacity of a software simulation platform, the simulative logic scale is increased, and the efficiency of simulation testing is improved.

Fig. 1 is a schematic diagram of a system architecture according to an embodiment of the present application. As shown in FIG. 1, the simulation test system 10 includes at least a stimulus generator 11, a scheduler 12, and a General Bus Model (GBM) 13. Wherein the stimulus generator 11 and the scheduler 12 are running in a software-side environment (e.g. an operating system of a server or a personal computer), the stimulus generator 11 is used to generate a stimulus file, and the scheduler 12 is used to load the stimulus file into the generic bus model 13. The universal bus model 13 runs in a hardware side environment (e.g., a hardware simulator (emulator) or a Field Programmable Gate Array (FPGA)), and is configured to generate an excitation signal according to an excitation file, input the excitation signal to a Design Under Test (DUT) 20, and receive a response signal output by the DUT, so as to perform a simulation behavior, thereby testing a function of the DUT. The DUT is a logic circuit to be tested implemented on a hardware simulation platform, such as a System On Chip (SOC), a subsystem or a functional module of a chip, and the like. The GBM interacts with the DUT with signals based on a bus protocol, such as advanced extensible interface (AXI).

As shown in fig. 1, the scheduler 12 in the simulation test system 10 may schedule a plurality of GBMs, each GBM may correspond to the same DUT as shown in the figure, for example, different functional modules respectively used for testing the same chip, or may correspond to different DUTs respectively, for example, a plurality of hardware simulators may implement a cooperative test of multiple chips. Correspondingly, the stimulus generator 11 may also generate a plurality of stimulus files, and the stimulus generator 12 may load one or more stimulus files in the GBM according to requirements, different stimulus files that may be loaded in different GBMs, or the same stimulus file.

In the above process, the generation of the stimulus file and the scheduling may be completed before the simulation behavior of the DUT starts, and the scheduler 12 may obtain the test result information from the generic bus model 13 after receiving the test end signal sent by the GBM. Therefore, the signal interaction between the DUT and the simulation test system 10 in the simulation behavior can only occur between the GBM and the DUT in the hardware environment, and the operation process of the simulation test is independent of the information interaction of the software part and the hardware part in the system. Therefore, decoupling of hardware and software can be achieved, the simulation logic scale and the simulation running speed are improved, and the simulation test efficiency is improved.

It should be understood that the system architecture shown in fig. 1 is only implemented in two parts, namely software and hardware, and for the purpose of explaining that the system for simulation test in the embodiment of the present application can implement decoupling of the software part and the hardware part, it is not limited that the excitation generator 11 and the scheduler 12 can only be implemented in a software environment. The stimulus generator 11 and the scheduler 12 may also be implemented in a hardware environment according to system requirements, for example, the stimulus generator may be integrated in the GBM in the form of functional modules, so that the respective functions of the stimulus generator and the scheduler are implemented by hardware.

For better understanding of the solution of the embodiment of the present application, a brief description is given below to a possible application scenario of the embodiment of the present application with reference to fig. 2.

Fig. 2 is a schematic diagram of an example of an application scenario according to an embodiment of the present application. As shown in fig. 2, the DUT and the GBM of the simulation test system provided in this embodiment complete the simulation behavior of signal interaction, so that the DUT and the GBM of the simulation test system form a test platform (testbench) in this application scenario. The DUT may be the design under test 20 in the system architecture shown in FIG. 1, and the GBM may be the universal bus model 13 in the system architecture shown in FIG. 1. The DUT is written in a hardware descriptive language (e.g., verilog or systemvverilog, SV, etc.), and the GBM is written in synthesizable Verilog code (or other language implementable by real circuits), so that both constitute synthesizable testbench, i.e., the test platform can be synthesized into real circuits and thus implemented in a hardware platform. The synthesizable testbench works on a hardware emulator (emulator) in an application scenario such as that shown in fig. 2.

It should be understood that the testbench shown in fig. 2 is written by synthesizable code, and therefore, the testbench can be applied not only to a hardware simulation (emulation) platform, but also to other platforms, such as a software simulation (emulation) platform or an FPGA platform, and the application is not limited in particular. For the sake of brevity, some embodiments of the present application are described below with reference to GBM as an example applied to a hardware acceleration platform, but it is clear to those skilled in the art that this description does not constitute a limitation to the scope of the present application.

In this case, fig. 3 shows a schematic structural block diagram of a system 300 for simulation testing provided by the embodiment of the present application.

As shown in fig. 3, the system 300 includes: stimulus generator 310, scheduler 320, generic bus model 330. Alternatively, the system 300 may be the simulation test system 10 in the architecture shown in FIG. 1, the stimulus generator 310 may be the stimulus generator 11 in the architecture shown in FIG. 1, the scheduler 320 may be the scheduler 12 in the architecture shown in FIG. 1, and the generic bus model 330 may be the GBM in the architecture shown in FIG. 1. Wherein the generic bus model 330 is implemented in hardware.

In particular, the stimulus generator 310 is used to generate a stimulus file that is used to indicate the operation of the simulation test on the DUT. For example, the stimulus generator 310 can generate instruction information readable by the GBM and corresponding debug information according to the function to be tested of the DUT, wherein the instruction information indicates the operation performed by the GBM on the DUT, such as writing data or reading data, using a binary system, and the debug information interprets the operation indicated by the instruction information using a hexadecimal system. Each piece of instruction information may also be referred to as an excitation vector. A file of at least one stimulus vector is referred to as a stimulus file and is used to describe the operation of a series of simulation tests on the DUT. It should be understood that the encoding format of the instruction information is not limited to binary, and other encoding formats that can be understood by hardware devices may be used; similarly, the encoding format of the debugging information is not limited to hexadecimal, and other encoding formats which are convenient for the tester of the user to read can be used.

In particular, the scheduler 320 is used to load the stimulus file into the generic bus model. For example, scheduler 320 can assign the stimulus file generated by stimulus generator 310 to the corresponding GBM. For example, scheduler 320 may interact with a Static Random Access Memory (SRAM) of the GBM to download the stimulus file into the SRAM of the GBM. Optionally, the scheduler 320 may also upload test result information stored in the SRAM by the GBM to a server or a user device, so that a user can obtain a test result after the simulation test is finished.

Optionally, the scheduler 320 may further include the following functions according to user requirements. Optionally, the scheduler 320 can monitor critical signals in the hardware logic operation, for example, add probes to monitor the test completion signals of the GBM, and determine that the simulation test of the round is finished when all the test completion signals of the GBM are detected; for another example, a probe is added to monitor the response error signal of the GBM, so that the GBM with a problem in test can be debugged; as another example, probes are added to the DUT to monitor critical signals in the operation of the DUT for locating the cause of a problem when the test is in trouble. Optionally, the scheduler 320 can control the operation of the whole test platform, for example, initializing the DUT before the simulation test starts, resetting the clock of the DUT, and the like; for another example, the GBM is controlled to be started or closed so as to simulate a scene in which a plurality of chips to be tested work cooperatively; as another example, the clock and/or GBM of the DUT may be paused to debug the GBM that is running in problem.

Specifically, the universal bus model 330 is used for generating a stimulus signal according to a stimulus file to perform simulation test on the DUT; a response signal is received to determine the result of the simulation test. Wherein the stimulus signal is an input signal recognizable by the DUT and the response signal is an output signal transmitted by the DUT in accordance with the stimulus signal. For example, the generic bus model 330 can parse the stimulus vector to determine the operation performed on the DUT and the information required to perform the operation, e.g., a write operation requires determining a write address and write data, and a read operation requires determining a read address, and the generic bus model 330 performs signal interaction with the DUT through the corresponding channel specified by the standard protocol used by the DUT according to the parsed information.

Taking the AXI bus protocol as an example, the write operation uses three channels: the GBM sends a signal indicating an address of write data to the DUT through the write address channel, sends a signal indicating the write data to the DUT through the write data channel, and receives a response signal of a write operation sent by the DUT through the write response channel. The read operation uses two channels: the GBM sends a signal indicating an address of read data to the DUT through the read address channel, and receives a response signal of a read operation sent by the DUT and a signal of the read data through the write response channel. Optionally, the GBM may include only a channel for a write operation, or only a channel for a read operation, or may include both channels for a write operation and a read operation according to a use requirement, which is not specifically limited in this application. It should be understood that the present application only uses the AXI bus protocol as an example to illustrate the process of GBM interacting with DUT signals, and does not constitute a limitation on the specific interface of GBM, and GBM may also provide other interfaces required by other bus standard protocols as needed. Optionally, the GBM may also extend control signals outside the bus standard protocol according to the test requirements, such as a test complete signal (GBM _ test _ done) for indicating that the simulation test is complete and a response error signal (GBM _ error) for indicating that the test result is inconsistent with the expectation. The expandable control signal may be monitored in the background by the scheduler 320, or may be integrated into an interrupt circuit of the SOC, and the test state of the GBM is monitored by a Central Processing Unit (CPU) or other devices.

According to the technical scheme of the embodiment of the application, the simulation test system can achieve the processes of generating the excitation signal and receiving the response signal in a hardware environment, all simulation behaviors are completed in the hardware environment, decoupling of software and hardware in the simulation process is achieved, frequent interaction of the hardware and the software is avoided, the speed of simulation test and the simulatable logic scale are improved, and therefore the efficiency of the simulation test is improved.

The system of simulation test provided by the embodiment of the present application is described above with reference to fig. 1 to 3, and the implementation manners of the excitation generator 310 and the universal bus model 330 in the embodiment of the present application are respectively described in detail below.

Fig. 4 shows a schematic block diagram of an excitation generator 310 provided in the embodiment of the present application. The structure of the excitation generator 310 is described below with reference to fig. 4.

As shown in fig. 4, the excitation file is generated by generating instruction fields and then splicing the instruction fields into instruction information. Correspondingly, the excitation generator 310 may include: a field generating module 312 and a field splicing storage module 315.

Specifically, the field generating module 312 is configured to generate an instruction field satisfying the constraint file according to the constraint file. For example, a constraint file may constrain four attributes for each field: field type (type), field bit width (width), field constraint list (cons), and field weight list (weight). Wherein, the field type (type) is used to indicate the role of the instruction field, and taking a write operation instruction in the AXI protocol as an example, the write operation instruction may include an address field (awaddr), a data size field (awlen), a data size field (awsize), and the like; the field bit width (width) is used for indicating the number of bytes occupied by the instruction field in the instruction; a field constraint list (cons) is used for indicating the value range of the instruction field; the field weight list (weight) is used to indicate the weight of the instruction field in the instruction.

Alternatively, the manner in which field generation module 312 generates the instruction field may vary depending on the type of incentive selected by the user. For example, the stimulus types can include random address stimuli, continuous address stimuli, weighted address stimuli. The generation manner of the continuous address excitation is that the field generation module 312 determines, according to the corresponding field constraint list (cons), a starting awaddr, a fixed awlen, and a fixed awsze, thereby determining at least one excitation vector with continuous addresses; the excitation vectors for both the random address excitation and the weighted address excitation are randomly generated, i.e., field generation module 312 determines random awaddr, awlen, and awsize from the corresponding field constraint list (cons) to generate at least one excitation vector for the address randomness. The field constraint list (cons) may be a specific value, for example, determined from a random number table, or may be a range of values, for example, any value between two specified values, which is not specifically limited in the present application.

Specifically, the field splicing storage module 315 is configured to splice instruction fields to generate instruction information, and determine corresponding debugging information according to the instruction information. Still taking the write operation instruction in the AXI protocol as an example, the field splicing storage module 315 can splice the awaddr, awlen, and awsize fields generated by the field generation module 312 into a piece of instruction information that can be decoded by the GBM for instructing to write a specific amount of data having a specific size to a specific address of the DUT. Correspondingly, the field splicing storage module 315 can convert the instruction information into an encoding format that is easy for a tester of a user to read, so as to generate debugging information, which plays a role in explaining the content of the instruction information. A complete piece of instruction information may also be referred to as an excitation vector, and the excitation vector and the corresponding debug information are temporarily stored in the field splicing storage module 315 until the number of generated excitation vectors meets the requirements of an excitation file, and a stored set of excitation vectors is output as an excitation file. And storing the corresponding debugging information in user equipment or a server so as to be convenient for a tester of the user to check during debugging.

Optionally, the manner in which the plurality of excitation vectors in the excitation file are continuously generated may be different according to excitation types, including but not limited to: random address excitation, continuous address excitation, weighted address excitation. For example, after the field splicing storage module 315 generates and stores the first excitation vector, if the number of the stored excitation vectors is less than the number of excitation vectors required by the excitation file, the field splicing storage module continues to generate the second excitation vector, and for the random address excitation, the instruction field of the second excitation vector is randomly determined from the field constraint list (cons) that is the same as the first excitation vector; for consecutive address stimuli, the awaddr of the second stimulus is consecutive to the address at which the first stimulus was terminated, and the same fixed awlen and awsize are used as for the first stimulus; for weighted address excitation, a group of excitation vectors is further divided into a plurality of subgroups according to weights, the excitation vectors of the same subgroup are randomly determined according to the same field constraint list (cons), and the excitation vectors of different subgroups are randomly determined according to different field constraint lists (cons). For example, the number of excitation vectors expected by the weighted address excitation file is N (N is a positive integer greater than 1), where the first subset of N1 vectors, the second subset of N2 excitation vectors, and the third subset of N3 excitation vectors (N1, N2, and N3 are positive integers, and N1+ N2+ N3= N) may give 6 values a1 to a6 in the corresponding field constraint list (cons), then the instruction field of the excitation vector in the first subset may take a random value in a range from a1 to a2, the instruction field of the excitation vector in the second subset may take a random value in a range from a3 to a4, and the instruction field of the excitation vector in the third subset may take a random value in a range from a5 to a 6.

From the above example, it can be seen that the weighted address stimulus file enables the generation of random instruction fields of different ranges for stimulus vectors of different subgroups in the same stimulus file, but since the stimulus vectors are generated sequentially, the stimulus vectors of the same subgroup are adjacent. In order to make the excitation file more realistic, the order of the excitation vectors in the weighted address excitation file may also be scrambled.

In this case, optionally, the excitation generator 310 may further include an out-of-order processing module 314, configured to, when the excitation type is address weighting, perform out-of-order processing on the excitation vectors generated by the field splicing storage module 315, thereby rearranging the order of the excitation vectors in the excitation file.

Since each instruction field is generated independently, the instruction field generated by the field generation module 312, although able to satisfy the constraint file, may be spliced to be out of compliance with the standard protocol used by the DUT, and thus the instruction field may optionally be preprocessed after being generated. The preprocessing may include address preprocessing and/or preprocessing across 4K boundaries.

In this case, optionally, the stimulus generator 310 may further include a pre-processing module 313 for pre-processing the instruction field to meet the standard protocol used by the DUT. Optionally, the pre-processing module 313 includes an address pre-processing module 313 and/or a cross 4K boundary pre-processing module 313. For example, taking AXI as an example, when an AXI bus performs narrowband transmission, a low bit of an address field is assigned with a value of 0, for example, when a data bus has a bit width of 128 bits, and the size is configured to be 3, the last mantissa of the address field can only be 0, 4, 8, and c, so that if the DUT performs narrowband transmission, the address field generated by the field generation module 312 can be preprocessed. For another example, the address of the AXI bus is generally not allowed to cross a 4K boundary, and although the start address generated by field generation module 312 can satisfy the requirement, if the data amount (len) field generated randomly is too large, the end address may exceed the 4K boundary, so the data amount (len) field may be preprocessed to become two shorter fields. It should be understood that the two preprocessing cases are only for illustration, and the instruction field may be preprocessed in other manners according to the requirement and the actually used bus protocol, which is not specifically limited in this application.

Since the constraint file can be input by a user according to test requirements, and the situation that the constraint file does not conform to a standard protocol used by the DUT can exist, the constraint file can be optionally subjected to self-checking on the value and the format before generating the instruction field.

In this case, optionally, the stimulus generator 310 may further include a constraint format self-test module 311 for determining whether the format of the constraint file is correct. For example, checking the expressive power that the value in the field constraint list cannot be larger than the field bit width. For another example, taking the AXI protocol as an example, the field width of the field AXI protocol of the partial type is specified, so whether the field type matches with the field width can be checked. For another example, if an address weighting type of stimulus is selected, it may also be checked whether the field constraint list provides multiple value ranges, etc.

The excitation generator 310 in the system provided by the embodiment of the present application is described above with reference to fig. 4, and the structure of the universal bus model 330 is described below with reference to fig. 5.

Fig. 5 shows a schematic structure diagram of a general bus model provided in an embodiment of the present application. As described above, the GBM may handle write operations or read operations separately, depending on the requirements of the emulation test. Therefore, it should be understood that fig. 5 only shows a case where the GBM handles both write operations and read operations, and the structure of the GBM is not limited, and the GBM provided in the embodiment of the present application may only include a part of the modules related to write operations in fig. 5, may only include a part of the modules related to read operations in fig. 5, or may include all the modules in fig. 5. The GBM components provided in the present application will be described separately with respect to write operations and read operations.

As shown in fig. 5, to simulate a write operation to a DUT, the generic bus model 330 may include: a write channel decode module 3311, a write address control module 3312, a write data control module 3313, a write response recording module 3314, a write stimulus storage module 3315.

In particular, the write stimulus storage module 3315 is configured to receive a stimulus file loaded into the GBM by the scheduler and to store a write stimulus vector in the stimulus file. The stimulus vector in the stimulus file that indicates a write operation to the DUT is referred to herein as a write stimulus vector.

Alternatively, when the trigger timing of the write stimulus vector needs to be scheduled, for example, when there are multiple write stimulus vectors in the stimulus file that need to be executed in sequence, or when the write stimulus vectors need to be triggered at a specific time, etc., the GBM may also store the stimulus vectors first, and trigger the corresponding stimulus vectors when the conditions are met. The write stimulus storage module 3315 in this case may also be used to send the write stimulus vector to the write channel decode module 3311 when the trigger condition for the write stimulus vector is met. For example, the write stimulus storage module 3315 may be capable of storing write stimulus vectors in a stimulus file while monitoring the operational state of the system and determining to send the write vectors to the write channel decode module 3311 based on the downstream state of the system. Taking the AXI bus protocol as an example, a count (num) field may be included in the write stimulus vector, which is invoked when the counter of the write address channel matches the num field of the write stimulus vector. The write stimulus storage module 3315 may also select other trigger conditions according to the simulation test requirements, which is not specifically limited in this application, for example, trigger a corresponding write stimulus vector at a specific time of the DUT clock.

In particular, the write channel decode module 3311 is used to decode write stimulus vectors to determine write address channel signals and write data channel signals. The write address channel signal is used for indicating an address of data to be written to the DUT, and the write data channel signal is used for indicating the data to be written to the DUT. For example, the write channel decode module 3311 can extract the instruction fields required for a write operation from the write stimulus vector to determine the address and data to write to the DUT, according to the bus standard protocol used by the DUT.

Alternatively, the write address channel signal and the write data channel signal may be determined directly from the value of the corresponding instruction field, or may be determined from the value profile of the other instruction field. For example, the write stimulus vector may include an address field for indicating an address for writing data to the DUT and a data field for indicating data for writing to the DUT, thereby increasing decoding speed. For another example, the write stimulus vector may not include a data field, and the data written to the DUT may be determined according to a mapping relationship between an identification code (id) field in the write stimulus vector and data pre-stored in the GBM, or may be obtained by encoding/decoding according to an address field in the write stimulus vector, thereby simplifying the content of the stimulus vector.

In particular, the write address control module 3312 is used to send write address channel signals to the DUT. For example, taking the DUT using the AXI bus protocol as an example, the write address control module 3312 can send signals to the DUT via a write address channel, controlling the timing and level of the write address channel signals according to the write address determined by the write channel decoding module 3311, thereby indicating the address at which the DUT writes data.

In particular, the write data control module 3313 is used to send write data channel signals to the DUT. For example, taking the example of a DUT using the AXI bus protocol, the write data control module 3313 can send signals to the DUT over a write data channel. While the write address channel is sending write address signals to the DUT, the write data control module 3313 can control the timing and level of the write data channel signals to indicate the data being written by the DUT based on the write data determined by the write channel decode module 3311.

Specifically, the write response recording module 3314 is used to receive write response channel signals sent by the DUT. For example, taking the example that the DUT uses the AXI bus protocol, the write response recording module 3314 can receive a response signal returned by the DUT through a write response channel, where the write response signal indicates whether the write operation was successful.

According to the technical scheme of the embodiment of the application, the GBM can analyze the write excitation vector in a hardware environment and perform signal interaction with the DUT by using a hardware interface provided by a standard protocol, so that the hardware realizes the simulation test of write operation and verifies the correctness of the write operation of the DUT.

The modules required for the simulation of write operations to the DUT are described above, and the modules associated with the simulation of read operations are described below. As shown in fig. 5, simulating a read operation of a DUT, the universal bus model 330 may include: a read channel decoding module 3321, a read address control module 3322, a read response recording module 3323, and a read stimulus storage module 3324.

Specifically, the read stimulus storage module 3324 is configured to receive a stimulus file loaded to the GBM by the scheduler, and store a read stimulus vector in the stimulus file. The stimulus vector in the stimulus file that indicates a read operation to the DUT is referred to herein as a read stimulus vector.

Optionally, the read stimulus storage module 3324 may be further configured to send the read stimulus vector to the read channel decoding module 3321 when a trigger condition of the read stimulus vector is satisfied. Optionally, the implementation manner of the read channel decoding module 3321 may be similar to that of the write channel decoding module 3311, and reference may be made to the above description of the write channel decoding module 3311, which is not described herein again.

In particular, the read channel decode module 3321 is configured to decode the read excitation vector to determine a read address channel signal. Wherein the read address channel signal is used to indicate an address for reading data from the DUT. For example, the read channel decode module 3321 can extract the instruction fields needed for a read operation from the read stimulus vector to determine the address to read data from the DUT according to the bus standard protocol used by the DUT. Optionally, the implementation manner of the read channel decoding module 3321 may be similar to that of the write channel decoding module 3311, and reference may be made to the above description of the write channel decoding module 3311, which is not described herein again.

In particular, the read address control module 3322 is used to send read address channel signals to the DUT. For example, taking the example that the DUT uses the AXI bus protocol, the read address control module 3322 can send signals to the DUT through a read address channel, and control the timing and level of the read address channel signals according to the read address determined by the read channel decoding module 3321, so as to instruct the DUT of the address at which to read data.

Specifically, the read response recording module 3323 is configured to receive a read response channel signal transmitted by the DUT. For example, taking the DUT using the AXI bus protocol as an example, the read response recording module 3323 can receive a response signal returned by the DUT through a read response channel, where the read response signal can indicate whether the read operation is successful. Optionally, the read response recording module 3323 may also be configured to receive read data sent by the DUT through the read response channel, so that the GBM can be further configured to verify the correctness of the read/write data in addition to verifying the correctness of the read/write operation of the DUT.

According to the technical scheme of the embodiment of the application, the GBM can analyze the read excitation vector in a hardware environment and perform signal interaction with the DUT by using a hardware interface provided by a standard protocol, so that the hardware realizes simulation test of read operation and verifies the correctness of the read operation of the DUT.

The above describes the relevant modules required by the GBM for read-write operation emulation. In some possible cases, it is also necessary to determine the test result information of the stimulus file according to the response result of each read/write stimulus vector in the stimulus file.

In this case, optionally, the universal bus model 330 may further include a process monitoring module for determining test result information according to the response signal; and sending the test result information to the scheduler. The test result information may include, but is not limited to, at least one of: successful read/write operands, failed read/write operands, information about failed read/write operations, response speed of read/write operations, and the like. For example, the process monitoring module can count the number of completed read/write operands, and also count the number of successful read/write operands that are consistent with the expectation and the number of failed read/write operands that are inconsistent with the expectation, according to the operation result reflected by the received response signal sent by the DUT. Further, for failed read/write operations, the process monitor module may also record relevant information (e.g., read/write addresses) in the corresponding stimulus vector, thereby facilitating determination of the cause of the response error. Optionally, the process monitoring module may further analyze the response signal, for example, determine a delay of the read/write operation according to a time when the read/write address channel sends the signal and a time interval when the read/write response channel receives the signal, and further determine an average delay of the read/write operation according to the delay of each read/write operation, so as to analyze a response speed of the read/write operation.

Optionally, the process monitoring module may also be capable of generating a test complete signal and/or a response error signal to enable the scheduler 320 to monitor the test status of the GBM. For example, the process monitoring module may generate a test complete signal when execution of all of the excitation vectors in the excitation file is complete. As another example, the process monitoring module may generate a response error signal when the received response signal does not correspond to the expected response.

The system embodiment of the simulation test provided in the present application is described above with reference to fig. 1 to fig. 5, and the method embodiment of the simulation test provided in the present application is described below with reference to fig. 6. It is to be understood that the method embodiments correspond to the system embodiments and similar descriptions may be made with reference to the system embodiments.

Fig. 6 shows a schematic flowchart of a method for simulation testing according to an embodiment of the present application. Alternatively, the method of fig. 6 may be performed by the system 300 of fig. 3.

As shown in fig. 6, the method includes the following steps.

S610: the stimulus generator generates a stimulus file.

In particular, the stimulus generator is used to generate a stimulus file that is used to indicate the operation of the simulation test on the DUT. Alternatively, step S610 may be performed by the stimulus generator 310 in the system shown in fig. 3.

S620: the scheduler loads the stimulus file into the generic bus model.

In particular, the scheduler can assign the stimulus file generated by the stimulus generator to the corresponding GBM. Alternatively, step S620 may be performed by the scheduler 320 in the system shown in fig. 3.

S630: and the universal bus model generates an excitation signal according to the excitation file and sends the excitation signal to the design to be tested for simulation test.

S640: the universal bus model receives the response signal and determines the result of the simulation test according to the response signal.

Specifically, the universal bus model generates an excitation signal according to an excitation file so as to perform simulation test on the DUT; the response signal is received to determine the result of the simulation test. Wherein the stimulus signal is an input signal recognizable by the DUT and the response signal is an output signal transmitted by the DUT in accordance with the stimulus signal. Alternatively, steps S630 and S640 may be performed by the universal bus model 330 in the system shown in fig. 3.

According to the technical scheme of the embodiment of the application, the process of generating the excitation signal and receiving the response signal is realized in the hardware environment, all simulation behaviors are completed in the hardware environment, decoupling of software and hardware in the simulation process is realized, frequent interaction of the hardware and the software is avoided, the speed of simulation test and the simulatable logic scale are improved, and therefore the efficiency of the simulation test is improved.

For the step S610, optionally, the stimulus generator generates a stimulus file, including: generating an instruction field meeting the constraint file according to the constraint file through a field generating module, wherein the constraint file is used for indicating the value range of the instruction field; and generating instruction information by the splicing storage module according to the splicing instruction field, wherein the instruction information is used for indicating the operation of the universal bus model on the design to be tested.

Optionally, the excitation generator generates an excitation file, further comprising: and determining debugging information according to the instruction information by the splicing storage module, wherein the debugging information is used for explaining the content of the instruction information.

Optionally, the excitation generator generates an excitation file, further comprising: the instruction field is preprocessed by the preprocessing module to meet the standard protocol used by the universal bus model.

Optionally, the excitation generator generates an excitation file, further comprising: and determining whether the format of the constraint file is correct or not through a constraint format self-checking module.

As for the above steps S630 to S640, optionally, the method includes: decoding the write excitation vector through a write channel decoding module to generate a write address channel signal and a write data channel signal, wherein the write address channel signal is used for indicating an address for writing data into the design to be tested, and the write data channel signal is used for indicating the data written into the design to be tested; sending a write address channel signal to the design to be tested through a write address control module; sending a write data channel signal to the design to be tested through the write data control module; receiving, by a write response recording module, a write response channel signal, the write response channel signal for indicating whether the write operation was successful.

Optionally, the foregoing steps further include: storing, by a write stimulus storage module, a write stimulus vector; and when the trigger condition of the write excitation vector is met, sending the write excitation vector to a write channel decoding module.

Optionally, the foregoing steps further include: decoding the read excitation vector through a read channel decoding module to determine a read address channel signal, wherein the read address channel signal is used for indicating an address for reading data from the design to be tested; sending a read address channel signal to the design to be tested through a read address control module; a read response channel signal is received by the read response recording module, the read response channel signal indicating whether the read operation was successful.

Optionally, the foregoing steps further include: storing, by a read stimulus storage module, a read stimulus vector; and when the trigger condition of the read excitation vector is met, sending the read excitation vector to a read channel decoding module.

Optionally, the foregoing steps further include: determining test result information according to the response signal through a process monitoring module, wherein the test result information is used for indicating the result of the simulation test; and sending the test result information to the scheduler.

Optionally, the method further includes: and the dispatcher receives the test result information and uploads the test result information to the server.

Optionally, the method further includes: the scheduler monitors the running state of the design to be tested so that a user can debug the design to be tested according to the running state.

Optionally, the method further includes: and the scheduler sends a control signal to the universal bus model, and the control signal is used for controlling the universal bus model to be started or closed.

Optionally, the method further includes: and the scheduler sends an initialization signal to the design to be tested, and the initialization signal is used for restoring the design to be tested to the state before the simulation test.

The present application also provides a system 100 for simulation testing. As shown in fig. 7, the system 100 includes: a bus 102, a processor 104, a memory 106, a communication interface 108, and a hardware emulation device 110. The processor 104, the memory 106, and the communication interface 108 communicate with each other via the bus 102, and the hardware emulation device 110 communicates with other components of the system via the communication interface 108. It should be understood that the present application does not limit the number of processors, memories in the system 100.

The bus 102 may be a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, or the like. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one line is shown in FIG. 3, but that does not indicate only one bus or type of bus. Bus 102 may include a path that transfers information between various components of system 100 (e.g., memory 106, processor 104, communication interface 108).

The processor 104 may include any one or more of a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a Micro Processor (MP), or a Digital Signal Processor (DSP).

The memory 106 may include volatile memory (volatile memory), such as Random Access Memory (RAM). The processor 104 may also include non-volatile memory (non-volatile memory), such as read-only memory (ROM), flash memory, a Hard Disk Drive (HDD), or a Solid State Drive (SSD).

The memory 106 stores executable program code, and the processor 104 executes the executable program code to implement the functions of the excitation generator, the scheduler, the general bus model or each module in the system, respectively, so as to implement the above simulation test method. That is, the memory 106 has stored thereon instructions for performing the above-described method of simulation testing.

The communication interface 108 enables communication between the system 100 and other devices or communication networks using transceiver modules such as, but not limited to, network interface cards, transceivers, and the like.

The hardware simulation apparatus 110 uses a hardware simulator (emulator) based on, for example, but not limited to, a processor-based (CPU-based) or a field programmable gate array (FPGA-based) to perform the steps that need to be performed on the hardware side in the above simulation test method.

The embodiment of the present application further provides a chip, where the chip includes a processor and a data interface, and the processor reads an instruction stored in a memory through the data interface to execute the method for simulation test.

Embodiments of the present application further provide a computer program product containing instructions. The computer program product may be a software or program product containing instructions capable of being run on a computing device or stored in any available medium. The computer program product, when run on at least one computing device, causes the at least one computing device to perform the method of simulation testing described above.

The embodiment of the application also provides a computer readable storage medium. The computer-readable storage medium can be any available medium that a computing device can store or a data storage device, such as a data center, that contains one or more available media. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid state disk), among others. The computer-readable storage medium includes instructions that direct a computing device to perform the method of simulation testing described above.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A system for simulation testing, the system comprising a stimulus generator and a scheduler implemented on a software side and a generic bus model implemented on a hardware side, wherein,

the excitation generator is used for generating an excitation file, and the excitation file is used for indicating the operation of carrying out simulation test on the design to be tested;

the scheduler is used for loading the excitation file to the universal bus model;

the universal bus model is used for generating an excitation signal according to the excitation file and sending the excitation signal to the design to be tested for simulation test;

the universal bus model is further configured to receive a response signal, and determine a result of the simulation test according to the response signal, where the response signal is an output signal sent by the design to be tested according to the excitation signal.

2. The system of claim 1, wherein the stimulus file includes a write stimulus vector for indicating a write operation to the design under test, the stimulus signals include write address channel signals and write data channel signals, the response signals include write response channel signals,

the universal bus model comprises:

a write stimulus storage module for storing the write stimulus vector;

a write channel decoding module, configured to decode the write excitation vector to generate the write address channel signal and the write data channel signal, where the write address channel signal is used to indicate an address for writing data to the design to be tested, and the write data channel signal is used to indicate data written to the design to be tested;

the write address control module is used for sending the write address channel signal to the design to be tested;

the data writing control module is used for sending the data writing channel signal to the design to be tested;

and the write response recording module is used for receiving the write response channel signal, and the write response channel signal is used for indicating whether the write operation is successful or not.

3. The system of claim 2, wherein the write stimulus storage module is further configured to:

and when the trigger condition of the write excitation vector is met, sending the write excitation vector to the write channel decoding module.

4. The system of any of claims 1-3, wherein the stimulus file includes a read stimulus vector for indicating a read operation on the design under test, the stimulus signals include read address channel signals, the response signals include read response channel signals,

the universal bus model comprises:

a read excitation storage module for storing the read excitation vector;

a read channel decoding module, configured to decode the read excitation vector to generate the read address channel signal, where the read address channel signal is used to indicate an address for reading data from the design to be tested;

the read address control module is used for sending the read address channel signal to the design to be tested;

and the read response recording module is used for receiving the read response channel signal, and the read response channel signal is used for indicating whether the read operation is successful or not.

5. The system of claim 4, wherein the read stimulus storage module is further configured to:

and when the trigger condition of the read excitation vector is met, sending the read excitation vector to the read channel decoding module.

6. The system of any one of claims 1 to 3, wherein the generic bus model further comprises a process monitoring module configured to:

determining test result information according to the response signal, wherein the test result information is used for indicating the result of the simulation test;

and sending the test result information to the scheduler.

7. The system of claim 6, wherein the scheduler is further configured to:

and receiving the test result information, and uploading the test result information to a server.

8. The system of any of claims 1-3, wherein the scheduler is further configured to:

and monitoring the running state of the design to be tested so that a user can debug the design to be tested according to the running state.

9. The system of any of claims 1 to 3, wherein the scheduler is further configured to:

and sending a control signal to the universal bus model, wherein the control signal is used for controlling the universal bus model to be started or closed.

10. The system of any of claims 1-3, wherein the scheduler is further configured to:

and sending an initialization signal to the design to be tested, wherein the initialization signal is used for restoring the design to be tested to a state before simulation test.

11. The system of any one of claims 1 to 3, wherein the excitation generator comprises:

the field generating module is used for generating an instruction field meeting the constraint file according to the constraint file, wherein the constraint file is used for indicating the value range of the instruction field;

and the field splicing storage module is used for splicing the instruction field to generate instruction information, and the instruction information is used for indicating the operation of the universal bus model on the design to be tested.

12. The system of claim 11, wherein the field stitching module is further configured to:

and determining debugging information according to the instruction information, wherein the debugging information is used for explaining the content of the instruction information.

13. The system of claim 11, wherein the excitation generator further comprises:

and the preprocessing module is used for preprocessing the instruction field so as to enable the instruction field to meet the standard protocol used by the universal bus model.

14. The system of claim 11, wherein the excitation generator further comprises:

and the constraint format self-checking module is used for determining whether the format of the constraint file is correct or not.

15. The system of any one of claims 1 to 3, wherein the stimulus file generated by the stimulus generator comprises at least one of: random address excitation, continuous address excitation, weighted address excitation.

16. The system of any one of claims 1 to 3, wherein the generic bus model is written in synthesizable code.

17. A method of simulation testing, the method being performed by a system of simulation testing, the system comprising a stimulus generator and scheduler implemented on a software side and a generic bus model implemented on a hardware side, the method comprising:

the excitation generator generates an excitation file, and the excitation file is used for indicating the operation of carrying out simulation test on the design to be tested;

the scheduler loads the stimulus file to the generic bus model;

the universal bus model generates an excitation signal according to the excitation file and sends the excitation signal to the design to be tested to perform simulation test;

and the universal bus model receives a response signal and determines the result of the simulation test according to the response signal, wherein the response signal is an output signal sent by the design to be tested according to the excitation signal.

18. The method of claim 17, wherein the stimulus file includes a write stimulus vector that indicates a write operation to the design under test, wherein the stimulus signals include write address channel signals and write data channel signals, wherein the response signals include write response channel signals,

the general bus model generates an excitation signal according to the excitation file and sends the excitation signal to the design to be tested for simulation test, and the method comprises the following steps:

storing, by a write stimulus storage module, the write stimulus vector;

decoding, by a write channel decoding module, the write excitation vector to generate the write address channel signal and the write data channel signal, where the write address channel signal is used to indicate an address for writing data to the design to be tested, and the write data channel signal is used to indicate data for writing to the design to be tested;

sending the write address channel signal to the design to be tested through a write address control module;

sending the write data channel signal to the design to be tested through a write data control module;

the general bus model receives a response signal and determines the result of the simulation test according to the response signal, and the method comprises the following steps:

and receiving the write response channel signal through a write response recording module, wherein the write response channel signal is used for indicating whether the write operation is successful or not.

19. The method of claim 18, wherein the generic bus model generates excitation signals from the excitation files and sends the excitation signals to the design under test for simulation testing, further comprising:

and sending the write excitation vector to a write channel decoding module through a write excitation storage module when the trigger condition of the write excitation vector is met.

20. The method of any of claims 17 to 19, wherein the stimulus file includes a read stimulus vector for indicating a read operation on the design under test, wherein the stimulus signals include read address channel signals, and wherein the response signals include read response channel signals,

storing, by a read stimulus storage module, the read stimulus vector;

decoding, by a read channel decoding module, the read excitation vector to generate the read address channel signal, wherein the read address channel signal is used to indicate an address at which data is read from the design to be tested;

sending the read address channel signal to the design to be tested through a read address control module;

and receiving the read response channel signal through a read response recording module, wherein the read response channel signal is used for indicating whether the read operation is successful or not.

21. The method of claim 20, wherein the generic bus model generates excitation signals from the excitation files and sends the excitation signals to the design under test for simulation testing, further comprising:

and sending the read excitation vector to the read channel decoding module through a read excitation storage module when the trigger condition of the read excitation vector is met.

22. The method of any of claims 17 to 19, wherein the generic bus model receives a response signal and determines the result of the simulation test based on the response signal, further comprising:

determining test result information according to the response signal through a process monitoring module, wherein the test result information is used for indicating the result of the simulation test;

and sending the test result information to the scheduler.

23. The method of claim 22, further comprising:

and the dispatcher receives the test result information and uploads the test result information to a server.

24. The method according to any one of claims 17 to 19, further comprising:

and the scheduler monitors the running state of the design to be tested so that a user can debug the design to be tested according to the running state.

25. The method according to any one of claims 17 to 19, further comprising:

and the scheduler sends a control signal to the universal bus model, and the control signal is used for controlling the universal bus model to be started or closed.

26. The method according to any one of claims 17 to 19, further comprising:

and the scheduler sends an initialization signal to the design to be tested, wherein the initialization signal is used for restoring the design to be tested to a state before simulation testing.

27. The method of any one of claims 17 to 19, wherein the stimulus generator generates a stimulus file comprising:

generating an instruction field meeting a constraint file according to the constraint file through a field generation module, wherein the constraint file is used for indicating a value range of the instruction field;

and generating instruction information by a splicing storage module according to the spliced instruction field, wherein the instruction information is used for indicating the operation of the universal bus model on the design to be tested.

28. The method of claim 27, wherein the stimulus generator generates a stimulus file, further comprising:

and determining debugging information according to the instruction information by a splicing storage module, wherein the debugging information is used for explaining the content of the instruction information.

29. The method of claim 27, wherein the stimulus generator generates a stimulus file, further comprising:

and preprocessing the instruction field by a preprocessing module so as to enable the instruction field to meet the standard protocol used by the universal bus model.

30. The method of claim 27, wherein the stimulus generator generates a stimulus file, further comprising:

and determining whether the format of the constraint file is correct or not through a constraint format self-checking module.

31. The method of any of claims 17 to 19, wherein the stimulus file generated by the stimulus generator comprises at least one of: random address excitation, continuous address excitation, weighted address excitation.

32. The method of any one of claims 17 to 19, wherein the generic bus model is written in synthesizable code.

33. A system for simulation testing, comprising: a processor and a memory for storing a computer program, the processor for invoking and executing the computer program stored in the memory to perform the method of any of claims 17-32.

34. A computer-readable storage medium for storing a computer program which causes a computer to perform the method of any one of claims 17 to 32.