CN117172205A

CN117172205A - Performance analysis method, device, electronic equipment and storage medium

Info

Publication number: CN117172205A
Application number: CN202311448814.7A
Authority: CN
Inventors: 请求不公布姓名
Original assignee: Moore Threads Technology Co Ltd
Current assignee: Moore Threads Technology Co Ltd
Priority date: 2023-11-02
Filing date: 2023-11-02
Publication date: 2023-12-05
Anticipated expiration: 2043-11-02
Also published as: CN117172205B

Abstract

The disclosure relates to the technical field of integrated circuits, and provides a performance analysis method, a performance analysis device, electronic equipment and a storage medium. The method comprises the following steps: in the first stage, a first interface excitation track file is generated according to configuration information input by a user, and a replay is arranged on a port for verifying that the IP is connected with a bus; inputting the first interface excitation track file into a player, and the player transmitting a read command and a write command to the port according to the first interface excitation track file and receiving a read response and a write response from the port; and a sampler is arranged on the port and is used for sampling data transmitted through the port and analyzing and obtaining the performance data of the bus interconnection of the system on chip according to the sampling result. According to the method and the device, the performance analysis of the system-on-chip bus interconnection can be realized in the first stage, so that the adjustment of the system-on-chip bus interconnection can be performed earlier, more time allowance is provided for optimizing the bus interconnection to obtain higher performance, and the performance of the finally determined bus interconnection mode is better.

Description

Performance analysis method, device, electronic equipment and storage medium

Technical Field

The disclosure relates to the technical field of integrated circuits, and in particular relates to a performance analysis method, a performance analysis device, electronic equipment and a storage medium.

Background

In the design process of a large-scale chip, the performance analysis of the chip is one of the indispensable links. There are two conventional analytical methods: firstly, starting re-verification (Co-verification) of the verification IP related to the real working scene of the chip in the verification environment of software, confirming whether the started verification IP can work normally or not, inserting a plurality of samplers, sampling data generated in the working process of the chip, and analyzing to obtain the performance data of the chip. Secondly, starting re-verification (Co-verification) of the verification IP related to the real working scene of the chip on a verification platform of hardware, confirming whether the started verification IP can work normally or not, and confirming whether the performance of the chip is abnormal or not through whether the service can work normally or not.

The two methods have high demands on the development quality and progress of the chip because the re-verification (Co-verification) must be performed when the chip is developed to a relatively complete state. The development of chips can be roughly divided into two phases: the first stage represents the early development stage of the chip, and the functions and structures of many modules of the chip are not yet determined; the second stage is the middle and later stages of chip development, and all the modules and functions and structures of the chip have been determined. That is, the prior art cannot analyze the performance of the chip in the first stage, and the performance analysis of the chip and the adjustment of the system-on-chip bus interconnect based on the performance data must be achieved until the second stage. This results in less time margin for optimizing the bus interconnect to achieve higher performance, and the performance of the final bus interconnect is still improved.

Disclosure of Invention

In view of this, the disclosure provides a performance analysis method, a device, an electronic apparatus, and a storage medium, where the performance analysis method according to the embodiments of the disclosure may implement performance analysis of system-on-chip bus interconnection in a first stage, so that adjustment of system-on-chip bus interconnection may be performed earlier, providing more time margin for obtaining higher performance by optimizing bus interconnection, and the performance of a finally determined bus interconnection mode is better.

According to an aspect of the present disclosure, there is provided a performance analysis method for analyzing performance of bus interconnection of a system on chip including a master, a slave, and a bus, the master and the slave being respectively provided with a verification IP, the method comprising: in a first stage, generating a first interface excitation track file according to configuration information input by a user, wherein the format of the first interface excitation track file is the same as a predefined format of the user; setting a replay on a port to which the authentication IP is connected to the bus; inputting the first interface excitation trace file into the player, the player sending read commands and write commands to the port according to the first interface excitation trace file and receiving read responses and write responses from the port; and setting a sampler on the port, wherein the sampler is used for sampling data transmitted through the port, analyzing and obtaining the performance data of the bus interconnection of the system on chip according to a sampling result, and the sampled data comprises the read command, the write command, the read response and the write response.

In one possible implementation, the method further includes: determining a deviation of the performance data from a performance expected value of the current bus interconnect; and comparing the deviation with a first threshold value, and determining a performance analysis result under the current bus interconnection according to a comparison result.

In one possible implementation, the method further includes: and generating a mail comprising the performance analysis result, and automatically sending the mail to a mailbox of the user.

In one possible implementation, the method further includes: after the bus interconnect changes, the steps of inputting the first interface excitation trace file to the player and thereafter are automatically performed every predetermined time period.

In one possible implementation, the method further includes: in a second stage, a second interface excitation track file of the system on chip in a real application scene is obtained; inputting the second interface excitation trace file to the player, the player sending read commands and write commands to the port according to the second interface excitation trace file and receiving read responses and write responses from the port; and performing the steps of sampling the data transmitted through the port and thereafter.

In one possible implementation, the method further includes: in a second stage, a second interface excitation track file of the system on chip in a real application scene is obtained; inputting the first interface excitation track file and the second interface excitation track file into the player, wherein the player sends a read command and a write command to the port according to the first interface excitation track file and the second interface excitation track file, and receives a read response and a write response from the port; and performing the steps of sampling the data transmitted through the port and thereafter.

In one possible implementation manner, the first interface excitation trace file includes a plurality of lines of data, each line of data is used for generating a command, and each line of data includes one or more of a port number, a read/write identifier, a valid time, a handshake time, a read/write number, a transmission start address, a transmission length, a transmission bit width, a transmission type, a transmission lock signal, a transmission priority, transmission buffer information, transmission protection information, and transmission user information; wherein the data comprising the read identity is used for generating a read command and the data comprising the write identity is used for generating a write command.

In one possible implementation, the player sends read commands and write commands to the port according to the first interface excitation trace file, and receives read responses and write responses from the port, including: processing according to the first interface excitation track file to obtain a write command queue and a read command queue; sequentially sending the write commands stored in the write command queue through a port where the replay device is located; sequentially sending the read commands stored in the read command queue through the port where the replay device is located; a write response corresponding to each write command stored in the write command queue and a read response corresponding to each read command stored in the read command queue are received.

In one possible implementation manner, the read command further includes a read command valid signal and a read command handshake signal, the write command further includes a write command valid signal and a write command handshake signal, the performance data includes a write command transmission delay, a read command transmission delay, a write response transmission delay, a first read response transmission delay, a second read response transmission delay, and a bandwidth, the sampling the data transmitted through the port, and analyzing according to a sampling result to obtain the performance data of the bus interconnection of the system on chip, including: sampling the write command valid signal and the write command handshake signal, and obtaining the write command transmission delay according to the interval of the sampling time of the write command valid signal and the sampling time of the write command handshake signal; sampling the read command valid signal and the read command handshake signal, and obtaining the read command transmission delay according to the sampling time of the read command valid signal and the interval of the sampling time of the read command handshake signal; sampling the write command and the write response corresponding to the write command, and obtaining the write response transmission delay according to the interval between the sampling time of the write response and the sampling time of the write command; and sampling the read command and a plurality of read responses corresponding to the read command, obtaining the first read response transmission delay according to the interval between the sampling time of the read response sampled earliest and the sampling time of the read command, obtaining the second read response transmission delay according to the interval between the sampling time of the read response sampled latest and the sampling time of the read command, and obtaining the bandwidth according to the ratio of the byte number of the read response sampled and the number of the read commands sampled.

According to another aspect of the present disclosure, there is provided a performance analysis apparatus for analyzing performance of bus interconnection of a system on chip including a master, a slave, and a bus, the master and the slave being respectively provided with an authentication IP, the apparatus comprising: the first generation module is used for generating a first interface excitation track file according to configuration information input by a user in a first stage, wherein the format of the first interface excitation track file is the same as a predefined format of the user; a first setting module for setting a player on a port to which the authentication IP is connected to the bus; a first input module for inputting the first interface excitation trace file to the player, the player sending read commands and write commands to the port according to the first interface excitation trace file and receiving read responses and write responses from the port; the second setting module is used for setting a sampler on the port, wherein the sampler is used for sampling data transmitted through the port and analyzing and obtaining the bus interconnection performance data of the system on chip according to a sampling result, and the sampled data comprises the read command, the write command, the read response and the write response.

In one possible implementation, the apparatus further includes: the first determining module is used for determining deviation between the performance data and the performance expected value of the current bus interconnection; and the first analysis module is used for comparing the deviation with a first threshold value and determining a performance analysis result under the current bus interconnection according to the comparison result.

In one possible implementation, the apparatus further includes: and the second generation module is used for generating mails comprising the performance analysis results and automatically sending the mails to the mailbox of the user.

In one possible implementation, the apparatus further includes: and the regression module is used for automatically executing the steps of inputting the first interface excitation track file into the player and the following steps every preset time period after the bus interconnection is changed.

In one possible implementation, the apparatus further includes: the first acquisition module is used for acquiring a second interface excitation track file of the system-on-chip in the real application scene in a second stage; a second input module for inputting the second interface excitation trace file to the player, the player sending read commands and write commands to the port according to the second interface excitation trace file and receiving read responses and write responses from the port; and the first driving module is used for driving the sampler to execute the steps of sampling the data transmitted through the port and the following steps.

In one possible implementation, the apparatus further includes: the second acquisition module is used for acquiring a second interface excitation track file of the system-on-chip in a real application scene in a second stage; a third input module for inputting the first interface excitation trace file and the second interface excitation trace file to the player, the player sending a read command and a write command to the port according to the first interface excitation trace file and the second interface excitation trace file, and receiving a read response and a write response from the port; and the second driving module is used for driving the sampler to execute the steps of sampling the data transmitted through the port and the following steps.

According to another aspect of the present disclosure, there is provided an electronic device including: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to implement the above-described method when executing the instructions stored by the memory.

According to another aspect of the present disclosure, there is provided a non-transitory computer readable storage medium having stored thereon computer program instructions, wherein the computer program instructions, when executed by a processor, implement the above-described method.

According to another aspect of the present disclosure, there is provided a computer program product comprising a computer readable code, or a non-transitory computer readable storage medium carrying computer readable code, which when run in a processor of an electronic device, performs the above method.

According to the performance analysis method of the embodiment of the disclosure, in a first stage, a first interface excitation track file is generated according to configuration information input by a user, a replay is arranged on a port for verifying that an IP is connected with a bus, the first interface excitation track file is input into the replay, the replay sends a read command and a write command to the port according to the first interface excitation track file, and a read response and a write response are received from the port, so that a real IP service is simulated; the port is provided with a sampler, the sampler is used for sampling a read command, a write command, a read response and a write response transmitted through the port, and analyzing and obtaining the bus interconnection performance data of the system on chip according to the sampling result, so that the bus interconnection performance of the system on chip when simulating real IP service can be obtained. According to the performance analysis method of the embodiment of the disclosure, by setting the replay and combining with the sampler, the analysis of the bus interconnection performance of the system on chip can be completed in the first stage representing the early development stage of the chip, so that the adjustment of the bus interconnection of the system on chip can be performed earlier, more time allowance is provided for optimizing the bus interconnection to obtain higher performance, and the performance of the finally determined bus interconnection mode is better.

Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments, features and aspects of the present disclosure and together with the description, serve to explain the principles of the disclosure.

Fig. 1 illustrates an exemplary application scenario of a performance analysis method according to an embodiment of the present disclosure.

Fig. 2 illustrates an exemplary application scenario of a performance analysis method according to an embodiment of the present disclosure.

Fig. 3 illustrates an exemplary structure of a global database according to an embodiment of the present disclosure.

Fig. 4 shows a schematic diagram of a flow of a performance analysis method according to an embodiment of the disclosure.

Fig. 5 illustrates an example of the content and format of a first interface stimulus trajectory file according to an embodiment of the present disclosure.

Fig. 6 shows a schematic diagram of a workflow of a player according to an embodiment of the present disclosure.

Fig. 7 shows a schematic diagram of a workflow of a sampler according to an embodiment of the present disclosure.

Fig. 8 shows a schematic diagram of the structure of a performance analysis apparatus according to an embodiment of the present disclosure.

Fig. 9 shows a block diagram of an apparatus 1900 according to an embodiment of the disclosure.

Detailed Description

Various exemplary embodiments, features and aspects of the disclosure will be described in detail below with reference to the drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. Although various aspects of the embodiments are illustrated in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

The word "exemplary" is used herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

In addition, numerous specific details are set forth in the following detailed description in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements, and circuits well known to those skilled in the art have not been described in detail in order not to obscure the present disclosure.

Fig. 1 and 2 illustrate exemplary application scenarios of a performance analysis method according to an embodiment of the present disclosure.

As shown in fig. 1, in this application scenario, the system includes a bus, and a plurality of masters (masters) and a plurality of slaves (slave) connected to the bus.

The buses may include a main bus and a sub-bus. The system may include a plurality of subsystems connected to the main bus by a sub-bus. A number of masters and/or a number of slaves may be included in each subsystem. Each of the master and slave is provided with a corresponding authentication IP (Verification Intellectual Property, VIP) to communicate with the bus via the authentication IP. The host may be a hardware device or a software module, such as a central processing unit (central processing unit, CPU), a module using a peripheral component interconnect express (peripheral component interconnect express, PCIE) protocol, a module using a universal serial bus (universal serial bus, USB) protocol, and the like. The slave may be a hardware device or a software module, such as a Double Data Rate (DDR) synchronous dynamic random access memory (SRAM), a static random-access memory (SRAM), and the like.

Each host may correspond to at least one slave, each slave having access to at least one address space of the system.

Referring to fig. 1, the system may include a master 1, a master 2, a slave 1, and a slave 2. The host 1 belongs to the subsystem 1, the host 2 belongs to the subsystem 2, the slave 1 belongs to the subsystem 3, and the slave 2 belongs to the subsystem 4. Wherein host 1 may correspond to slave 1 and host 2 may correspond to slave 2. Slave 1 may access address space 1 and address space 2, and slave 2 may access address space 3 and address space 4.

As shown in fig. 2, the user's requirement may be to verify whether the bus interconnection manner can meet that a random certain host can successfully access a certain address space, and provide the requirement to the processor in a manner of information to be verified, and store the filled file related to the system bus interconnection verification and configuration information (not shown) in the memory.

The processor may retrieve the user filled file from memory. The user may fill in a plurality of files, and the formats of the different files may not be uniform or recognized by the verification environment. In this regard, the processor may convert the retrieved file into a predefined data format such that the format of the format-converted file is uniform and recognizable by the verification environment.

The processor may then generate a connection component and a global database based on the format-converted file. The connection component comprises a port for connecting the host verification IP with the bus and a port for connecting the slave verification IP with the bus. The global database comprises a plurality of resource pools and at least one method object, and different resource pools are isolated from each other. Fig. 3 illustrates an exemplary structure of a global database according to an embodiment of the present disclosure. Referring to fig. 3, the resource pool is used to store data related to system bus interconnection verification based on file parsing after format conversion. The method object defines a method of querying a resource pool.

The processor may generate test cases and verification environments from the connection components and the global database. The test case can be executed in the first stage, and when the test case is executed, whether a random verification that a certain host can successfully access a certain address space can be met or not can be realized by the bus interconnection mode, and a comparison result of verification results of the host and the slave to be verified is output. And determining whether the bus interconnection mode of the system meets the user requirement according to the comparison result.

The processor may also perform the performance analysis method of the embodiments of the present disclosure when executing the test case, by setting a replay at a port where the verification IP is connected to the bus to send out a stimulus (including a write command, a read command, and the like described below) to the bus and receive a response (including a write response, a read response, and the like described below), sampling the stimulus and the response at the port, and analyzing the sampling time to obtain the performance data of the bus interconnection of the system on chip. Further, deviation of the performance data and the performance expected value can be monitored, a performance analysis result is determined based on the deviation, the performance analysis result is notified to a user in a mail mode, and whether the user needs to adjust bus interconnection of the system on chip is prompted.

The user may set up to regularly regress test cases. When the device returns, the replay device sends out excitation and receives response again, the sampler re-samples, performance data is obtained through re-analysis according to sampling time, and new performance analysis results are obtained through further analysis. The above regression process can be continued until the end of chip development, so that the chip obtains more excellent performance.

In one possible implementation, the disclosure proposes a performance analysis method for analyzing performance of bus interconnection of a system-on-chip, where the system-on-chip includes a master, a slave, and a bus, the master and the slave are respectively provided with a verification IP, and the structure of the system-on-chip may be referred to as an example of fig. 1.

As shown in fig. 4, the method includes:

step S41, in a first stage, generating a first interface excitation track file according to configuration information input by a user, wherein the format of the first interface excitation track file is the same as a predefined format of the user;

step S42, setting a replay device on a port for verifying that the IP is connected with the bus;

step S43, inputting the first interface excitation track file into a replay device, and sending a read command and a write command to the port according to the first interface excitation track file and receiving a read response and a write response from the port by the replay device;

In step S44, a sampler is set on the port, and the sampler is configured to sample the data transmitted through the port, and analyze, according to the sampling result, to obtain the performance data of the bus interconnection of the system on chip, where the sampled data includes a read command, a write command, a read response, and a write response.

The first stage may refer to a chip development earlier stage, and functions and structures of many modules of the chip have not been determined yet. For a system on a chip, only a simple bus interconnect and the structure of several subsystems as shown in fig. 1 may be determined. The determined subsystem may include a memory subsystem, such as a Double Data Rate (DDR) synchronous dynamic random access memory. Steps S41-S44 may all be performed in the first stage.

The user may input configuration information based on the current architecture of the system-on-chip. The configuration information mainly includes configuration modes of the authentication IP, such as a port number of an available authentication IP connection, a type of data that can be transmitted by the port, a transmission start address, a transmission length, a transmission bit width, and the like. The specific type of configuration information may be determined based on prior art and is not exemplified herein.

In step S41, in a first stage, a first interface excitation track file (trace) may be generated according to configuration information input by a user, the format of the first interface excitation track file being identical to a predefined format by the user.

As shown in fig. 5, in one possible implementation, the first interface excitation trace file includes a plurality of lines of data, each line of data being used to generate a command, each line of data including one or more of a port number, a read/write identification, a valid time, a handshake time, a read/write number, a transmission start address, a transmission length, a transmission bit width, a transmission type, a transmission lock signal, a transmission priority, transmission buffer information, transmission protection information, and transmission user information;

wherein the data comprising the read identity is used for generating a read command and the data comprising the write identity is used for generating a write command.

Wherein the port number (port id) indicates the number of the port at which the player is set. In the example of fig. 1, the data 1 includes a port number of port_1, indicating that a command for data 1 generation will be issued through port_1. The data 2 includes a port number of port_2, indicating that a command for data 2 generation will be issued through port_2.

The read/write flag indicates whether the data is used to generate a read command or a write command. Each row of data may include a read identifier or a write identifier. The data comprising the read identity is used for generating a read command and the data comprising the write identity is used for generating a write command. In the example of fig. 1, the 1 st data includes a read identifier AR, indicating that the 1 st data is used to generate a read command. The data 2 includes a write flag AW indicating that the data 2 is used to generate a write command.

The valid time (valid time) represents the point in time when the current line read/write command is valid. The read/write command is transmitted via the handshake protocol valid-ready, i.e. the valid signal shared between the sender and the receiver is set to 1 when the sender is ready to send commands. When the receiving end is ready to receive the command, the ready signal shared between the transmitting end and the receiving end is set to 1. When the valid signal and the ready signal shared between the transmitting end and the receiving end are both set to 1, the command starts to be transmitted. Thus, the point in time when the current row read/write command is valid may be the point in time when the valid signal is set to 1. In the example of fig. 1, the point in time when the read command generated from the 1 st data is valid may be t1, and the point in time when the write command generated from the 2 nd data is valid may be t2.

The handshake time (ready time) represents the time point when the current line read/write command and the downstream handshake succeed, and may be the time point when the valid signal and the ready signal are both set to 1. In the example of fig. 1, the point in time when the read command and downstream handshake generated by the 1 st data succeed may be t_1, and the point in time when the write command and downstream handshake generated by the 2 nd data succeed may be t_2.

The read/write number (arid/awid) indicates the number of the read/write command that is transmitted. In the example of fig. 1, the number of the read command generated from the 1 st data may be arid_1, and the number of the write command generated from the 2 nd data may be awid_2.

The transfer start address (araddr/awaddr) indicates the start position of the address to which the read/write command is transferred. In the example of fig. 1, the transfer start address of the read command generated from the 1 st data may be araddr_1, and the transfer start address of the write command generated from the 2 nd data may be awaddr_2.

The transfer length (arlen/awlen) represents the length of the read/write command. In the example of fig. 1, the length of the read command generated by the data 1 may be 16 and the length of the write command generated by the data 2 may be 16.

The transmission bit width (arsize/awsize) represents the bit width of the read/write command. In the example of fig. 1, the bit width of the read command generated by the 1 st data may be 40 and the bit width of the write command generated by the 2 nd data may be 32.

The transmission type (arbrust/awbrust) indicates the burst type of the read/write command. There are various burst types, such as loop-back burst (wrap), delta burst (incrementing burst, INCR), fixed length burst (fixed), etc. In the example of fig. 1, the burst type of the read command generated by the 1 st data may be an incremental burst INCR, and the burst type of the write command generated by the 2 nd data may be a loop-back burst wrap.

The transfer lock signal (arock/awlock) indicates whether the current transfer is Exclusive access (Exclusive) and lock access (Locked). Exclusive access eliminates the need for the bus to remain locked to a particular host, i.e., the bus may be used by multiple hosts simultaneously. Locking access allows a host to lock the bus for exclusive use, and only after the host completes transmission, the bus is released for other hosts. In the example of fig. 1, the transmission lock signal of the read command generated from the 1 st data indicates that Ex is exclusive access, and the transmission lock signal of the write command generated from the 2 nd data indicates that Lo is lock access.

The value of the transfer priority (arqos/awqos) indicates the transfer order of the read/write commands. A plurality of read commands and a plurality of write commands may be derived from the first interface excitation track file. The transmission order of the read/write commands may be determined by the transmission priority. In the example of fig. 1, if the smaller the value of the transmission priority is, the higher the priority is, and the smallest transmission priority 1 is 1, the transmission priority of the 1 st data generated read command is 1, indicating that the 1 st data generated read command is ordered 1 in the transmitted read commands; the transmission priority of the write command generated by the data 2 is 2, which means that the write command generated by the data 2 is ordered by the data 2 in the transmitted write command.

The transfer cache information (arcche/awcache) represents the optimization strategy employed by the read/write command. The available policies may be determined based on the prior art, and are replaced by policies a and B in fig. 1, which are not described here again.

The transfer protection information (arprot/awprot) indicates the access rights of the read/write command. The access rights may include read/write access, privileged/non-privileged access, secure/non-secure access, and the like. In the example of fig. 1, the access right r_pri_sec of the read command generated from the 1 st data indicates that the access right is a read access, a privileged access, a secure access; the access right w_n_pri_n_sec of the write command generated from the 2 nd data indicates that the access right is write access, non-privileged access, non-secure access.

The transmitted user information (aruser/awuser) represents a user-defined sideband signal. The function of this signal may be set by the user, for example, to pass additional control signals or to specify certain operating instructions. In the example of fig. 1, the control signal S1 may be used when transmitting a read command generated from the 1 st data. The control signal S2 may be used in the transmission of the write command generated from the data 2.

It should be understood by those skilled in the art that the first interface excitation track file may further include more information, and any information that the user wishes to configure may be added to the first interface excitation track file, and the specific content included in the first interface excitation track file is not limited by the embodiments of the present disclosure.

The user-predefined format may be, for example, a text format, or a tabular format, or other format that may be recognized by the verification environment, to which embodiments of the present disclosure are not limited.

In step S42, a replay (replay) is provided on the port to which the authentication IP is connected to the bus. The purpose of the replay is to send stimuli to the ports and to receive responses to the stimuli from the ports. Where the stimulus may include a read command, a write command, and the response may include a read response, a write response. In the first phase, the stimulus sent by the player may be generated by a first interface stimulus track file.

In step S43, the first interface excitation trace file may be input to the player, which transmits a read command and a write command to the port according to the first interface excitation trace file, and receives a read response and a write response from the port. Whether a read response corresponding to a read command and a write response corresponding to a write command can be received or not can indicate whether bus interconnect can satisfy access from a host to a slave to an address space. Exemplary ways of sending the command and exemplary ways of receiving the response may be found in the further description of step S43 below.

In step S44, a sampler is disposed on the port, the data transmitted through the port is sampled by using the sampler, and the performance data of the bus interconnection of the system on chip is obtained according to the analysis of the sampling result, where the sampled data includes a read command, a write command, a read response, a write response, a sampling result refers to a sampling time of the read command, the write command, the read response, the write response, and the number of the sampled read responses, and an exemplary manner of obtaining the performance data according to the analysis of the sampling result may be referred to further description of step S44 below.

As shown in fig. 6, in one possible implementation, in step S43, the player sends a read command and a write command to the port according to the first interface excitation trace file, and receives a read response and a write response from the port, including:

step S60, a write command queue and a read command queue are obtained according to the first interface excitation track file processing;

step S61, sequentially transmitting the write commands stored in the write command queue through the port where the replay device is located;

step S62, sequentially sending the read commands stored in the read command queue through the port where the replay device is located;

in step S63, a write response corresponding to each write command stored in the write command queue and a read response corresponding to each read command stored in the read command queue are received.

For example, the player may first process the trace file according to the first interface stimulus to obtain a write command queue and a read command queue. When the read/write command is obtained according to one line of data of the first interface excitation track file, the read/write command may be generated according to the read/write number, the transmission start address, the transmission length, the transmission bit width and the transmission type in the line of data. Other information included in the row is used to determine the manner in which the generated command is transmitted, for example, the ordering of the read/write command in the read/write command queue is determined according to the transmission priority in the row data, which is not illustrated here. In this way a write command queue and a read command queue can be obtained.

Thereafter, the execution of steps S61-S63 may be started simultaneously. The player may be provided with a write command counter for counting the transmitted write commands and a read command counter for counting the transmitted read commands, the write command counter being incremented each time a write command is issued and the read command counter being incremented each time a read command is issued. In step S61, the player may determine whether the write command is all sent by comparing the value recorded by the write command counter with the total number of commands in the write command queue, and in step S62, the player may determine whether the read command is all sent by comparing the value recorded by the read command counter with the total number of commands in the read command queue.

The replay may be provided with a write response counter for counting received write responses and a read response counter for counting received read responses, the write response counter being incremented for each received write response and the read response counter being incremented for each received read response. In step S63, the player may determine whether the write response is completely received by comparing the value recorded by the write response counter with the total number of responses in the write command queue, and may determine whether the read response is completely received by comparing the value recorded by the read response counter with the total number of commands in the read command queue.

In this way, the player can perform the functions of command transmission and response reception, and ensure that the transmitted command and received response are not missed.

As shown in fig. 7, in one possible implementation, the read command further includes a read command valid signal, a read command handshake signal, the write command further includes a write command valid signal, a write command handshake signal,

the performance data includes write command handshake delay, read command handshake delay, write response transfer delay, first read response transfer delay, second read response transfer delay, bandwidth,

in step S44, the data transmitted through the port is sampled, and the performance data of the bus interconnection of the system on chip is obtained according to the analysis of the sampling result, including:

step S71, sampling a write command effective signal and a write command handshake signal, and obtaining write command transmission delay according to the interval of the sampling time of the write command effective signal and the sampling time of the write command handshake signal;

step S72, sampling the reading command effective signal and the reading command handshake signal, and obtaining reading command transmission delay according to the sampling time of the reading command effective signal and the interval of the sampling time of the reading command handshake signal;

Step S73, sampling a write command and a write response corresponding to the write command, and obtaining a write response transmission delay according to the interval between the sampling time of the write response and the sampling time of the write command;

step S74, sampling the read command and a plurality of read responses corresponding to the read command, obtaining a first read response transmission delay according to the interval between the sampling time of the read response sampled earliest and the sampling time of the read command, obtaining a second read response transmission delay according to the interval between the sampling time of the read response sampled latest and the sampling time of the read command, and obtaining the bandwidth according to the ratio of the byte number of the read response obtained by sampling to the number of the read commands obtained by sampling.

Wherein steps S71-S74 may be performed simultaneously.

For example, since the transmission of commands and responses employs a valid-ready handshake protocol, read/write command valid signals, read/write command handshake signals are also used in transmitting read/write commands. These signals may be used when generating the read/write command such that the read command comprises a read command valid signal arvalid, a read command handshake signal arready, and the write command comprises a write command valid signal awvalid, a write command handshake signal awready. Likewise, the read/write response also includes a read/write response valid signal, a read/write response handshake signal. The functions of the active signals and handshake signals have been described above and are not described in detail here.

The performance data that the sampler can analyze includes several types: write command transfer delay, read command transfer delay, write response transfer delay, first read response transfer delay, second read response transfer delay, bandwidth.

Wherein, the write command transmission delay refers to the interval between the time of the write command valid signal set 1 and the time of the write command handshake signal set 1. In contrast, in step S71, the write command valid signal and the write command handshake signal may be sampled, and the write command transmission delay may be obtained according to the interval of the sampling time of the write command valid signal (refer to the time of sampling the write command valid signal to set 1) and the sampling time of the write command handshake signal (refer to the time of sampling the write command handshake signal to set 1).

Read command transfer delay refers to the interval between the time the read command valid signal is set 1 and the time the read command handshake signal is set 1. In contrast, in step S72, the read command valid signal and the read command handshake signal may be sampled, and the read command transmission delay is obtained according to the interval between the sampling time of the read command valid signal (refer to the time of sampling the read command valid signal to set 1) and the sampling time of the read command handshake signal (refer to the time of sampling the read command handshake signal to set 1).

The write response propagation delay refers to the interval between issuing a write command to receiving a write response. In contrast, in step S73, the write command and the write response corresponding to the write command may be sampled, and the write response transmission delay is obtained from the interval of the sampling time of the write response (refer to the time of sampling the write response valid signal to set 1) and the sampling time of the write command (refer to the time of sampling the write command valid signal to set 1).

Since the same read command may correspond to multiple read responses, there may be two read response transfer delays. Wherein the first read response propagation delay refers to the interval between issuing a read command and receiving a first read response corresponding to the read command. The second read response propagation delay refers to the interval from the issuance of a read command to the receipt of the last read response corresponding to the read command. In contrast, in step S74, the read command and the plurality of read responses corresponding to the read command may be sampled, the first read response transmission delay is obtained according to the interval between the sampling time of the read command and the sampling time of the read response sampled earliest, and the second read response transmission delay is obtained according to the interval between the sampling time of the read response sampled latest and the sampling time of the read command.

The bandwidth refers to the average bandwidth of the read response for each read command. In contrast, in step S74, the bandwidth may be obtained according to a ratio of the number of bytes of the sampled read response to the number of sampled read commands.

In this way, the sampler can complete the acquisition of various performance data.

In one possible implementation, the method further includes:

determining a deviation of the performance data from a performance expected value of the current bus interconnect;

and comparing the deviation with a first threshold value, and determining a performance analysis result under the current bus interconnection according to the comparison result.

For example, the first interface excitation trace file is generated according to the configuration information of the user, so that the operation mode of the player is expected after the first interface excitation trace file is input into the player, and the performance data obtained by the sampler is also expected.

In this regard, the user may pre-determine a performance expected value for the current bus interconnect and set a first threshold value indicative of a maximum allowable performance deviation. After the sampler obtains the performance data, determining the deviation between the performance data and the expected performance value of the current bus interconnection; and comparing the deviation with a first threshold value, and determining a performance analysis result under the current bus interconnection according to the comparison result. If the deviation is greater than the first threshold, the performance of the current bus interconnection is considered to be poor, and further adjustment of the bus interconnection is required. If the deviation is less than or equal to the first threshold, the deviation is deemed acceptable and the performance of the current bus interconnect meets the demand.

In this way, the comparison of the actual performance and the expected performance of the system on chip can be automatically realized, and the labor cost is reduced.

In one possible implementation, the method further includes:

and generating a mail comprising the performance analysis result, and automatically sending the mail to a mailbox of the user.

For example, the performance analysis result directly indicates whether the bus interconnection needs to be adjusted, so, in order to save the time of the bus interconnection adjustment, after the performance analysis result is obtained, the mail including the performance analysis result can be automatically generated and sent to the mailbox of the client, and in this way, the time of the bus interconnection adjustment can be saved, and the experience of the user is improved.

In one possible implementation, the method further includes:

after the bus interconnect changes, the steps of inputting the first interface excitation trace file to the player and thereafter are automatically performed every predetermined time period.

For example, as a chip is developed, the number of modules included in the chip may increase or decrease, and the functions of the modules may also change, which may result in a change in bus interconnection. Alternatively, if the deviation between the performance data of the current bus interconnect and the performance expected value is greater than the first threshold, the user may modify the bus interconnect without changing the modules and functions included in the chip. The change in bus interconnect results in a change in bus interconnect performance, where regression of test cases is required.

In this regard, it may be arranged that the steps of inputting the first interface excitation trace file to the player and thereafter are automatically performed at predetermined intervals after the bus interconnection is changed. At this time, the replay sends out command again, receives response, the sampler re-samples, re-analyzes the performance data under the new bus interconnection according to the sampling time, and further analyzes the performance data to obtain new performance analysis results.

The preset time period can be set according to the requirements of users, so that the performance of bus interconnection can be analyzed for multiple times, the accuracy of performance data and performance analysis results obtained through analysis is ensured, and the performance monitoring effect of the sampler is improved.

In one possible implementation, the method further includes:

in the second stage, a second interface excitation track file of the system on chip in a real application scene is obtained;

inputting the second interface excitation track file into a player, and the player transmitting a read command and a write command to the port according to the second interface excitation track file and receiving a read response and a write response from the port;

the steps of sampling data transmitted through the port and thereafter are performed.

For example, in the first stage, the verification IP may not have issued a real stimulus yet, and the data included in the first interface stimulus track file used in the first stage is generated according to the configuration information provided by the user, and is simulated for the commands of the possible application scenario of the chip. While in the second stage of the chip development process, it is verified that IP may have issued a realistic stimulus. At this time, the real excitation sent by each verification IP may be captured, and a second interface excitation track file may be generated based on the captured excitation, where the format of the second interface excitation track file may be the same as the format of the first interface excitation track file.

The use of the second interface excitation trajectory file in the second stage may be the same as the use of the first interface excitation trajectory file in the first stage. That is, the second interface excitation trace file is input to the player, and the player transmits a read command and a write command to the port according to the second interface excitation trace file and receives a read response and a write response from the port. The sampler has been set in the first stage and therefore does not have to be set again, the following steps being identical to the first stage, i.e. the sampling of the data transmitted through the ports and the following steps are performed.

In this way, the authenticity of the stimulus can be improved.

In one possible implementation, the method further includes:

inputting the first interface excitation track file and the second interface excitation track file into a replay, and sending a read command and a write command to the port and receiving a read response and a write response from the port by the replay according to the first interface excitation track file and the second interface excitation track file;

For example, in addition to commands (incentives) that all use the real application scenario, it is also possible to have part of the verification IP issue real commands, so that the rest of the verification IPs still issue simulated commands (incentives). In the second stage, a second interface excitation track file of the system on chip under a real application scene is still acquired, the first interface excitation track file and the second interface excitation track file are input into the replay together, the replay determines which ports are sent with real commands, which ports are sent with simulated commands, then the ports are sent with read commands and write commands according to the first interface excitation track file and the second interface excitation track file, and read responses and write responses are received from the ports. The sampler has been set in the first stage and therefore does not have to be set again, the following steps being identical to the first stage, i.e. the sampling of the data transmitted through the ports and the following steps are performed.

In this way, the real stimulus and the analog stimulus can be mixed and transmitted, and the flexibility of the command transmission mode of the replay device is improved.

The embodiment of the present disclosure also provides a performance analysis apparatus, and fig. 8 is a schematic diagram showing the structure of the performance analysis apparatus according to the embodiment of the present disclosure.

As shown in fig. 8, in one possible implementation manner, the apparatus is configured to analyze performance of bus interconnection of a system on chip, where the system on chip includes a master, a slave, and a bus, and the master and the slave are respectively provided with an authentication IP, and the apparatus includes:

a first generation module 81, configured to generate, in a first stage, a first interface excitation track file according to configuration information input by a user, where a format of the first interface excitation track file is the same as a predefined format of the user;

a first setting module 82 for setting a player on a port to which the authentication IP is connected to the bus;

a first input module 83 for inputting the first interface excitation trace file to the player, the player sending read commands and write commands to the port according to the first interface excitation trace file, and receiving read responses and write responses from the port;

And a second setting module 84, configured to set a sampler on the port, where the sampler is configured to sample data transmitted through the port, and analyze, according to a sampling result, to obtain performance data of bus interconnection of the system on chip, where the sampled data includes the read command, the write command, the read response, and the write response.

In one possible implementation, the apparatus further includes:

the first determining module is used for determining deviation between the performance data and the performance expected value of the current bus interconnection;

and the first analysis module is used for comparing the deviation with a first threshold value and determining a performance analysis result under the current bus interconnection according to the comparison result.

In one possible implementation, the apparatus further includes:

and the second generation module is used for generating mails comprising the performance analysis results and automatically sending the mails to the mailbox of the user.

In one possible implementation, the apparatus further includes:

and the regression module is used for automatically executing the steps of inputting the first interface excitation track file into the player and the following steps every preset time period after the bus interconnection is changed.

In one possible implementation, the apparatus further includes:

the first acquisition module is used for acquiring a second interface excitation track file of the system-on-chip in a real application scene in a second stage;

a second input module for inputting the second interface excitation trace file to the player, the player sending read commands and write commands to the port according to the second interface excitation trace file and receiving read responses and write responses from the port;

and the first driving module is used for driving the sampler to execute the steps of sampling the data transmitted through the port and the following steps.

In one possible implementation, the apparatus further includes:

the second acquisition module is used for acquiring a second interface excitation track file of the system-on-chip in a real application scene in a second stage;

a third input module for inputting the first interface excitation trace file and the second interface excitation trace file to the player, the player sending a read command and a write command to the port according to the first interface excitation trace file and the second interface excitation trace file, and receiving a read response and a write response from the port;

And the second driving module is used for driving the sampler to execute the steps of sampling the data transmitted through the port and the following steps.

In one possible implementation manner, the first interface excitation trace file includes a plurality of lines of data, each line of data is used for generating a command, and each line of data includes one or more of a port number, a read/write identifier, a valid time, a handshake time, a read/write number, a transmission start address, a transmission length, a transmission bit width, a transmission type, a transmission lock signal, a transmission priority, transmission buffer information, transmission protection information, and transmission user information;

In one possible implementation, the player sends read commands and write commands to the port according to the first interface excitation trace file, and receives read responses and write responses from the port, including:

processing according to the first interface excitation track file to obtain a write command queue and a read command queue;

sequentially sending the write commands stored in the write command queue through a port where the replay device is located;

sequentially sending the read commands stored in the read command queue through the port where the replay device is located;

A write response corresponding to each write command stored in the write command queue and a read response corresponding to each read command stored in the read command queue are received.

In one possible implementation, the read command further includes a read command valid signal, a read command handshake signal, the write command further includes a write command valid signal, a write command handshake signal,

the performance data includes write command transfer delay, read command transfer delay, write response transfer delay, first read response transfer delay, second read response transfer delay, bandwidth,

the sampling the data transmitted through the port, and analyzing the performance data of the bus interconnection of the system on chip according to the sampling result, including:

sampling the write command valid signal and the write command handshake signal, and obtaining the write command transmission delay according to the interval of the sampling time of the write command valid signal and the sampling time of the write command handshake signal;

sampling the read command valid signal and the read command handshake signal, and obtaining the read command transmission delay according to the sampling time of the read command valid signal and the interval of the sampling time of the read command handshake signal;

Sampling the write command and the write response corresponding to the write command, and obtaining the write response transmission delay according to the interval between the sampling time of the write response and the sampling time of the write command;

and sampling the read command and a plurality of read responses corresponding to the read command, obtaining the first read response transmission delay according to the interval between the sampling time of the read response sampled earliest and the sampling time of the read command, obtaining the second read response transmission delay according to the interval between the sampling time of the read response sampled latest and the sampling time of the read command, and obtaining the bandwidth according to the ratio of the byte number of the read response sampled and the number of the read commands sampled.

In some embodiments, functions or modules included in an apparatus provided by the embodiments of the present disclosure may be used to perform a method described in the foregoing method embodiments, and specific implementations thereof may refer to descriptions of the foregoing method embodiments, which are not repeated herein for brevity.

The disclosed embodiments also provide a computer readable storage medium having stored thereon computer program instructions which, when executed by a processor, implement the above-described method. The computer readable storage medium may be a volatile or nonvolatile computer readable storage medium.

The embodiment of the disclosure also provides an electronic device, which comprises: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to implement the above-described method when executing the instructions stored by the memory.

Embodiments of the present disclosure also provide a computer program product comprising computer readable code, or a non-transitory computer readable storage medium carrying computer readable code, which when run in a processor of an electronic device, performs the above method.

Fig. 9 shows a block diagram of an apparatus 1900 according to an embodiment of the disclosure. For example, the apparatus 1900 may be provided as an electronic device. Referring to fig. 9, the apparatus 1900 includes a processing component 1922 that further includes one or more processors and memory resources represented by memory 1932 for storing instructions, such as application programs, that are executable by the processing component 1922. The application programs stored in memory 1932 may include one or more modules each corresponding to a set of instructions. Further, processing component 1922 is configured to execute instructions to perform the methods described above.

The apparatus 1900 may further comprise a power component 1926 configured to perform power management of the apparatus 1900, a wired or wireless network interface 1950 configured to connect the apparatus 1900 to a network, and an input/output interface 1958 (I/O interface). The apparatus 1900 may operate based on an operating system stored in the memory 1932, such as Windows Server ^TM ，Mac OS X ^TM ，Unix ^TM , Linux ^TM ，FreeBSD ^TM Or the like.

In an exemplary embodiment, a non-transitory computer readable storage medium is also provided, such as memory 1932, including computer program instructions executable by processing component 1922 of apparatus 1900 to perform the above-described methods.

The present disclosure may be a system, method, and/or computer program product. The computer program product may include a computer readable storage medium having computer readable program instructions embodied thereon for causing a processor to implement aspects of the present disclosure.

The computer readable storage medium may be a tangible device that can hold and store instructions for use by an instruction execution device. The computer readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium would include the following: portable computer disks, hard disks, random Access Memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static Random Access Memory (SRAM), portable compact disk read-only memory (CD-ROM), digital Versatile Disks (DVD), memory sticks, floppy disks, mechanical coding devices, punch cards or in-groove structures such as punch cards or grooves having instructions stored thereon, and any suitable combination of the foregoing. Computer-readable storage media, as used herein, are not to be construed as transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., optical pulses through fiber optic cables), or electrical signals transmitted through wires.

The computer readable program instructions described herein may be downloaded from a computer readable storage medium to a respective computing/processing device or to an external computer or external storage device over a network, such as the internet, a local area network, a wide area network, and/or a wireless network. The network may include copper transmission cables, fiber optic transmissions, wireless transmissions, routers, firewalls, switches, gateway computers and/or edge servers. The network interface card or network interface in each computing/processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium in the respective computing/processing device.

Computer program instructions for performing the operations of the present disclosure can be assembly instructions, instruction Set Architecture (ISA) instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, c++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer readable program instructions may be executed entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computer (for example, through the Internet using an Internet service provider). In some embodiments, aspects of the present disclosure are implemented by personalizing electronic circuitry, such as programmable logic circuitry, field Programmable Gate Arrays (FPGAs), or Programmable Logic Arrays (PLAs), with state information of computer readable program instructions, which can execute the computer readable program instructions.

Various aspects of the present disclosure are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer-readable program instructions.

These computer readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable medium having the instructions stored therein includes an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.

The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer, other programmable apparatus or other devices implement the functions/acts specified in the flowchart and/or block diagram block or blocks.

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

The foregoing description of the embodiments of the present disclosure has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various embodiments described. The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or the technical improvements in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A performance analysis method for analyzing performance of bus interconnection of a system on chip, the system on chip including a master, a slave, and a bus, the master and the slave being respectively provided with a verification IP, the method comprising:

in a first stage, generating a first interface excitation track file according to configuration information input by a user, wherein the format of the first interface excitation track file is the same as a predefined format of the user;

setting a replay on a port to which the authentication IP is connected to the bus;

inputting the first interface excitation trace file into the player, the player sending read commands and write commands to the port according to the first interface excitation trace file and receiving read responses and write responses from the port;

And setting a sampler on the port, wherein the sampler is used for sampling data transmitted through the port, analyzing and obtaining the performance data of the bus interconnection of the system on chip according to a sampling result, and the sampled data comprises the read command, the write command, the read response and the write response.

2. The method according to claim 1, wherein the method further comprises:

and comparing the deviation with a first threshold value, and determining a performance analysis result under the current bus interconnection according to a comparison result.

3. The method according to claim 2, wherein the method further comprises:

4. The method according to claim 1, wherein the method further comprises:

5. The method according to claim 1, wherein the method further comprises:

In a second stage, a second interface excitation track file of the system on chip in a real application scene is obtained;

inputting the second interface excitation trace file to the player, the player sending read commands and write commands to the port according to the second interface excitation trace file and receiving read responses and write responses from the port;

and performing the steps of sampling the data transmitted through the port and thereafter.

6. The method according to claim 1, wherein the method further comprises:

inputting the first interface excitation track file and the second interface excitation track file into the player, wherein the player sends a read command and a write command to the port according to the first interface excitation track file and the second interface excitation track file, and receives a read response and a write response from the port;

7. The method of claim 2, wherein the first interface stimulus trace file includes a plurality of rows of data, each row of data being used to generate a command, each row of data including one or more of a port number, a read/write identification, a valid time, a handshake time, a read/write number, a transmission start address, a transmission length, a transmission bit width, a transmission type, a transmission lock signal, a transmission priority, transmission buffer information, transmission protection information, and transmission user information;

8. The method of claim 7, wherein the player transmitting read commands and write commands to the port and receiving read responses and write responses from the port according to the first interface excitation trace file comprises:

9. The method of claim 7, wherein the read command further comprises a read command valid signal, a read command handshake signal, wherein the write command further comprises a write command valid signal, a write command handshake signal,

10. A performance analysis apparatus for analyzing performance of bus interconnection of a system on chip including a master, a slave, and a bus, the master and the slave being respectively provided with a verification IP, the apparatus comprising:

the first generation module is used for generating a first interface excitation track file according to configuration information input by a user in a first stage, wherein the format of the first interface excitation track file is the same as a predefined format of the user;

a first setting module for setting a player on a port to which the authentication IP is connected to the bus;

a first input module for inputting the first interface excitation trace file to the player, the player sending read commands and write commands to the port according to the first interface excitation trace file and receiving read responses and write responses from the port;

the second setting module is used for setting a sampler on the port, wherein the sampler is used for sampling data transmitted through the port and analyzing and obtaining the bus interconnection performance data of the system on chip according to a sampling result, and the sampled data comprises the read command, the write command, the read response and the write response.

11. An electronic device, comprising:

a processor;

a memory for storing processor-executable instructions;

wherein the processor is configured to implement the method of any one of claims 1 to 9 when executing the instructions stored by the memory.

12. A non-transitory computer readable storage medium having stored thereon computer program instructions, which when executed by a processor, implement the method of any of claims 1 to 9.