CN1316695A - Integrated method for analoging and testing ASIC chip by combining software with hardware - Google Patents
Integrated method for analoging and testing ASIC chip by combining software with hardware Download PDFInfo
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- CN1316695A CN1316695A CN 00113353 CN00113353A CN1316695A CN 1316695 A CN1316695 A CN 1316695A CN 00113353 CN00113353 CN 00113353 CN 00113353 A CN00113353 A CN 00113353A CN 1316695 A CN1316695 A CN 1316695A
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Abstract
An integrated method for simulating and testing ASIC design by the cooperation of hardware and software is based on "existing-response" principle, and features that the ASIC design is simulated by the cooperation of hardware and software and the "exciting-response" method is used for its test. Its advantages include high simulating level and successful rate of ASIC design, and low cost.
Description
The present invention relates to the integral method of ASIC (special IC) design carrying out software and hardware cooperation simulation with test.
Along with the raising of asic chip integrated level and the enhancing of function, the simplation verification to ASIC in the design process of ASIC is had higher requirement.Because have only the success ratio that could guarantee its throwing sheet to its design through sufficient simplation verification.Software simulator (for example, the Verilog of the U.S.) in commercial electronic design automation (EDA) instrument is the main tool of asic chip being carried out simplation verification at present.But such software simulator is difficult to realize the simplation verification of higher level owing to be subjected to the restriction of software modeling.The objective of the invention is to design ASIC software and hardware cooperation simulation and the integrated instrument of testing (be called for short mould and survey instrument).Because mould is surveyed instrument the ASIC that is designing organically is joined together as soft model and die type (for example microprocessor), the code and the actual die type of the soft model (being ASIC) in the simulation are moved together, saved in the software simulator and will carry out software modeling and many restrictions of bringing corresponding die type, make the simulation rank be improved (can on architecture level, plate level, three ranks of ASIC level, simulate), thereby make that simulation is more abundant, more effectively guaranteed to throw the success ratio of sheet; Simultaneously, utilize this mould to survey instrument and also can the ASIC after producing be tested, accomplish that an instrument is dual-purpose, removed the overhead that needs to buy or develop special testing apparatus from, save cost.
Technical scheme of the present invention is based on " excitation-response " principle, and asic chip is carried out software and hardware cooperation simulation and test.Concrete grammar is: if be operated in analog form, cooperation simulation application software (for example is based upon the eda software simulator, Verilog-XL) on the analog platform, replace soft model corresponding, software simulator and die type are organically combined with it by direct use die type.Simulation application software utilizes the numerical value change chain mechanism of software simulator to monitor the variation of this die type input port constantly in each simulation.If input port changes, can carry out quantitative check, judge whether the port input satisfies clocking discipline.If satisfy, then the Shell file according to this die type is optimized processing to input attributes, form input pattern excitation vector IPattern then, the parallel bus interface of surveying instrument from the mould of the design according to the present invention writes the current address of input pattern memory IPM by storage controller MC with it.Like this, the IPattern that had write IPM before this moment forms the die type incentive mode vector in this moment jointly together with this IPattern that writes IPM constantly.Start burst (Burst) working method of MC, make IPM read the mode speed of work clock (promptly with) this incentive mode vector is continuously loaded to the input port that is placed in the die type on the adapter, till the incentive mode vector has been loaded with burst.When the input port of die type loads the input pattern excitation vector, output mode storer OPM also is recovered to output mode vector OPattern the sequence address of OPM by the output port of adapter from the die type with the burst WriteMode speed of work clock (promptly with).The OPattern that simulation application software will be stored in last address of OPM reads back by parallel bus interface, after the deferred message that adds the upper die type, form the final output mode vector of this die type, and it is acted on each output port of this soft model example, thereby realized software and hardware cooperation simulation process.If the test mode of being operated in, the first step: the test profile of editor's measured piece (being ASIC), this file comprise necessary test condition, as: clock frequency, time delay, pumping signal level, and the logical position concerns table of comparisons filename, test patterns filename etc.; Second step: generate the corresponding relation list file between the logic pin of the adapter physical pin of measured piece and test patterns according to the Shell file of measured piece; The 3rd step: the test patterns file conversion of the measured piece that software simulator is provided becomes mould to survey the test patterns file of instrument internal format; The 4th step: the test profile of Test Application software processes measured piece, logical position concern the test patterns file of table of comparisons file and mould survey instrument internal format, by master controller MS mould are surveyed instrument and carry out the test condition configuration; With the test patterns in the test patterns file, promptly IPattern writes the sequence address of input pattern memory I PM by memory controller MC from parallel bus interface one by one.Start burst (Burst) mode of MC, make IPM read the mode speed of work clock (promptly with) this test patterns vector is continuously loaded to the input port that is placed in the measured piece on the adapter, till the test patterns vector has been loaded with burst.Meanwhile, OPM also preserves from the output port of measured piece continuously is recovered to OPattern oneself sequence address with the burst WriteMode.The 5th step: by address order from small to large, reading back one by one is kept at the middle OPattern of OPM by parallel bus interface, and the expectation that itself and software simulator are provided is reclaimed and yard compared.If both equate that then the corresponding IPattern test patterns of OPattern is passed through test therewith; Otherwise, be saved in the error logger file with this OPattern with its corresponding expectation recovery sign indicating number, so that compare, analyze.
Description of drawings:
The logical diagram of Fig. 1 for a certain asic chip is simulated;
The logical diagram of Fig. 2 for a certain asic chip is tested.
The invention will be further described below in conjunction with accompanying drawing.
The process that the present invention carries out software and hardware cooperation simulation to ASIC is as shown in Figure 1: (for example, numerical value change chain mechanism Verilog-XL) monitors the variation of die type input port constantly to simulation application software in each simulation by software simulator.If input port changes, carry out quantitative check, judge whether input port satisfies clocking discipline.If satisfy, then the Shell file according to this die type is optimized processing to input attributes, forms the input mode vector IPattern of the C end of soft model Asic1 then.And it is preserved by the current address that storage controller MC writes input pattern memory IPM from parallel bus interface.The IPattern that had write IPM before this moment forms this moment die type incentive mode vector jointly together with this IPattern that writes IPM constantly.Start burst (Burst) mode of MC, the IPattern vector that is kept among the IPM is continuously loaded to the input port of the die type speed with work clock by adapter, till the incentive mode vector has been loaded.When the input port of die type loads the input pattern excitation vector, output mode storer OPM also is recovered to output mode vector OPattern the sequence address of OPM by the output port f of adapter from the die type with the burst WriteMode speed of work clock (promptly with).The OPattern that simulation application software will be stored in last address of OPM reads back by parallel bus interface, after the deferred message that adds the upper die type, form the final output mode vector of this die type, and with its output as Asic1, make its input that acts on soft model Asic2, thereby finish simulation soft model Asic1, Asic2.
The process that the present invention tests ASIC is as shown in Figure 2:
The first step: the test profile of editor's measured piece (this example is a non-conjunction, and is together following), this file comprises necessary test condition;
Second step: generate its adapter physical pin and the corresponding relation list file between the logic pin of test patterns according to the Shell file of measured piece;
The 3rd step: the test patterns file conversion of the measured piece that simulator is provided becomes mould to survey the test patterns file of instrument internal format;
The 4th step: the test profile of Test Application software processes measured piece, logical position concern the test patterns file of table of comparisons file and mould survey instrument internal format, by master controller MS mould are surveyed instrument and carry out the test condition configuration; Test patterns IPattern in the test patterns file is write the sequence address of input pattern memory IPM by storage controller MC one by one from the row bus interface.Start burst (Burst) mode of storage controller MC, till with the speed of work clock this test patterns vector having been loaded.Simultaneously, storage controller MC also preserves from the output port of measured piece successively is recovered to OPattern the sequence address of output mode memory OPM by adapter with burst mode.
The 5th step: by address order from small to large, reading back one by one is kept at OPattern among the output mode memory OPM by parallel bus interface, and the expectation that itself and software simulator are provided is reclaimed and yard compared.
Test patterns when the present invention tests non-conjunction, recovery sign indicating number, expected value such as following table:
| Test patterns (IPattern) | Reclaim sign indicating number (Opattern) | Expected value (for relatively) | |
| ????a | ????b | ????c | |
| ????0 | ????0 | ????1 | ????1 |
| ????0 | ????1 | ????1 | ????1 |
| ????1 | ????0 | ????1 | ????1 |
| ????1 | ????1 | ????0 | ????0 |
Equate with expected value owing to reclaim sign indicating number OPattern, so reclaim the corresponding test patterns IPattern of sign indicating number OPattern therewith by test.
Claims (3)
1, a kind of integral method that asic chip is carried out software and hardware cooperation simulation and test is characterized in that based on " excitation-response " principle, and asic chip is carried out software and hardware cooperation simulation and test.
2, the integral method that asic chip is carried out software and hardware cooperation simulation and test according to claim 1, the motivational techniques that it is characterized in that it are: if be operated in analog form, cooperation simulation application software (for example is based upon the eda software simulator, Verilog-XL) on the analog platform, replace soft model corresponding by direct use die type with it, software simulator and die type are organically combined, simulation application software utilizes software simulator numerical value change chain mechanism to monitor the variation of this die type input port constantly in each simulation, if input port changes, can carry out quantitative check, judge whether the port input satisfies clocking discipline, if satisfy, then the Shell file according to this die type is optimized processing to input attributes, form input pattern excitation vector IPattern then, the parallel bus interface of surveying instrument from the mould of the design according to the present invention writes the current address of input pattern memory IPM by storage controller MC with it, like this, the IPattern that had write IPM before this moment forms the die type incentive mode vector in this moment jointly together with this IPattern that writes IPM constantly; If the test mode of being operated in, Test Application software is according to the Shell file of this measured piece, after the test patterns file of the measured piece that software simulator is provided carries out suitable processing, also form the input pattern excitation vector Ipattern that same format is arranged with analog form, in the mode identical, promptly one by one IPattern is write in the sequence address of IPM then by memory controller MC with simulation; No matter be analog form or test mode, after this all start burst (Burst) working method of MC, make IPM read mode with burst, promptly this incentive mode vector is continuously loaded to being placed in the die type on the adapter or the input port of measured piece with the speed of work clock, till the incentive mode vector has been loaded, so just finished the loading process of motivation to die type or measured piece.
3, the integral method that asic chip is carried out software and hardware cooperation simulation and test according to claim 1, the response method that it is characterized in that it is: when the input port to die type or measured piece loads the input pattern excitation vector, output mode storer OPM is also with the burst WriteMode, promptly the speed with work clock is recovered to output mode vector OPattern the sequence address of OPM by the output port of adapter from die type or measured piece, if be operated in analog form, the OPattern that simulation application software then will be stored in last address of OPM reads back by parallel bus interface, after the deferred message that adds the upper die type, form the final output mode vector of this die type, and it is acted on each output port with the corresponding soft model example of this die type; If be operated in test mode, the OPattern that Test Application software then will be stored in the OPM sequence address reads back one by one by parallel bus interface, the expectation recovery sign indicating number that provides with software simulator compares, if both equate, then the corresponding input test sign indicating number of OPattern passes through test therewith, otherwise be saved in the error logger file so that compare, analyze with this OPattern with its corresponding expectation recovery sign indicating number, so far, finished recovery response process to die type or measured piece.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 00113353 CN1128409C (en) | 2000-04-03 | 2000-04-03 | Integrated method for analoging and testing ASIC chip by combining software with hardware |
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| Application Number | Priority Date | Filing Date | Title |
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| CN 00113353 CN1128409C (en) | 2000-04-03 | 2000-04-03 | Integrated method for analoging and testing ASIC chip by combining software with hardware |
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| CN1316695A true CN1316695A (en) | 2001-10-10 |
| CN1128409C CN1128409C (en) | 2003-11-19 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100418204C (en) * | 2002-06-03 | 2008-09-10 | 威盛电子股份有限公司 | Process flow for mfg. chip capable of pretesting efficiency, and testing method thereof |
| CN115659885A (en) * | 2022-12-29 | 2023-01-31 | 摩尔线程智能科技(北京)有限责任公司 | System and method for simulation test |
| CN115685785A (en) * | 2022-12-29 | 2023-02-03 | 摩尔线程智能科技(北京)有限责任公司 | Universal bus model and simulation test method |
| CN117031256A (en) * | 2023-10-07 | 2023-11-10 | 紫光同芯微电子有限公司 | Chip testing system and method |
-
2000
- 2000-04-03 CN CN 00113353 patent/CN1128409C/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100418204C (en) * | 2002-06-03 | 2008-09-10 | 威盛电子股份有限公司 | Process flow for mfg. chip capable of pretesting efficiency, and testing method thereof |
| CN115659885A (en) * | 2022-12-29 | 2023-01-31 | 摩尔线程智能科技(北京)有限责任公司 | System and method for simulation test |
| CN115685785A (en) * | 2022-12-29 | 2023-02-03 | 摩尔线程智能科技(北京)有限责任公司 | Universal bus model and simulation test method |
| CN117031256A (en) * | 2023-10-07 | 2023-11-10 | 紫光同芯微电子有限公司 | Chip testing system and method |
| CN117031256B (en) * | 2023-10-07 | 2024-03-01 | 紫光同芯微电子有限公司 | Chip testing system and method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1128409C (en) | 2003-11-19 |
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