KR20060101127A - Efficient functional verification apparatus in esl design methodology, and the verification method using the same - Google Patents

Abstract

The present invention relates to an efficient verification apparatus for design verification at the system level of a very complex digital system designed and an effective verification method using the same.

In the present invention, the verification software of the present invention, which is performed on any computer, adds additional code or additional circuits to the design code, and, if necessary, converts the original design code into another code having high abstraction level. Automated method using or manual modeling through the modeling process to perform one or more simulations. Simulation execution is divided into leading simulation using high level of abstraction design code and lower simulation level of low level of abstraction. The latter simulation which uses the result of leading simulation effectively uses one or more simulations on one or more computers. In addition to enabling sequential execution, two or more simulators running on two or more computers connected to the network can also be used to perform parallel execution completely independent of each other, thereby significantly reducing overall verification time and verification cost. It can greatly increase the efficiency of verification.

Description

Effective Functional Verification Apparatus in ESL Design Methodology, and the Verification Method Using the Same}

1 is a diagram schematically showing an example of a design verification apparatus according to the present invention.

2 is a diagram schematically showing still another example of the design verification apparatus according to the present invention;

3 is a schematic illustration of an example of the configuration of a VP in comparison with the corresponding DUV example;

4 is a diagram schematically showing an example of a situation in which a simulation for a DUV is performed in parallel using a simulation result of s-VP.

5 is a diagram schematically showing an example of a situation in which a simulation for a DUV is performed in parallel by using a simulation result of t-VP.

FIG. 6 schematically illustrates another example of a situation in which a simulation for a DUV is performed in parallel using a simulation result of t-VP. FIG.

FIG. 7 is a schematic diagram illustrating a process of quickly performing design verification for a DUV using the apparatus as shown in FIG. 2 and using simulation results of s-VP. FIG.

FIG. 8 schematically illustrates another process of quickly performing design verification for a DUV using the apparatus as shown in FIG. 2 and using simulation results of s-VP.

FIG. 9 is a schematic diagram illustrating a process of quickly performing design verification for a DUV using the apparatus as shown in FIG. 2 and using simulation results of t-VP. FIG.

FIG. 10 is a schematic illustration of another process of quickly performing design verification for a DUV using the same device as in FIG. 2 and using the simulation results of t-VP. FIG.

FIG. 11 is a schematic illustration of another process of quickly performing design verification for a DUV using the device as shown in FIG. 2 and using the simulation results of t-VP. FIG.

Figure 12 is a schematic illustration of an example of a process of (a) from the original design code, (b) analyzing it, and (c) automatically generating s-VP.

<Explanation of symbols for main parts of drawing>

32: Verification Software 34: HDL Simulator

35: computer 36: VP

37: Design object representing VP 38: Design object representing Design Block

39: design object representing the design module

40: design object representing the DUV

TECHNICAL FIELD The present invention relates to a technique for verifying a design at an electronic system level (abbreviated as ESL in the future). An apparatus and a verification method using the same.

With the recent rapid development of integrated circuit design and semiconductor process technology, the scale of digital circuits or digital system designs has grown from at least millions of gates to tens of millions of gates, and its composition has become extremely complicated. Is continuing to expand, with more than 100 million gate designs expected in the near future. However, competition in the market has become more intense, and the need to develop superior products in a short time has led to shorter design periods, which has become a very important factor in determining product success. Therefore, in recent chip designs, the ESL design technique is attracting attention from the industry as a new design method. Most chips designed using this ESL design technique are system on a chip (SOC), which has one or more processor cores. It must be done at the same time. Therefore, in order to proceed with the software development at the same time as the design of the hardware, the trend is to create and use a virtual platform (hereinafter, referred to as VP) that modeled the hardware in software, which is an executable specification. It also plays a role. The VP is fast enough to develop software, so it is important not to model at the register transfer level (RTL) using languages such as Verilog or VHDL, but rather than RTL using languages such as C / C ++ or SystemC. Modeling is done at the level of transaction or algorithm at high abstraction level. However, due to the limitation of the synthesis technology, it is not common to implement a chip using VP modeled at the transaction level directly, and it is common to implement a chip using a design coded in a separate RTL. .

However, the most time consuming time in such a recent SOC chip design is that chip design verification takes up to 70% of the total design time, and this process is a bottleneck for the overall design. In the ESL design, the hardware design verification is carried out through the same method without any change from the existing situation.

In SOC chip design, there are two targets to design as before, one is DUV (Design Under Verification) and the other is testbench (abbreviated as TB). The DUV is the design target ultimately made into a chip through the semiconductor manufacturing process, and the testbench is used to simulate the DUV by modeling the ambient conditions in which the chip is implemented. When a DUV is to be verified by simulation, it is common for the test bench to apply an input to the DUV and accept and process the result output from the DUV with the authorized input. For the sake of convenience, in the future, DUV is a design object ultimately implemented as a chip, and is a design object coded in RTL, and VP is defined as a model modeled at a higher level (eg, transaction level) than RTL. These DUVs and testbenches are generally hierarchical and have one or more submodules inside them. Each of these submodules can be called a design block, and there are design modules inside the design block. Modules exist. Such design blocks, or design modules, or submodules, DUVs, and test benches, or combinations thereof, are all referred to as design objects.

There are two methods of VP modeling. The first is the state information present in the DUV (all memory units in the DUV, including the flip-flops or latches, and, if there is a combined loop, the signal lines present in the combined loop-or these are the values of the models modeled). This is to model all variables or signal lines to define the same in VP. The advantage of this first modeling technique is that the VP model can be generated by an automated method in the DUV. The disadvantage is that the increase in the execution speed of the modeled VP is limited compared to the DTL at the RTL level. The model generated through the method will be referred to as s-VP). In general, the DUV has a hierarchical structure. The second is that the VP model has the same hierarchical structure as the DUV from the top of the hierarchy to a certain level. For example, if there is a three-level hierarchy of systems at the top of the DUV, a block at the bottom of the system, and a module at the bottom of the block, then the VP is a system of the top level, a two-level hierarchy of blocks at the bottom of the system. The system of the DUV and the system of the VP, each block of the DUV and each corresponding block of the VP correspond structurally in 1: 1 (see FIG. 3). The advantage of this second model approach is that the VP can run very fast compared to the RTL-level DUV, but the disadvantage is that it is difficult to create the model in an automated fashion, which is why the VP is usually used manually. This model is called t-VP.

Accordingly, an object of the present invention is a simulation-based design verification apparatus and a design verification method using the same, which greatly improves the performance and efficiency of the simulation for quickly performing hardware verification or hardware / software simultaneous verification that is a bottleneck in SOC design. In providing.

In order to achieve the above objects, the design verification apparatus according to the present invention comprises one or more computers in which verification software and one or more simulators are installed. The verification software runs on a computer, and if there are two or more computers in the design verification device, these two or more computers are networked to enable the movement of files between the computers via the network. The one or more simulators may consist solely of event-driven simulators, or may consist of both event-driven simulators and cycle-based simulators, or may consist solely of cycle-based simulators, or cycle-based simulators and tran It can be configured as a projection-based simulator, or as an event-driven simulator, a cycle-based simulator, and a transaction-based simulator.

To quickly perform hardware verification or hardware / software co-verification in an ESL design using VP, the results of running VP at a high level of abstraction are utilized. Design verification will be performed for the DUV. Specifically, simulation for design verification is divided into front-end simulation using VP with high level of abstraction and trailing-side simulation using DUV with low level of abstraction.Back-end simulation using the result of leading-edge simulation is performed once on one or more computers. The above simulations can be performed sequentially using one or more simulators, as well as parallel execution independently of each other using two or more simulators running on two or more computers connected in a network. It allows for a significant reduction and greatly increases the efficiency of verification. In detail, this is classified into a case of using s-VP and a case of using t-VP.

In the case of designing an ESL using s-VP, while executing s-VP, state information is stored at one or more specific simulation time points (this is called state information of s-VP, and n simulation time points are t1 and t2). , .., tn and state information at each time point is represented by S (t1), S (t2), ..., S (tn)). In some cases, all inputs applied to the s-VP and one or more specific internal signal lines (a situation where it is necessary to probe one or more specific internal signal lines are used when one or more black box blocks are used for the s-VP). , Black box blocks will be described later) and continuously probed and stored over the entire simulation section, and the probed values are divided and stored by one or more sections (the total number of sections is one more than the state information storage time point). (This is referred to as input information of s-VP and denoted as I (t0), I (t1), I (t2), ..., I (tn)). The probe made over the entire simulation section may be cycle based, transaction based, or event based.

As mentioned above, S (t1), S (t2), ..., S (tn) obtained by executing s-VP at a very fast simulation speed and in some cases I (t0), I (t1), I ( By using t2), ..., I (tn) for DUV verification, it is possible to significantly shorten the verification time of DUV performed at the RTL or gate level. This shortening of verification time is possible for two reasons. Firstly, S (t1), S (t2), ..., S (tn) and in some cases I (t0), I (t1), I (t2), ..., I (tn) When used for the DUV verification, not only the simulation of the DUV in a specific verification interval is possible (see FIG. 4), but also (the initial state of the DUV by using I (tn) and S (tn) during the simulation). If the information is set to S (tn) and I (tn) is applied to the DUV, the simulation is skipped from the first section to the nth section, and only the last section, n + 1 section, can be simulated.) In addition, the simulation on these two or more spheres can be performed in parallel using two or more simulators (see FIG. 5), thereby greatly reducing the DUV verification time. That is, assuming that n + 1 HDL (Hardware Description Language) simulators (eg Synopsys VCS, or Cadence NC-Verilog, or Mentor ModelSim) are installed on the n + 1 computer, the first section is the first Using a computer and an HDL simulator, the simulation of the DUV is simulated with I (t0) as the input and the initial initial condition of the DUV (denoted as S (t0)), at the same time the second section in parallel with the second computer. Using the HDL simulator and simulation of the DUV with I (t1) as input and the initial state information of the DUV as S (t1), the 3rd section is paralleled with the second computer and HDL. Using the simulator, I (t2) is input to simulate the DUV and the initial state information of the DUV is set to S (t2). In the n + 1 section, I (tn) is input to simulate the DUV using the n + 1th computer and the HDL simulator, and the initial state information of the DUV is set to S (tn) in parallel with the other sections. When the simulation is performed, it is possible to quickly perform the simulation for the entire section using the DUV. Second, it is possible to compare the simulation results with s-VP and the simulation results with DUV in real time during the simulation run with DUV, so that the simulation of DUV can be performed as soon as a discrepancy between the two simulation results is found. It can reduce the overall verification time by focusing and promptly debugging by analyzing the cause of the inconsistency. This entire process is prepared and executed in an automated manner by the verification software of the design verification apparatus according to the invention.

As an example of a specific method of automatically generating s-VP, DUV can be used in RTL-level original design code dictated at RTL level in HDL such as Verilog or VHDL or SDL- (System Description Language) such as SystemVerilog or SystemC. Fast logical conversions in this process, such as removing loop statements by un-rolling loop statements, removing unnecessary lists from the sensitivity list, or in some cases removing delay-related statements. It is possible to convert design codes through logic translation or fast logic synthesis. Specifically, parsing and elaborating the original RTL-level code into a structural form of generic translation library cells (except flip-flops or latches, which are repositories in common library cells). Has only D type, the input of D type flip-flop or latch is divided into data input and timing input, the output is one data output Q-output, the data input is one D-output and the timing input is clock input and asynchronous. Set inputs, asynchronous reset inputs, in the case of latches, the clock inputs are also referred to as enable inputs, so that the outputs of the reservoir (flip-flop or latch) and the timing inputs and primary inputs (DUV in the test bench). The data inputs of the repository and the rest of the intermediate variables, leaving only the variables and signals that define Eliminate the signals as much as possible (enhancing both the data inputs of these repositories and the rest of the intermediate variables or intermediate signals, if possible) and, if necessary, all of the primary outputs (signals from the DUV to the test bench). It is also possible to remove even part of. That is, the outputs and timing inputs of all reservoirs present in the DUV are expressed using injection forces and outputs of other reservoirs without using any of the reservoir data inputs and the remaining intermediate variables or intermediate signals, or at least It is expressed using the data inputs of the repository and the remaining intermediate variables or intermediate signals. Also, if the main output is not removed, the main outputs that have not been removed can also be expressed using only the injection forces and the output of the reservoir, or by using the data inputs of the minimum reservoir together with the remaining intermediate variables or intermediate signals. (See FIG. 12). Languages that can be used in such an expression process include SDL (System Description Language) language (for example, SystemC code, C ++, C code, or SystemVerilog), or HDL (Hardware Description Language) language (for example, Verilog or VHDL).

In this process, the code modeling the combined circuit part is considered to be evaluated the least number of times in the simulation process, or special data structure (e.g., binary decision diagram or multiple-valued decision diagram) that can be evaluated very quickly. ) Can be expressed at the RTL level. In addition, if the DUV has IP (Intellectual Property) blocks or large memory (RAM or ROM) blocks (collectively referred to as black box blocks) that are used without seeing the internal design code, The outputs of the blocks must also be treated as pseudo primary inputs and considered the same as the injection forces. That is, when the outputs and timing inputs of all reservoirs present in the DUV, or specific main outputs are expressed using the injection forces and the outputs of other reservoirs, the temporary main inputs are also used as the injection forces. The outputs and timing inputs of all the reservoirs present in the DUV must be represented, or specific main outputs.

The model represented through this conversion process can significantly reduce the number of signals or variables (specifically regs or wires in Verilog and signals or variables in VHDL) compared to the original RTL design code. In addition, the loop statements existing in the original RTL design code are expanded during the conversion process, eliminating loop statements, unnecessary lists in the sensitivity list, and removing all delay-related statements. Can be performed. In addition, it is possible to speed up the simulation by advancing the entire model expressed in a cycle, simulation, or event unit in the simulation. In addition, the model expressed in this manner may be performed in part of a cycle and the rest may be performed in an event unit, or the model may be partially in a transaction unit, and the rest may be performed in an event unit, or a model may be partially formed. You can further speed up the simulation by proceeding in transaction units and the rest in cycles, or in part by modeling in transaction units, in part by cycles, and in the event units. .

Next, the case of using t-VP as VP will be described. t-VP has the same hierarchy as DUV with the highest hierarchy. Therefore, in the course of executing the simulation using t-VP at high speed, all the inputs in each of the one or more independent design objects DO1, DO2, ..., DOi, which exist in the hierarchical structure of t-VP, are all sections of the simulation. Probe over. The corresponding design objects DO1, DO2, ..., DOi are independent, and when all of them are combined, the DO1, DO2, DO2, so that the largest design object DO_t of the DUV to be verified in hardware verification or hardware / software simultaneous verification is configured. ..., construct DOi (that is, DO_t = DO1 ∪ DO2 ∪ ... ∪ DOi and any two DOx ∩ DOy = Ø, where x and y are one of 1, 2, ..., i) Or x and y cannot be the same). The probe, which is performed over the entire simulation section, may be cycle-based, transaction-based, or event-based. The input probe result for each design object may be I (DO1). , I (DO2), ..., 1 (DOi). Each of the design objects in these t-VPs also exists in the DUV. For the verification of the DUV, each of the design objects DO1, DO2, ..., DOi in the DUV is identified by I (DO1) and I (DO2). It is possible to run the simulation independently using I, DOi, and this simulation can be executed in parallel using two or more computers equipped with two or more HDL simulators. Using iHDL simulators equipped with a computer, the parallelism can be maximized. This simulation is called t-2-s simulation). This i t-2-s simulation is performed throughout the entire simulation section, and status information is provided at one or more identical simulation time points t1, t2, ..., tn for each of the corresponding design objects DO1, DO2, ..., DOi. Save it. In this case, it is important to note that the sum of the stored state information at a specific simulation time ts (s = 1, 2, ..., n) is the largest design object of the DUV to be verified by hardware verification or hardware / software simultaneous verification. Status information S (ts) (s = 1, 2, ..., n) for DO_t is obtained. Therefore, after S (ts) (s = 1, 2, ..., n) is obtained, S (t1), s (t2), ..., S (tn) is applied by applying the technique used in s-VP. When used for DUV verification, it is possible to significantly shorten the verification time of DUV. N (1) simulations are performed in parallel using either one simulator or two or more simulators by setting the initial state of DO_t n times with each of S (ts) (s = 1, 2, ..., n) I (t0), I (t1), I (t2), ..., I (tn) are only necessary values for I (DO1), 1 (DO2), ..., I (DOi) It can be obtained by dividing by time intervals.

Therefore, even when the ESL design is performed using the s-VP, it is possible to quickly verify the DUV by utilizing the execution result of the s-VP.

Next, the situation of using black box blocks in such an ESL design will be described. Black box blocks can only know the BFM (Bus Functional Model) level of operation (i.e., cycle-based or transaction-based or event-based operation at the I / O port), and the specific implementation method internally. Commonly referred to as design objects, such as processor cores (eg, ARM cores, Teak DSP cores, MIPS cores, etc.) or memory cores supplied from third parties. Since such black box blocks are usually encrypted, it is impossible to dump and store state information existing at one or more desired points during simulation. Therefore, in the case of the design using the black box blocks, one of the following two methods should be used to quickly perform the DUV design verification using the VP simulation results.

First, in the DUV design verification, when simulating the entire DUV, all the black box blocks in the DUV use BFM dump information of the black box blocks dumped while running VP instead of using the encrypted design code. Is to perform a simulation. Using the BFM dump information of the black box blocks can also be used to testbench the IPs for DUV verification.

Secondly, in the process of performing only the black box blocks from the simulation time 0 to the time point ts (s = 1, 2, ..., n) in the entire DUV, the remaining design objects of the DUV are disabled. And state information S (ts) (s = 1, 2, collected at the time ts (s = 1, 2, ..., n) obtained from the previous simulation using VP for the state of the remaining design objects of the DUV. After the state setting is performed using ..., n), after the time ts (s = 1, 2, ..., n), the simulation of the entire DUV is performed (see FIG. 6). As a specific example of how to disable the remaining design objects of the DUV in the process of performing the first process in the three processes described above to the time point ts (s = 1, 2, ..., n), DUV All the inputs of the rest of the design objects in the system are fixed to a fixed value using the force command of the HDL simulator to eliminate the generation of the event, or add additional code to prevent the event from being input to all inputs of the rest of the design objects in the DUV. It is. This three-step process can be carried out in an automated manner without human intervention, which means that the verification software in the present invention can be added to additional code or additions in an automated manner to the gate-level netlist generated by design code or synthesis. This is possible by adding a circuit. To explain an example of a situation in which the additional code or the additional circuit is executed, various controllability methods provided by the simulator can be used for the additional code, which includes the XMR of the simulator along with various control syntaxes of the HDL. (Cross Module Reference) or may include force / release procedural statements or system tasks such as PLI / VPI / FLI. Therefore, the above additional code or additional circuit is added to the original design code through the verification software of the present verification device so that the above steps can be automatically performed. Such execution can also be performed in parallel, which will be described in detail later with reference to the drawings.

Other objects and advantages of the present invention in addition to the above object will be apparent from the detailed description of the embodiments with reference to the accompanying drawings.

1 is a diagram schematically showing an example of a design verification apparatus according to the present invention composed of a computer having a simulator and a verification software of the present invention running on a computer.

Fig. 2 schematically shows another example of the design verification apparatus according to the present invention composed of the verification software of the present invention running on a computer, two or more computers having two or more simulators, and a computer network connecting these computers. Drawing.

3 is a diagram schematically showing an example of the configuration of the VP (specifically, an example of the configuration of t-VP) in comparison with the corresponding DUV example. The example shows that VP is composed of design blocks B1, B2, B3, B4, B5, and B6 as DUV. Of these, B1 is a black box block.

4 is a diagram schematically showing an example of a situation in which a simulation for a DUV is performed in parallel by using a simulation result of s-VP.

5 is a diagram schematically showing an example of a situation in which a simulation for a DUV is performed in parallel by using a simulation result of t-VP.

FIG. 6 is a diagram schematically illustrating another example of a situation in which a simulation for a DUV is performed in parallel by using a simulation result of t-VP.

FIG. 7 is a flowchart schematically illustrating a process of quickly performing design verification for a DUV using the apparatus as shown in FIG. 2 and using simulation results of s-VP.

In the step S100, during the s-VP simulation, additional code is added to the design code of the original s-VP to automatically store state information existing in all design objects except the black box block at a predetermined interval or at least one specific simulation time point. Add or add s-VP automatically from the DUV, add additional code to the design code of the DUV so that the simulation can be performed in parallel later, and proceed to step S102. In step S102, the state information storage interval or a storage time point is set, and the flow proceeds to step S104. In step S104, at the same time as performing the s-VP simulation, the state information is stored at a predetermined interval or at least one specific simulation time point, and the input values for all the design objects except the black box block are stored over the entire simulation section. Proceed to step S106. In step S106, the DUV to which the additional code is added is used, and the state information S (t1), S (t2), ..., S (tn) and the input information I (t0) and I (t1) stored in step S104. By using I (t2), ..., I (tn), the simulation of the DUV in each time period is performed in parallel and terminated.

FIG. 8 is a flowchart schematically showing another process of quickly performing a design verification for a DUV using the apparatus as shown in FIG. 2 and using simulation results of s-VP.

In the step S200, during the s-VP simulation, additional code is added to the design code of the original s-VP so that the state information existing in all design objects except the black box block is automatically stored at a predetermined interval or at least one specific simulation time point. Add or add s-VP automatically from the DUV, add additional code to the design code of the DUV so that the simulation of the DUV can be performed in parallel later, and proceed to step S202. In step S202, a state information storage interval or a storage time point is set, and the flow proceeds to step S204. In step S204, at the same time as performing the s-VP simulation, the state information is stored at a predetermined interval or at least one specific simulation time point, and the input values of all the design objects except the black box block are stored over the entire simulation section. The flow proceeds to step S206. In step S206, the DUV to which the additional code is added is used, and the state information S (t1), S (t2), ..., S (tn) and the input information I (t0), I (t1), Using I (t2), ..., I (tn), in parallel with the simulation of the DUV in each time interval, the status information obtained from the s-VP performance and the DUV performance are the same simulation time zone. The simulation is terminated at the point of time different from or at the point of final simulation.

FIG. 9 is a flowchart schematically showing a process of quickly performing a design verification for a DUV using the apparatus as shown in FIG. 2 and using a simulation result of t-VP.

In step S300, during the t-VP simulation, the original t-VP is designed so that all input values of one or more design objects of the hierarchical structure existing in the t-VP can be dumped and stored in the entire simulation section. Add additional code to the code or automatically generate the s-VP from the DUV, and add additional code to the design code of the DUV so that later simulations can be performed in parallel with the DUV. Proceed. In the step S302, the input values I (DO1), I (DO2),... In the entire simulation section for the design objects DO1, DO2, ..., DOi except the black box block while the t-VP simulation is performed. .., dumps I (DOi) and stores it and proceeds to step S304. In step S304, the state information storage interval or the storage time point is set, and the flow advances to step S306. In the step S306, the simulation of each design object is performed in parallel using input information of each design object stored in the step S302, and at the same time, the state information of all the design objects except the black box blocks is periodically spaced. Or at one or more simulation time points and proceeds to step S308. In step S308, I (DO1), I (DO2), ..., I (DOi) obtained in step S302 and state information of each of the design objects DO1, DO2, ..., DOi obtained in step S306 From the state information S (t1), S (t2), ..., S (tn) and input information I (t0), I (t1), I (t2), ..., I (tn) Proceed to step S310. In step S310, the DUV to which the additional code is added is used, and the status information S (t1), S (t2), ..., S (tn) and the input information I (t0) and I (t1) generated in step S308 are used. By using I (t2), ..., I (tn), the simulation of all DO_t of design objects in the DUV in each time interval except the black box block is performed in parallel.

FIG. 10 is a flowchart schematically showing another process of quickly performing a design verification for a DUV using the apparatus as shown in FIG. 2 and using the simulation result of t-VP.

In the step S400, during the t-VP simulation, all input values and all output values of one or more design objects of the hierarchical structure existing in the t-VP can be dumped and stored in all simulation sections. Add additional code to the design code of the original t-VP or automatically generate s-VP from the DUV, and add additional code to the design code of the DUV so that later simulations can be performed in parallel on the DUV. The flow proceeds to step S402. In step S402, t-VP is simulated and input values I (DO1), I (DO2),..., In the entire simulation period for each of the design objects DO1, DO2, ..., DOi except the black box block. .., I (DOi) and output values O (DO1), O (DO2), ..., O (DOi) are dumped and stored, respectively, and the process proceeds to step S404. In step S404, the state information storage interval or a storage time point is set, and the flow proceeds to step S406. In the step S406, the simulation of each design object is performed in parallel using the input information of each design object stored in the step S402, and at the same time, the state information of all the design objects except the black box blocks is periodically spaced. Or at one or more specific simulation time points and proceeds to step S408. In step S408, I (DO1), I (DO2), ..., I (DOi) obtained in step S402 and state information of each of the design objects DO1, DO2, ..., DOi obtained in step S406. From the state information S (t1), S (t2), ..., S (tn) and input information I (t0), I (t1), I (t2), ..., I (tn) Proceed to step S410. In step S410, the DUV to which the additional code is added is used, and the state information S (t1), S (t2), ..., S (tn) and the input information I (t0) and I (t1) generated in step S408 are used. Output values for the design objects in the DUV while simulating all DO_t design objects in the DUV in each time interval except the black box block using, I (t2), ..., I (tn) These results are compared with the output values for the design objects existing in the t-VP stored in step S404, and the simulation is terminated at the point when these two results are different or at the end of the simulation.

FIG. 11 is a flowchart schematically showing another process of quickly performing a design verification for a DUV using the apparatus as shown in FIG. 2 and using the simulation result of t-VP.

In operation S500, all input values I (DO1) and I (DO2) for one or more design objects DO1, DO2, ..., DOi of the hierarchical structure existing in the t-VP during the t-VP simulation are performed. ), ..., I (DOi) and all output values O (DO1), O (DO2), ..., O (DOi) can also be dumped and stored in the entire simulation section to save the original t-VP. Adding additional code to the design code or automatically generating the s-VP from the DUV, and additionally adding the additional code to the design code of the DUV so that a simulation can be performed in parallel later on, in step S502. Proceed to In step S502, while the t-VP is simulated, the input values and output values are dumped and stored for each of one or more design objects of the hierarchical structure existing in the t-VP in the entire simulation section, and the flow proceeds to step S504. . In step S504, the state information storage interval or a storage time point is set, and the flow proceeds to step S506. In step S506, the simulation of each design object is performed in parallel using the input information of each design object stored in step S502, and at the same time, the state information of all the design objects except the black box blocks is set at a predetermined interval. At least one specific simulation time point is stored and the process proceeds to step S508. In step S508, I (DO1), I (DO2), ..., I (DOi) obtained in step S502, and state information of each of the design objects DO1, DO2, ..., DOi obtained in step S506. From the state information S (t1), S (t2), ..., S (tn) and input information I (t0), I (t1), I (t2), ..., I (tn) Proceed to step S510. In step S510, the DUV to which the additional code is added and the status information S (t1), S (t2), ..., S (tn) and the input information I (t0), I (t1), I generated in step S508 Using the (t2), ..., I (tn) and the i-th simulator using the i-th simulator from the simulation point O to ti point the simulation for the entire black box blocks in the DUV only dumped in step S502 Proceed with inputs to the entire box blocks, ensure that all design objects except the black box blocks in the DUV at ti have the state information obtained in step S508, and from ti, the simulation of the entire DUV is performed in parallel. You will then proceed and finish the simulation.

FIG. 12 schematically illustrates an example of a process of automatically generating an s-VP such as (c) using the results of an analytical process such as (b) from a circle design code such as (a). to be.

As described above, the purpose of the verification apparatus and the design verification method using the same according to the present invention is to quickly perform the verification of the DUV by utilizing the results of the simulation using VP when performing the super scale design based on ESL. By doing so, it is possible to drastically shorten the overall design verification time and greatly increase the efficiency of verification.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

Claims (35)

A design verification device having a VP, verification software and at least one simulator, The verification software adds additional code or additional circuitry to the VP and adds additional code or additional circuitry in an automated fashion to the design code or synthetically generated gate-level netlist that includes the DUV, leading to simulation using VP. One or more simulations performed after the first simulation, which is a post-simulation step for one or more design objects in the DUV while performing the first-order simulation, which is a step-wise simulation. The minimum information necessary to allow simulations to be performed on one or more design objects in the list can be automatically collected in the first simulation step, the first simulation step, and the first simulation step, the first step, using VP. Remind simulation Design verification device that performs quickly while collecting minimal information and quickly performs one or more simulations after the first stage, which is the post-simulation step targeting one or more design objects existing in the DUV using the collected information. . A design verification apparatus having verification software and at least one simulator, The verification software generates the VP from the DUV in an automated manner and adds additional code or additional circuitry in an automated manner to the design code or synthetically generated gate-level netlist that includes the DUV, thereby generating the VP. One or more simulations that are performed after the first stage simulation, which is the first stage simulation targeting the one or more design objects in the DUV while performing the first stage simulation using the first stage simulation, are generated by simulation intervals, design codes, or synthesis. The minimum information necessary to allow simulations to be performed on one or more design objects in the gate-level netlist is automatically collected in the first simulation step, the first simulation step. Step The first simulation is performed quickly while collecting the minimum information, and the collected information is used to quickly perform one or more simulations after the first stage, which is the post-simulation step for one or more design objects present in the DUV. Design verification device to perform. In the design verification method of performing the simulation several times with multiple test benches to locate and correct one or more design errors in the gate-level netlist generated by the design code or synthesis, Each one of the simulations in the above several simulations consists of one or more simulations after the first stage, which is the first stage simulation using VP and the subsequent stage simulation using one or more design objects in the DUV. A gate-level netlist generated by simulation sections, design codes, or synthesis of one or more simulations after the first stage of the first stage simulation using the VP while performing the first stage simulation using the VP. Validate additional code or additional circuitry in the VP to automatically collect the minimum information necessary to allow simulations to be performed on one or more design objects present in the first simulation phase, the first simulation step using the VP. And add it in an automated manner and quickly perform a first-order simulation, using the VP, with the minimal information collected, and use the collected information for one or more design objects in the DUV. Verification method that allows one or more simulations to be performed quickly after the first stage, which is the post-simulation stage. The method according to claim 1 or 2 or 3, At least one design object in the DUV includes the entire DUV. The method according to claim 1 or 2 or 3, At least one design object in the DUV is a design object excluding black box blocks in the DUV. The method of claim 3, wherein Verification method for automatically generating VP using the verification software. The method according to claim 1 or 2 or 3, A verification method in which the minimum information collected in the first simulation, the preceding simulation step using the VP, includes state information and input information of the DUV The method according to claim 1 or 2 or 3, Verification method including the state information and input information of at least one design object existing in the DUV is the minimum information collected in the first simulation, the preceding simulation step using the VP The method according to claim 1 or 2 or 3, Verification method including the state information and input information of the design objects excluding the black box blocks existing in the DUV is the minimum information collected in the first simulation, the previous simulation step using the VP The method according to claim 1 or 2 or 3, One or more simulations after the first stage of the post-simulation step are performed in parallel using two or more simulators. The method according to claim 1 or 2 or 3, The results of the first simulation using the VP and the first and subsequent simulation results for the one or more design objects of the DUV are compared in real time during the subsequent simulation, and the results of the two simulations are different from each other. Validation method to stop the post simulation and proceed with debugging to find the cause of the difference The method according to claim 1, 2, or 3, 5, 9, 10, 11, or 25, In the post-simulation step, the simulation for the DUV is composed of three processes. From the first process, only the black box blocks in the DUV are from simulation time 0 to one or more simulation time points ts in which state information is stored for the VP in the preceding simulation. The remaining design objects of the DUV, except the black box blocks, are disabled so that they are not executed. In the second process, at the time ts in the previous simulation process using VP, the state of the remaining design objects of the DUV is disabled. Verification method using the collected state information S (ts) to perform the state setting, and then perform the simulation for the entire DUV from the time point ts onwards in the third process The method of claim 12, In the first step of the above-described three processes, the remaining design objects of the DUV except the black box blocks are disabled so that all the inputs of the remaining design objects of the DUV are removed from the HDL simulator. Use the force command to fix the event to the time ts, either by removing the event generation until the time ts, or by adding additional code to the DUV, the event is input to all inputs of the remaining design objects of the DUV. Verification method to prevent The method of claim 12, One or more simulation time points ts storing state information for the VP are two or more time points, and thus, the state information S (ts) collected at these time points is also two or more times, so that each of them is parallel with two or more simulators. Verification method The method according to claim 1 or 2 or 3, A verification method in which the minimum information collected in the first simulation, which is the preceding simulation step using the VP, includes the state information of the DUV The method according to claim 1 or 2 or 3, The verification method including the state information of one or more design objects existing in the DUV is the minimum information collected in the first simulation step that is the preceding simulation step using the VP The method according to claim 1 or 2 or 3, The verification method including the state information of the design objects excluding the black box blocks existing in the DUV is the minimum information collected in the first simulation, the previous simulation step using the VP The method according to claim 1 or 2 or 3, And the simulator is an HDL simulator. The method according to claim 1 or 2 or 3, And the VP is modeled as SystemC, C ++ or C. The method according to claim 1 or 2 or 3, And the VP is modeled at the level of abstraction with transaction accuracy. The method according to claim 1 or 2 or 3, A verification method modeled at the abstraction level at which the VP has cycle accuracy, The method according to claim 1 or 2 or 3, A verification method modeled at the abstraction level with the VP having event accuracy, The method according to claim 1 or 2 or 3, And wherein the VP is modeled at a higher level of abstraction than the RTL level, and wherein the DUV is dictated at the RTL level. The method according to claim 1 or 2 or 3, The verification method including the input information of one or more design objects existing in the DUV is the minimum information collected in the first simulation, the preceding simulation step using the VP The method of claim 24, One or more independent design objects below the DO1, DO2, which exist in the hierarchy of the VP in the process of performing the front end simulation using the VP as the minimum information collected in the first simulation step, the front end simulation using the VP. Probe and store all inputs I (DO1), I (DO2),.,., I (DOi) in each of the .i., DOi, and hierarchical structure of VP in the post simulation for DUV. Independent design objects existing in DO1, DO2, ..., DOi and DUV in each of the same design objects DO1, DO2, ..., DOi are stored in the previous simulation process I (DO1) The design objects of the DUV in the process of executing the simulation independently using sequential or I (DO2), ..., I (DOi) using two or more computers equipped with two or more HDL simulators. DO1, DO2, ..., After storing the state information for each of the design objects DO1, DO2, ..., DOi of the DUV at one or more identical simulation time points t1, t2, ..., tn for each DOi, the DUV at each simulation time point. The status information S (ts) (s = 1, 2, ..., n) of the largest design object DO_t of DUV is obtained by integrating the status information of each of DO1, DO2, ..., DOi design objects of Later, these methods are used to verify the DUV's largest design object DO_t by using two or more simulators in parallel or sequential simulation for specific simulation intervals to reduce the simulation time for the DUV. The method of claim 25, One or more independent design objects below the DO1, DO2, which exist in the hierarchy of the VP in the process of performing the front end simulation using the VP as the minimum information collected in the first simulation step, the front end simulation using the VP. Validation method that probes all inputs I (DO1), I (DO2), ..., I (DOi) existing in each of DO. The method of claim 25, One or more independent design objects DO1, DO2, which are lower in the hierarchy of the VP in the process of performing the front end simulation using the VP as the minimum information collected in the first simulation step, the front end simulation using the VP. Validation method for cycle-based probing of all inputs I (DO1), I (DO2), ..., I (DOi) present in each of .., DOi The method of claim 25, One or more independent design objects below the DO1, DO2, which exist in the hierarchy of the VP in the process of performing the front end simulation using the VP as the minimum information collected in the first simulation step, the front end simulation using the VP. Verification method that probes all inputs I (DO1), I (DO2), ..., I (DOi) existing in each of DO. The method according to claim 3 or 6, The method for automatically generating the VP analyzes the original design code for the DUV, finds all the variables or signals for which the flip-flop or latch is generated through logic synthesis in the original design code, and finds the specific flip-flop of all the flip-flops or latches. Alternatively, the variable or signal corresponding to the output of the latch is expressed only as variables or signals corresponding to the inputs of the DUV and the outputs of other flip-flops or other latches, and if there are temporary main inputs. The variables or signals corresponding to each of the specific flip-flops or latches of all the timing inputs of the flip-flops or latches are input power of the DUV, the outputs of the flip-flops or latches, and the temporary main inputs are present. Verification method including the process of expressing only variables or signals corresponding to temporary injection forces The method according to claim 3 or 6, The method for automatically generating the VP analyzes the original design code for the DUV, finds all the variables or signals for which the flip-flop or latch is generated through logic synthesis in the original design code, and finds the specific flip-flop of all the flip-flops or latches. Alternatively, if a variable or signal corresponding to the output of the latch is present in the DUV's injection forces, other flip-flops or the outputs of the other latches, and the temporary inputs are present, the variables or signals corresponding to the temporary inputs are used. And the variables or signals corresponding to each of the particular flip-flops or latches of all timing inputs of the flip-flops or latches are the injection forces of the DUV, the outputs of the flip-flops or latches, and the temporary main inputs. The verification method includes a process of expressing using variables or signals corresponding to temporary main inputs. The method of claim 29 or 30, All variables or signals corresponding to the flip-flop or latch found by analyzing the original design code for the DUV are grouped into one or more groups having the same clock input or the same enable input, and the VP is performed based on the grouping. Method to speed up VP performance by partially performing cycle-based The method of claim 29 or 30, All variables or signals corresponding to the flip-flop or latch found by analyzing the original design code for the DUV are grouped into one or more groups having the same clock input or the same enable input, and the VP is performed based on the grouping. Method to speed up the performance of VP by executing PAR in parallel in distributed environment The method according to claim 1 or 2 or 3, Validation method with VP modeled to have event accuracy in part and cycle accuracy in all others. The method according to claim 1 or 2 or 3, Verification method using VP modeled to be partially cycle accurate and transaction accuracy in all others. The method according to claim 1 or 2 or 3, Validation method using VP modeled to have event accuracy in part, cycle accuracy in another part, and transaction accuracy in the other part.

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