KR20080096723A - Distributed parallel simulation method based on adaptive synchronization/communication scheme - Google Patents

Abstract

A dispersion parallel simulation method by the variable synchronization/communication method are provided to improve the dispersion parallel simulation speed by effectively reducing synchronization overhead and communication overhead. A dispersion parallel simulation is performed by variably changing communication/synchronization point which controls the dispersion parallel simulation. The dispersion parallel simulation uses the future synchronous point prediction method based on experience to present, and the method for progressing as the variable interval. Through the simulation result, communication overhead, or synchronization overhead is minimized. Therefore, the dispersion parallel simulation speed is gradually improved.

Description

Distributed Parallel Simulation Method Based on Variable Synchronization / Communication Scheme {Adtributed Parallel Simulation Method Based on Adaptive Synchronization / Communication Scheme}

1 schematically illustrates some examples of logical connection structure schemes of two or more local computers installed in two or more computers for simulation of a distributed processing parallel execution scheme in the present patent.

2 is a diagram schematically illustrating an example of a distributed parallel simulation environment in which distributed parallel simulation is configured using two or more computers and two or more HDL simulators installed in these computers.

3 is a schematic illustration of an example of an overall flow chart of a typical distributed parallel simulation.

<Description of the symbols for the main parts of the drawings>

32: Verification Software 34: HDL Simulator

35: computer

62: additional code added to the design code to be verified by the verification software

64: Communication and Synchronization Module for Distributed Parallel Simulation

333: Local simulations of distributed parallel simulation

SW server module in the central computer that performs the connection of control and local simulations

343: Simulator for Local Simulation in Distributed Parallel Simulation Environment

353: central computer

354: Outer Computer

644: Local Simulation Run-Time Module for Distributed Parallel Simulation

646: communication and synchronization module for simulation acceleration

648 Hardware-based Verification Platform

650 simulation acceleration runtime module

660: Installation in a model that is split to be performed on the local simulator in distributed parallel simulation.

Object

670: VPI / PLI / FLI

674: Socket API

676: TCP / IP socket

678: Device API

680: Device Driver

682: Hardware Abstraction Layer (HAL)

684: Giga-bit LAN card

The present invention relates to a technique for systematically verifying a design from an electronic system level (abbreviated to ESL) to a gate level by using a simulation. In this case, the present invention relates to a verification method which increases the performance and efficiency of verification. In semiconductor design verification, simulation is a computer-executable model that is software-based under design (DUV) or one or more design objects in a DUV (defined later) and the test bench that drives it. The computer-implemented model is converted into a sequence of machine instructions of a computer through a simulation compilation process and executed using a computer. Therefore, the execution of the simulation is basically performed through the sequential execution of the machine language of the computer, and at present various simulation techniques (event-driven simulation, cycle-based simulation). simulation, compiled simulation, interpreted simulation, co-simulation, etc. exist. That is, simulation means design objects that are designed or implemented as appropriate abstraction levels (abstraction level, semiconductor transfer design, gate-level, register transfer-level, transaction-level, architecture-level, behavior-level, algorithm-level, etc.). Various processes that simulate the operating function or operation characteristics of the corresponding design object on the computer through software modeling through the modeling process in various levels of abstraction) It is. The advantage of such simulation is that it is possible not only to predict virtually the operation function or operation characteristics of the design object before implementing it physically, but also provide high flexibility in software. The disadvantage is that the simulation is finally performed through the sequential execution of the machine languages, so that the complexity of the design object to be simulated is large. Present), the simulation is very slow (for example, if the 100 million-gate design is performed by event-driven simulation, the simulation speed is 1 cycle / sec and about 3.2 years if the simulation is to be performed 100,000,000 cycles). Is required). Therefore, simulation in this patent refers to all methods of software modeling one or more design objects in a DUV or DUV at an appropriate level of abstraction and executing them in software. More specifically, the behavior of a particular level of abstraction of a DUV or one or more design objects within a DUV ultimately defines a particular computer data structure and certain operations on that particular data structure. Process to make it computer-executable and to operate the computer with input values applied thereto or to include a series of computations or processing in the computer as input values. If it is defined as a simulation, it is defined as a simulation (So, if the process meets the definition as well as the simulation using a commercial simulator, the simulation is performed on the computer through the simulation by the self-made simulator and the modeling through the same process as the simulation process.If a software process which is normally carried out will be both defined by simulation).

With the recent rapid development of integrated circuit (IC) and semiconductor process technology, the scale of digital circuit or digital system design has grown from at least tens of millions of gates to hundreds of millions of gates. It is a trend, and this trend is continuously expanding. In particular, the recent system-class integrated circuits, commonly referred to as SOCs (System On Chip), are mostly embedded with at least one processor core (RISC core or DSP core, for example, ARM11 ARM or CEVA Teak DSP core). A great deal of functionality is being implemented in software. And competition in the market is fierce, so it is necessary to develop a superior product in a short time, and shortening the design period has become a very important factor in determining the success of the product. Therefore, in recent chip design, the ESL design technique is attracting much attention from the industry as a new design method. Chips designed with ESL design techniques that have higher abstraction levels (described later) than the Register Transfer Level (RTL) design techniques that have been used in traditional digital hardware designs are used in addition to the chip design. The development of the running software must also be carried out at the same time. Therefore, in order to proceed with software development at the same time as designing hardware, architecture exploration is made by system level model (ESL model) by creating virtual platform (hereinafter referred to as VP) modeling the hardware. ), Software development, hardware / software co-verification, and system verification are recent trends, which serve as an executable specification (i.e. the role of a reference model). ). Such VPs can be created quickly by increasing the level of abstraction, as well as creating a VP for the DUV before designing a viable DUV. Verification can be done in advance, which is advantageous in many ways. Such VPs play an important role in platform-based design (PBS), which is common in current SOC design methods. VPs are typically on-chip buses at the transaction level. ) Is a core component of the bus model (modeled at the transaction level, called the TLM model) modeled according to the specified bus protocol, and the transaction level of the design blocks connected to this bus. By designing these transaction level design blocks to communicate with the bus model according to the abstracted bus protocol, the simulation performance is relatively high (approximately 100 times -10,000 times compared to that of the RTL model). Make it possible. Currently, commercial tools for creating and executing such VP include ARM MaxSim, CoWare ConvergenSC, Cadence Insicive, Summit Design VisualElite, Vast Systems Technology VSP, Synopsys SystemStudio, TenisonEDA VTOC, Carbon Design Systems VSP, Virutech's VirtualPlatform. In SOC design, the VP is fast enough to develop software, so it is important not to model at the register transfer level (RTL) using languages such as Verilog or VHDL, but to use languages such as C / C ++ or SystemC. Therefore, the model is modeled at the transaction level or algorithm level, which has a higher level of abstraction than RTL. Abstraction level, a very important concept in system design, expresses the degree of dictation of the dictation of the design object (described later). It can be divided into level, transistor-level, gate-level, register transfer-level (RTL), transaction level, and algorithm level. That is, the gate-level has a lower level of abstraction than the RTL, the RTL level has a lower level of abstraction than the transaction level, and the transaction level has a lower level of abstraction than the algorithm level. Therefore, if the level of abstraction of a specific design object A is a transaction, and the design object B expressed in detail is RTL, the design object A is defined as having a higher level of abstraction than the design object B. In addition, if design object X has design object A and design object C inside, and design object Y has design object B and design object C incorporating A inside, design object X is more abstract than design object Y. It is defined as high. In addition, depending on how much more accurate the latency model is at the same gate level or the same RTL, it is possible to determine the high and low level of abstraction. In other words, the accurate latency model is said to have a low level of abstraction. For example, even if the gate level is the same, the netlist of the zero-delay model is better than the netlist of the unit-delay model. The level of abstraction is high, and the netlist of unit time model is higher than the netlist of full-timing model using SDF (Standard Delay Format). Recent SOC design defines the object to be finally implemented in the chip as the initial design object, which targets the initial design object from the initial abstraction level (e.g. transaction level) through the progressive refinement process. It can be defined as the process of shaping to the last level of abstraction (eg gate-level) (see FIG. 14). The design technique through progressive refinement process is the only design technique that can cope with the design complexity of the recent SOC with the platform-based design. It proceeds through. The core of the design technique through the gradual materialization process is to refine the design blocks existing in the design object MODEL_DUV (HIGH) modeled at the upper level of abstraction step by step to designate the design object MODEL_DUV (LOW) modeled at the lower level of abstraction than MODEL_DUV (HIGH). It can be summarized as a process obtained by using an automated method (eg, a logic synthesis or a higher level synthesis) or by a manual method or a mixture of an automated method and a manual method. As an example of this, first of all, the process of obtaining an RTL model that can be implemented from an ESL model, which is an embodiment of ESL to RTL (this process is currently performed manually or in a high-level synthesis method or a mixture thereof), is performed using the MODEL_DUV ( HIGH), and the implementable RTL model becomes MODEL_DUV (LOW), and the process of obtaining the gate-level model (ie, gate-level netlist) from the implementable RTL model, which is the step of specifying from the RTL to the gate level again ( This process is now mostly done in a logic synthesis method), and the RTL model that can be implemented becomes MODEL_DUV (HIGH) and the gate level model becomes MODEL_DUV (LOW). This gate-level model is a timing-accurate gate-level model by back-annotating the delay information (represented in Standard Delay Format) extracted during the placement and routing process. Unless otherwise defined, it includes both DUV (described later as Design Under Verification) and TB (described later as Test Bench).

One thing to note here is that not all design objects within the ESL model must exist at the system level, even for the ESL model, and all design objects within the RTL model must exist at the register transfer level, even for the RTL model. It is not. That is, even in the ESL model, a small number of design objects within this model exist at the register transfer level and are wrapped at the system level by wrapping these design objects in a wrapper for abstraction. It can be treated as an ESL model by matching the model, and even though it is an RTL model, a few of the design objects inside this model can be treated as RTL models like many other design objects that exist at the gate level but exist at the RTL level. have. For the same reason, in the GL model, a small number of design objects (e.g. memory blocks that do not generate gate-level netlists in logical synthesis) may exist at the register transfer level. Therefore, the term "specific abstraction level model" in this patent refers to the various abstraction levels (ESL, RTL, GL abstraction levels as well as their mixed forms of abstraction levels, ESL / RTL, which may exist in the process of gradual materialization from ESL to GL). Abstraction levels, including mixed abstraction level, RTL / GL mixed abstraction level, ESL / RTL / GL mixed abstraction level, etc.). The general term “abstraction level” refers to the various levels of abstraction that can exist in the gradual materialization process, from ESL to RTL and GL as well as from ESL to GL (eg, ESL / RTL mixed abstraction level, RTL / GL mixed abstraction). Levels, ESL / RTL / GL mixed abstraction levels, etc.). For example, four design objects A, B, C, and D exist as submodules inside the DUV, where A and B are dictated at ESL, C at RTL, and D at the GL abstraction level. Even with a mixed level abstraction level model, this DUV can be referred to as a model of a specific level of abstraction (as well as specifically referring to ESL / RTL / GL as a mixed level of abstraction model). In the future, in the case of a model having a mixed level of abstraction, when it is necessary to clearly state that the abstraction level is a mixed form, it will be referred to as an abstract upper / lower mixed level model or an abstract mixed level model.

Transaction, which is an important concept in ESL, corresponds to the RTL signal or pin, and the information represented on the signal or pin can only be expressed as bit or bit vector, whereas transaction is logical. It refers to information represented by defining a plurality of related signals or pins as a unit, and the transfer of information uses a function call. For example, a logical association between a total of (N + M + P) signals consisting of an address signal N-bit, a data signal M-bit, and a control signal P-bit that always exist in a design consisting of any processor module and any memory module. N-bit address bus, M-bit data bus, and P-bit control bus, each cycle consists of (N + M + P) bitvectors. ), DATA (data_value)), or WRITE (ADDR (address_value), DATA (data_value)), or READ-WAIT (ADDR (address_value), DATA (data_value)), or WRITE-WAIT (ADDR (address_value), DATA ( data_value)), and the like, as a symbol that can be interpreted as meaning. Such a thing is called a transaction. Transactions can also be defined not only in one cycle unit (this is called a cycle-accurate transaction, abbreviated as a ca-transaction), and extend to multiple cycle units as well. The transaction is defined as a transaction (which is called by several names such as a timed transaction, a cycle-count transaction, or a PV-T transaction), and in this patent, abbreviated as a single name as a timed-transaction. (A timed-transaction defined in multiple cycles can be expressed as Transaction_name (start_time, end_time, other_attributes)). Transactions also include transactions without time concepts (abbreviated as untimed-transactions). In fact, there is no standardized and consistent definition of transactions, but it is most common to divide them into untimed-transactions, timed-transactions and ca-transactions as described above. As such, even within a transaction, the level of abstraction is highest depending on the level of abstraction, but the time accuracy is lowest, from the untimed transaction with the lowest level of abstraction, but the highest level of time accuracy is ca-transaction, and the level of abstraction and time accuracy The intermediate level can be divided into timed transactions.

The materialization process takes place in a progressive manner so that transaction-level design objects in the VP are at least bit-level cycle-accurate RTL-level design objects through the conversion process for specification. Will change to At the end of this conversion process, all transaction-level design objects in the VP are transformed into RTL-level design objects (and thus converted into an RTL model that can be implemented as a transaction-level VP). In addition, RTL-level design objects in the feasible RTL model are converted to bit-level timing-accurate gate-level design objects through the conversion process for concrete specification. At the end of this conversion process, all RTL-level design objects in the RTL model are converted to gate-level design objects (and thus the RTL model is converted to a gate-level model). Figure 14 shows this process as an example. If you have four transaction-level design objects DO_esl_1, DO_esl_2, DO_esl_3, and DO_esl_4 as sub-blocks within the transaction-level DUV (ESL), these four transaction-level design objects go through the step-by-step gradual refinement process. The design objects of DO_rtl_1, DO_rtl_2, DO_rtl_3, and DO_rtl_4 are replaced with the register transfer level DUV (RTL) consisting of only RTL-level design objects DO_rtl_1, DO_rtl_2, DO_rtl_3, and DO_rtl_4. Also, if there are four design objects DO_rtl_1, DO_rtl_2, DO_rtl_3, and DO_rtl_4 as lower blocks in the register transfer level DUV (RTL), these four RTL design objects undergo a step-by-step gradual specification process to allow gate-level design objects DO_gl_1, It is replaced by DO_gl_2, DO_gl_3, and DO_gl_4, and eventually converted to gate-level DUV (GL) consisting of only gate-level design objects DO_gl_1, DO_gl_2, DO_gl_3, and DO_gl_4.

In SOC design, there are two things that need to be designed, one is Design Under Verification (DUV), and the other is a testbench for simulating DUV (abbreviated as TB). The DUV is the design target ultimately made into a chip through the semiconductor manufacturing process, and the testbench is used to simulate the DUV by modeling the ambient conditions in which the chip is implemented. When simulating a DUV, it is common for the testbench to apply an input to the DUV and accept and process the output from the DUV with the authorized input. These DUVs and testbenches typically have a hierarchical structure with one or more submodules inside them, each of which can be called a design block, with design modules inside the design block, and a submodule inside the design module. Modules exist. Such design blocks, or design modules, or submodules or DUVs, and test benches, respectively, or in part, or combinations thereof, or portions of combinations thereof, are all referred to herein as design objects (specific examples In the case of Verilog, module, VHDL entity, and SystemC sc_module are all examples of design objects). Thus, a VP may also be regarded as one of the design objects, and a part of the VP, one or more design blocks in the VP, a part of the design blocks, the design modules in the block, the parts thereof, or the submodules in the design module All of the parts of the can be viewed as design objects (ie, all of the DUV and TB or any part of the DUT and TB can be seen as design objects).

However, in the current gradual concrete design, the verification at the upper abstraction level can be performed very quickly, but the verification at the lower level of abstraction is performed relatively slowly. There is a problem that the speed is greatly reduced. In general, a single simulation method (a single simulation method is defined in this patent in a broad sense, not only when using one simulator but also when using two or more simulators (for example, using Verilog simulator and Vera simulator simultaneously). In contrast to defining two or more simulators on a single CPU as a single simulation method, there is a method of executing two or more simulators in a distributed parallel manner to increase the verification speed. Examples of this simulator include HDL (Hardware Description Language, NC-Verilog / Verilog-XL and X-sim from Cadence, VCS from Synopsys, ModelSim from Mentor, Riviera / Active-HDL from Aldec, and FinSim from Fintronic) Or HVL (Hardware Verification Language, Cadence's e simulator, Synopsys' Vera simulator, etc.) simulator, or SDL (System Description Language, SystemC simulator, Cadence's Incisive simulator, etc.) simulators. Another distinction is the event-driven simulator or the cycle-based simulators, the simulators of which are mentioned in this patent. Thus, in the case of using two or more simulators, it is possible not only to use any kind of simulators mentioned above, but also to freely use these different kinds of simulators. Distributed parallel simulation (also called parallel distributed simulation or simply parallel simulation, which is referred to in this patent as distributed parallel simulation), which is a distributed processing method of simulation. In the most common parallel simulation method, DUV and TB (ie, a model of a certain level of abstraction) to be simulated are divided into two or more design objects, and each of these divided design objects is distributed and executed in a separate simulator. 5). Therefore, for distributed parallel simulation, a partitioning process is needed to divide the model to be simulated into two or more design objects. Therefore, in this patent, a design object to be performed in a specific local simulation (to be defined later) through a division process will be referred to as a local design object.

Recently, two or more computers are connected by a high-speed computer network such as Gigabit Ethernet, and a simulator is performed on each of them (in this patent, simulations performed in each simulator of two or more simulators that enable these distributed parallel simulations) are performed. Multiprocessor computers (eg, Pentium dual-core chips and AMD dual-core chips are called local simulations and are referred to as local simulators), or are equipped with two or more central processing units (CPUs). It is also possible to configure a multiprocessor computer, and to perform a distributed parallel simulation by running a simulator on each of these CPUs in a multiprocessor computer with multiple CPU chips mounted on one or more system boards. end It is. However, such a conventional distributed parallel simulation has a problem in that the performance improvement is very limited due to the communication overhead and synchronization overhead between the simulators. There are two main methods of synchronization in distributed parallel simulations: one is conservative (also called pessimistic) and the other is optimistic. The conservative synchronization is that the causality relation of simulation events is maintained between simulators, so no rollback is required, but distributed parallel simulation is limited to the slowest local simulation. There is a problem of excessive synchronization, and optimistic synchronization can prevent causality between simulation events temporarily between simulators, and rollbacks are required to correct them, so reducing the total number of rollbacks is distributed parallel simulation. Will have a big impact on performance. However, up to now, distributed parallel simulations by optimistic methods have excessive rollbacks because the simulation points in which each local simulation proceeds without synchronization with other local simulations are not specially considered to minimize the rollback. This results in significant consequences for the overall simulation. Since the conventional optimistic distributed parallel simulation or the conservative distributed parallel simulation method and the implementation method thereof are well known in the literature or the literature, detailed description thereof will be omitted. One more thing to mention is that the number of processors performing distributed parallel simulations should be equal to the number of local simulations in order to maximize the performance of distributed parallel simulations. If a networked or multiprocessor computer has more than two processors), even if the number of local simulations is more than two, two or more local simulations can be performed by one processor. In conclusion, both the current conservative synchronization method and the communication method, or the optimistic synchronization method and the communication method have a problem of significantly reducing the performance of distributed parallel simulation using two or more simulators.

In addition, it is very important that the high-level abstraction model serves as a reference model of the low-level abstraction model in the design through the gradual materialization process. It is necessary to maintain model consistency between the model and the low-level model. However, there are no effective ways to maintain model coherence between two or more models present at these different levels of abstraction in current incremental refinement methods.

In addition, the debugging process for removing design errors found in the design process through a gradual materialization process is very time consuming because the system is not systematic.

It is an object of the present invention to provide a method of speeding up distributed parallel simulation by effectively reducing synchronization overhead and communication overhead in distributed parallel simulation.

In order to achieve the above objects, the design verification apparatus necessary for applying the design verification method according to the present invention may be composed of one or two or more computers in which verification software and one or two or more simulators are installed. Another design verification apparatus to which the design verification method of the present invention can be applied includes one or more computers including verification software and one or more simulators, and one or two simulation accelerators connected to the one or more computers. It consists of an FPGA board. The verification software runs on a computer, and if there are two or more computers in the design verification device, these two or more computers are connected by a network (e.g. Ethernet or Gigabit Ethernet) to network the movement of files or data between the computers. Enabled through The one or more simulators for design verification use consist only of event-driven simulators (Parallel Discrete Event Simulation (PDES) for parallel simulation by configuring distributed parallel simulations only of event-driven simulators). It can be a combination of an event-driven simulator and a cycle-based simulator, or it can consist of only a cycle-based simulator, or a cycle-based and transaction-based simulator. It can be configured as a "based simulator", or as a transaction simulator only, or as an event-driven and transaction-based simulator, or as an event-driven simulator and a cycle-based simulator. Get together with a transaction-based simulator It may be such that the configuration of the simulator according to the present patent can be configured in a wide variety of ways. Therefore, when the two or more simulators are composed of an event-driven simulator and a cycle-based simulator, the distributed parallel simulation using the same is partially performed in the event-driven simulation and the other part is performed in the cycle-based simulation. Proceed to co-simulation mode. Alternatively, when the two or more simulators are composed of an event-driven simulator, a cycle-based simulator, and a transaction-based simulator, distributed parallel simulation using the same is partially performed as an event-driven simulation method, and the other part is a cycle-based simulation method. The other part can also be run in the co-simulation mode, which proceeds in a transaction-based simulation manner.

In Patent 10-2006-92574 and PCT / KR2006 / 004059, the angles of distributed parallel simulation are obtained by using the predictive input and the predicted output obtained from the simulation result using the abstraction high-level model or the simulation result performed before the design change or the abstraction high-level model. We proposed a simulation method to minimize the communication overhead and synchronization overhead of local simulation. However, such a simulation method requires an expected input and an expected output, and therefore, a simulation using an abstract high-level model or a simulation or abstract high-level model before a design change must be performed in advance. Therefore, in this patent, the communication overhead or synchronization overhead in simulations or conventional distributed parallel simulations necessary for obtaining the expected inputs and expected outputs of the distributed parallelism simulation proposed in Patent 10-2006-92574 and PCT / KR2006 / 004059 We propose a new distributed parallel simulation method that can be minimized.

In the distributed parallel simulation method of the present invention, as the simulation proceeds, the synchronization point at which each local simulation synchronizes with other local simulations is dynamically determined during the simulation process. Specifically, each local simulation Sl (j) of distributed parallel simulation at the current simulation point Ti is the next event that will come to itself in other local simulations (i.e. this event is the local design object from the local design objects performed in other local simulations). This is the input event coming into the local design object performed in the simulation Sl (j). When Tn occurs from the current time Ti to the present time (i.e., simulation time 0 to Ti), the interval of all events sent by the corresponding local simulation. The interval is defined as a point in time that is further advanced by the shortest time n (which is referred to as "external event minimum interval" in this patent) among the previous events) and assumes Tn as Ti + n (this assumption Is at the current time Ti). This local time is different from Tn and local simulation Sl (j). The next event that should go to the migrations (that is, this event is an output event from the local design object performed in the local simulation Sl (j) to another local simulation). This is to estimate the time as the synchronization point Te and proceed with the local simulation (that is, the next expected synchronization point Te after Ti becomes min (Ti + n, To). It is not necessary to proceed to To, ie, when To arrives in the process of advancing local simulation time from Ti to Ti + n first, Te becomes To, and in this time advancement process, Ti + n before reaching To. Is reached, Te becomes Ti + n). If this assumption is wrong during the actual simulation, the actual synchronization point Ts will be in the past in time rather than min (Ti + n, To), making roll-back similar to an optimistic distributed parallel simulation. (I.e. rollback to a checkpoint point equal to or in the past Ts, and synchronize when the simulation time reaches Ts). To this end, each local simulation of distributed parallel simulation in this patent performs a checkpoint at one or more points of time during the simulation, so that a rollback can be performed when necessary. However, in the present patent, not only the checkpoint may be periodically performed, but also it may be variably performed by increasing or decreasing the checkpoint interval as the simulation time progresses. This dynamic change in checkpoint interval minimizes the simulation overhead for the checkpoint.

As described above, the distributed parallel simulation method proposed by the present patent will be described in detail through an example. In order to simplify the situation, it is assumed that the local simulation is 2. In a distributed parallel simulation consisting of local simulation A and local simulation B, it is assumed that events transmitted from local simulation A to local simulation B proceed at simulation time 0, 10, 20, 35, 45, 50, 60, 70, and local simulation Suppose that events from B to local simulation A go through simulation times 10, 20, 30, 40, 45, 50, 60, 65, and 75. In such a case, the synchronization timing between local simulations is dynamically determined in the distributed parallel simulation method of the present patent as follows.

First of all, when Ti = 0, local simulation A becomes To = 10 at the next synchronization time point and Te = 10 since n = 0 since it has never been passed from B to A, and To is at the next synchronization time point in local simulation B as well. = 10 and never passed from A to B, where n = 0, and Te = 10 (in this case, Ts is actually 10, so no rollback occurs).

In the case of Ti = 10, the local simulation A is Te = 20 with To = 20 and n = 10 at the next synchronization point, and Te = 20 with To = 20 and n = 10 at the next synchronization point in Local Simulation B as well. 20 (in this case, Ts is also 20, so no rollback occurs).

In the case of Ti = 20, local simulation A becomes Te = 30 with To = 35 and n = 10 at the next synchronization time point (in this case, local simulation A already knows that n = 10 when Ti = 20). Even though To is 35, synchronization is performed at simulation time 30 without progressing to simulation time 35), and in local simulation B, Te = 30 as To = 30 and n = 10 at the next synchronization point. 30, no rollback).

In the case of Ti = 30, local simulation A is Te = 35 with To = 35 and n = 10 at the next synchronization point, and Te = 40 with To = 40 and n = 10 at local synchronization B. (In this case, Ts is actually 35, so rollback occurs at B).

In the case of Ti = 35, the local simulation A is Te = 40 with To = 45 and n = 5 at the next synchronization time point, and Te = 40 with To = 45 and n = 5 at the next synchronization time point in Local Simulation B as well. (In this case Ts is also 40 so no rollback occurs).

In the case of Ti = 40, the local simulation A is Te = 45 with To = 45 and n = 5 at the next synchronization point, and Te = 45 with To = 45 and n = 5 at the next synchronization point in Local Simulation B as well. (In this case Ts is also 45, so no rollback occurs).

In the case of Ti = 45, local simulation A is Te = 50 with To = 50 and n = 5 at the next synchronization point, and Te = 50 with To = 50 and n = 5 at local synchronization B. (In this case, Ts is also 50, so no rollback occurs).

In the case of Ti = 50, local simulation A is Te = 55 with To = 60 and n = 5 at the next synchronization point, and Te = 55 with To = 60 and n = 5 at local synchronization B. (In this case, Ts is also 55, so no rollback occurs).

In the case of Ti = 55, local simulation A is Te = 60 with To = 60 and n = 5 at the next synchronization point, and Te = 60 with To = 60 and n = 5 at local synchronization B. (In this case Ts is also 60, so no rollback occurs).

In the case of Ti = 60, the local simulation A is Te = 65 with To = 70 and n = 5 at the next synchronization point, and Te = 65 with To = 65 and n = 5 at the next synchronization point in Local Simulation B as well. (In this case Ts is also 65 so no rollback occurs).

In the case of Ti = 65, the local simulation A is Te = 70 with To = 70 and n = 5 at the next synchronization point, and Te = 70 with To = 75 and n = 5 at the next synchronization point in Local Simulation B as well. (In this case Ts is also 70, so no rollback occurs).

In this example, if the event intervals of both A and B do not become smaller than 5 after the simulation time 65, the distributed parallel simulation is performed while the synchronization is performed at a time interval of 5 units from the simulation time 65. In the case of a simulation where the distributed parallel simulation targets the DUV described at the register transfer level, this time interval 5 is a user clock present in the DUV driving the connection signals between the design objects performed on the local simulations A and B. It is highly probable that the cycle of the user clock is the smallest among them. That is, according to the synchronization method proposed by the present patent, the time force determined as the synchronization interval between local simulations after a certain simulation time has elapsed is a DUV that drives the connection signals between design objects performed by local simulations of distributed parallel simulation. Since the probability of the user clock being the smallest among the user clocks present in R is very high, the distributed parallel simulation can be performed after the rollback probability is close to zero. Therefore, if such a parallel simulation is performed in the method of the present patent, and it is determined that such a point has been reached (the judgment is automatically performed by the software performing the distributed parallel simulation. If anything goes wrong, it will not affect the correctness or wrongness of the simulation results, and will only have a limited effect of slightly lowering the performance improvement of the simulation.) From this point forward, checkpoints are prepared for rollback in each local simulation. It is possible to dynamically change the spacing very widely, thereby minimizing the overhead of the checkpoint.

As described in detail above, the patent discloses that the next synchronization time point Tn at the simulation time Ti of a specific local simulation Sl (j) of such distributed parallel simulation is to be directed to itself in other local simulations, and the local simulation Sl ( In the process of setting the next event occurrence time To, which occurs from j) and needs to go to other local simulations, the smaller of the two (the past in time) as the next expected synchronization point Te, the Tn is present (ie, simulation time 0). To Ti), the method in this patent that assumes Tn to be Ti + n by setting the time further advanced in Ti by the shortest "event minimum interval" n of all event intervals sent by that other local simulation. The method of predicting future synchronous time based on the experiences to date "is called. In addition, in the present patent, for the "future synchronization point prediction method based on the present experience", the checkpoint execution that is performed while changing the checkpoint execution interval during the distributed parallel simulation is referred to as a "checkpoint method that proceeds at a variable interval".

Other objects and advantages of the present invention in addition to the above objects will become apparent from the following description with reference to the accompanying drawings.

FIG. 1 schematically illustrates some examples of logical connection structure schemes of two or more local computers installed in two or more computers for the simulation of the distributed processing parallel execution scheme in the present patent.

FIG. 2 is a diagram schematically illustrating an example of a distributed parallel simulation environment in which distributed parallel simulation is configured using two or more computers and two or more HDL simulators installed in these computers.

3 is a diagram schematically showing an example of an overall flow chart of a typical distributed parallel simulation. Thus, there may be any number of other progress flow diagrams for the overall progress of distributed parallel simulation. In this distributed parallel simulation process, local simulation is performed for each local design object on each local simulator in step S106. Local simulation is performed while determining synchronization timing using the synchronization point determination method proposed in the present patent. .

As described above, the effects of the present invention provide a method of speeding up distributed parallel simulation by effectively reducing synchronization overhead and communication overhead in distributed parallel simulation.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

Claims (4)

In distributed parallel simulation using two or more simulators, or one or more simulators and one or more simulation accelerators or hardware emulators, The distributed parallel simulation is "a future synchronization point prediction method based on the experience to date" Distributed parallel simulation, characterized in that the use of. In distributed parallel simulation using two or more simulators, or one or more simulators and one or more simulation accelerators or hardware emulators, Distributed parallel simulation, characterized in that the distributed parallel simulation uses a "checkpoint method proceeding at variable intervals". In distributed parallel simulation using two or more simulators, or one or more simulators and one or more simulation accelerators or hardware emulators, In order to obtain a predicted synchronization time point of the local simulation, which may be the next synchronization time point in a process of performing a simulation in at least one local simulation among two or more local simulations performing the distributed parallel simulation, the specific simulation Distributed parallel simulation characterized by using the "external event minimum interval" obtained from all events delivered from other local simulations up to the point in time. The method of claim 3, wherein And performing a rollback of the corresponding local simulation when the actual synchronization point exists in the past as the simulation time in the past than the predicted synchronization point predicted in the local simulation.

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