KR102493046B1 - Performance Improvement Method in Prediction-based Parallel Gate-level Timing Logic Simulation Using Adaptive Prediction Data - Google Patents

Abstract

The present invention relates to an effective simulation method for maintaining high performance of prediction-based parallel gate-level timing logic simulation even after design modifications aimed at eliminating design errors. In the present invention, high performance of simulation is continuously achieved even after design modification through dynamic variation of expected input and expected output required in the expected I/O use-run mode of execution of prediction-based parallel gate-level timing logic simulation.

Description

Performance Improvement Method in Prediction-based Parallel Gate-level Timing Logic Simulation Using Adaptive Prediction Data}

The present invention relates to a technique for improving simulation performance by parallelizing gate-level timing logic simulation in digital circuit design.

"This project was researched by the Pusan National University Basic Research Support Project (2 years)"

In semiconductor design verification, simulation is software that configures DUV (Design Under Verification) and a testbench that drives it (hereinafter abbreviated as TB) as an executable model on a computer, and this execution It is a process of converting a possible model into a sequence of machine instructions of a computer through a simulation compilation process and executing it using a computer. Therefore, simulation execution is basically performed through sequential execution of computer machine languages. Currently, the most commonly used logic simulation technology is event-driven logic simulation. . The advantage of such a simulation is that its operating function or characteristics can be predicted in advance on a computer virtually before the design object is actually implemented, and high flexibility can be provided as it is a software method. Since the simulation is eventually performed through sequential execution of a sequence of machine languages, simulation is performed when the complexity of the design target to be simulated is high (for example, most of the recent semiconductors are designs of hundreds of millions of gates or more). The speed is very slow (for example, when the 100 million gate class design is performed with event-driven gate level timing simulation, the simulation speed becomes 1 cycle/sec due to sequential execution and if the simulation must be performed for 100,000,000 cycles, it is about 3.2 years). In addition, after one or more design errors are found and the design is modified during the simulation run, the same simulation is repeatedly run to ensure that the design errors are properly removed and other design errors are not introduced unintentionally during the design correction process. You just have to make sure it doesn't. That is, design verification through simulation must be performed repeatedly with a very high frequency.

In the recent complex digital system design, there are two objects to be designed, one is the DUV and the other is the TB to simulate the DUV. The DUV is a design target that is ultimately made into a chip through the semiconductor manufacturing process, and the test bench is used for DUV simulation as a model of the surrounding situation in which the implemented chip is mounted and operated. In the case of simulating a DUV, it is common for a testbench to apply inputs to the DUV, accept the results output from the DUV as the applied inputs, and process them. These DUVs and test benches generally have one or more various sub-modules in a hierarchical structure. Each of these sub-modules can be referred to as a design block, design modules exist inside the design block, and sub-modules exist inside the design module. modules exist. All of these design blocks, or design modules, or submodules, or DUV, and each or part of the test bench, or combinations thereof, or parts of combinations thereof, are all designated as design objects in the present invention (specific examples include: Modules in the case of Verilog, entities in the case of VHDL, and sc_modules in the case of SystemC are all examples of design objects). In addition, one design object may include one or more other design objects inside through a hierarchical structure, and in this way, each of one or more design objects existing inside the hierarchical structure will be referred to as a sub-design object.

In preparation for a general single simulation method (in the present invention, a single simulation method is defined as a single simulation method in which one simulator is executed on a single CPU or CPU core), two or more simulators are combined with two or more CPUs or more as a method of increasing verification speed. There is a parallel simulation method in which a simulation is executed in a distributed parallel manner on a CPU core. Distributed parallel simulation, which is a distributed processing method of simulation (also referred to as parallel distributed simulation or simply parallel simulation, in the present invention is referred to as distributed parallel simulation) is the most common parallel simulation method, which is a simulation target DUV and TB (that is, a simulation model at a specific level of abstraction, in the present invention, the entire DUV and TB simulation target will be referred to as a simulation model, or simply "model") is divided into two or more design objects, and each of these divided design objects is distributed to a separate simulator to perform them in parallel. Therefore, for distributed parallel simulation, a partitioning process is required to divide the simulation target model into two or more local design objects (described below). In the present invention, a specific local simulation (local simulation refers to a simulation performed for a corresponding design object in an individual simulator in a parallel simulation) through a division process. A design object that has to be executed in the simulation) will be referred to as a "local design object".

In general, dividing the number of local design objects to increase the number of local design objects for parallel simulation increases the possibility of parallelization, so a greater performance improvement can be expected by parallel simulation. There is a problem that performance improvement is very limited due to head and synchronization overhead (communication overhead and synchronization overhead). There are two main synchronization methods in distributed parallel simulation. One is a conservative method (or also called a pessimistic method) and the other is an optimistic method. Synchronization of the conservative method does not require rollback as the causality relation between simulation events is always maintained between simulators, but the problem is that the speed of distributed parallel simulation is limited to the slowest local simulation. There is a problem in that excessive synchronization occurs, and synchronization in an optimistic manner may temporarily prevent the causal relationship between simulation events from being maintained between simulators, and rollback is required to correct this, so reducing the total number of rollbacks is a distributed parallel simulation. will have a great impact on the performance of However, in the distributed parallel simulation by the optimistic method so far, simulation points in which each local simulation proceeds without synchronization with other local simulations are not specially considered to minimize rollback, resulting in excessive rollback. As a result, the performance of the entire simulation is greatly reduced. In conclusion, all of the current conservative synchronization methods and communication methods, optimistic synchronization methods and communication methods have limitations that significantly reduce the performance of distributed parallel simulation using two or more simulators due to communication overhead and synchronization overhead. there was a problem with

A "prediction-based parallel simulation method" (Patent No. 10-2006-0092574) has been proposed as a new event-driven parallel logic simulation method to improve such problems. The operation method of the prediction-based parallel logic simulation method proposed in Patent No. 10-2006-0092574 is briefly described as follows. Prediction-based parallel logic simulation proceeds alternately between two execution modes: expected I/O use-run mode and actual I/O use-run mode. These two execution modes are described as follows. In the expected input/output use-run mode, each of the local design objects utilizes the expected input and executes each local simulation independently without interlocking with other local simulations to obtain actual outputs from the output of each local design object, and at the same time these The simulation proceeds while comparing each of the actual output values with the expected output values in real time during the simulation process. And if these comparisons (actual output and expected output) are matched, it is possible to greatly increase the simulation speed by completely omitting communication and synchronization between local simulators and advancing each local simulation time. However, if the actual output is compared with the expected output and they do not match (this simulation point is called the expected output/actual output discrepancy point), from this expected output/actual output discrepancy point, communication and synchronization process between all local simulators while performing, the distributed parallel simulation proceeds in the real input/output use-run mode that utilizes real inputs. That is, from this point of simulation, the execution mode is switched to the actual input/output use-run mode in which communication and synchronization processes are performed between local simulators (the simulation point at which this transition occurs is called the actual input/output use-run application point). However, one or more specific local simulations proceed faster than the local simulation that caused the expected output/actual output discrepancy, so that their local simulation time has already passed the expected output/actual output discrepancy point. There is a need to restart after rollback after returning to the point of inconsistency between the expected output and actual output. To this end, each local simulation must be conducted while creating a checkpoint at regular intervals in case of proceeding in the expected I/O use-run mode. When an expected output/actual output mismatch occurs and the local simulation time of one or more local simulations exceeds the expected output/actual output discrepancy point, all local simulations roll back to the nearest checkpoint from the expected output/actual output discrepancy point. After that, each local simulation proceeds in the expected I/O use-run mode until just before the point of the expected output/actual output discrepancy, then adjusts the local simulation time of all local simulations to the point of the expected output/actual output discrepancy. From this point on, the actual input All local simulations are run in real-output-run mode (i.e. in real-output-run mode, traditional parallel simulations are run). In this real input/output use-run mode, each local simulation proceeds with a simulation that causes communication and synchronization with other local simulations (therefore, while performing a simulation while generating communication overhead and synchronization overhead that limit simulation performance) ), and at the same time compare the actual output with the expected output in real time. When a situation in which this actual output coincides with the expected output a certain number of times (eg, 10 times) occurs in all local simulations, each local simulation reverts to the expected I/O use-run mode and uses the expected input to synchronize and Simulation proceeds without communication process. Through this process, in the prediction-based parallel logic simulation method, in the simulation process for local design objects, simulation is performed by using expected input values instead of actual input values as input values, and if the actual output values obtained are the same as the expected output values, another local design Synchronization and communication with objects are not required, and each local design object can be executed completely independently, so performance improvement by parallel simulation can be expected (refer to Patent 10-2006-0092574 for details). In addition, a “prediction-based parallel simulation method” (Patent Nos. 10-2020-0100940 and 10-2021-0103195) has been proposed as a new event-driven parallel logic simulation method that additionally improves problems.

In the prediction-based parallel gate-level timing simulation methods proposed in Patent Nos. 10-2006-0092574, 10-2020-0100940, and 10-2021-0103195, it is essential to ensure high prediction accuracy in order to keep the simulation performance high. to be. However, a design error is found and becomes a design change, and in particular, when this design error is a functional design error, design modification to eliminate it (referred to as "functional design change" in this patent), or functional design In the case of a pure timing design error that is not an error (in this patent, it is referred to as "timing design error"), the prediction-based Since high prediction accuracy cannot be maintained in parallel gate-level timing simulation, performance improvement by parallel simulation cannot be expected.

Accordingly, an object of the present invention is to provide a method capable of continuously maintaining high prediction-based parallel gate-level timing simulation performance even after a design change to eliminate design errors in a prediction-based parallel gate-level timing simulation method.

In order to achieve the above objects, a design verification device necessary to apply the design verification method according to the present invention may be composed of one or more computers in which verification software and one or more simulators are installed. Another design verification apparatus to which the design verification method in the present invention can be applied is composed of one or more computers in which verification software and one or more simulators are installed. Verification software runs on a computer, and if there are two or more computers in the design verification device, these two or more computers are connected by a bus to enable movement of data generated during simulation execution between the computers. The one or two or more simulators for the purpose of design verification are configured as event-driven simulators (Parallel Discrete Event Simulation (PDES) is a parallel simulation by configuring distributed parallel simulation only with event-driven simulators). there is.

The state information of a design object is a flip that exists in a model through modeling at a specific level of abstraction at a specific simulation time point (eg, simulation time 29,100,511 nanoseconds) or a certain simulation time interval (eg, 100 nanosecond interval from simulation time 29,100,200 nanoseconds to 29,100,300 nanoseconds). It refers to dynamic information including values of variables or signals that a flop model, latch model, memory model, or combinatorial feedback loop model should have. The dynamic information of a design object is one or more signals or logic values of signal lines that exist in the design object at a specific simulation time point or a specific simulation period (which may be the entire simulation period) in the simulation process, or in the model or design object. The value of one or more variables or constants that come into existence. These dynamic information can be obtained during the simulation execution process. To give an example of obtaining dynamic information during the simulation execution process, a typical method is system tasks such as $dumpvars, $dumpports, $dumpall, $readmemb, $readmemh, etc. This can be achieved by using a user-defined system task. In addition, the input information of a design object refers to the values of all inputs and inputs and outputs of a design object in a specific simulation time interval (this specific simulation time interval can be the entire simulation time interval), and the design object The output information of a design object refers to all the outputs of a design object in a specific simulation time section (which can be the entire simulation time section), and the values on the input/output, and the input/output information of a design object refers to the specific simulation time section (the entire simulation time). It refers to the values on all inputs, outputs, and inputs and outputs of the design object in (can be a section).

The prediction-based parallel gate-level timing simulation method presented in Patent Nos. 10-2006-0092574, 10-2020-0100940, and 10-2021-0103195 is expected input/output during the design process, and the simulation results previously performed temporally are used, or the results of simulations previously performed temporally using an abstracted high-level model (ie register transfer level model) are used during the progressive materialization process. That is, one or more design objects that can be obtained in the previous simulation run process (obtained through system tasks such as $dumpvars, $dumpports, $dumpall, $readmemb, $readmemh, etc. or user-defined system tasks in Verilog simulation run) After saving the input and output information for , it is used as the expected input and expected output required in the process of proceeding with the prediction-based parallel gate-level timing simulation for the subsequent simulation. It is possible to increase the performance of the simulation (in this patent, the methods presented in patents 10-2006-0092574, 10-2020-0100940, and 10-2021-0103195 are referred to as "pattern-based static expected input/expected output utilization method"). shall be referred to as).

However, in most cases, between the previously executed simulation and the current simulation, a design change was made to remove the design error through a debugging process in which design errors are found through previously executed simulations and removed (i.e., There is virtually no need to re-run the same simulation as previously run, even though no design changes have been made). In such a design change process, there is always a possibility that a new design error may be added to one or more design objects unintentionally. Therefore, iterative simulation is absolutely necessary after design change. If one or more design objects are modified through such a design change process, in the pattern-based static expected input/expected output utilization method, there is a risk that the prediction accuracy of the expected input/expected output obtained in the previous simulation execution process will be very low. In this case, the prediction-based parallel gate-level timing simulation method proposed in patents 10-2006-0092574, 10-2020-0100940, and 10-2021-0103195 cannot be performed in the expected I/O use-run mode and requires communication overhead. Since it has to be performed in actual I/O use-run mode in which synchronization overhead occurs, a large performance degradation occurs in parallel gate-level timing simulation.

In order to solve this problem, in this patent, two new methods are used together with the "pattern-based static expected input/expected output utilization method" used in patents 10-2006-0092574, 10-2020-0100940, and 10-2021-0103195. "Expected input/expected output dynamic generation method based on abstract high-level model" and "Expected input/expected output dynamic generation method based on abstraction mixed level model" are additionally used. The difference between the two new methods in this patent and the "pattern-based static expected input/expected output utilization method" used in patents 10-2006-0092574, 10-2020-0100940, and 10-2021-0103195 is In the above two new methods, expected input/expected output is dynamically generated in real time through a simulation execution process, while patents 10-2006-0092574 and 10-2020-0100940 and The pattern-based static expected input/expected output utilization method used in 10-2021-0103195 is to utilize expected input/expected output that is already statically stored in a file in the form of a pattern. As such, the advantage of the pattern-based static expected input/expected output obtained in the previous simulation execution process is that it is already statically stored in a file, so it is very fast and simple memory reading to use it as the expected input/expected output of the prediction-based parallel simulation. operation can be utilized, but a critical weakness is that in the prediction-based parallel gate-level timing simulation that proceeds after the design change due to design error correction, the design change can invalidate the expected input/expected output value obtained before the design change. As a result, it is very difficult to guarantee high prediction accuracy, and as a result, the actual I/O use-run mode rather than the expected I/O-run mode occupies most of the simulation time during the entire simulation run time, so that the expected simulation performance improvement is obtained through parallel simulation. is that it is difficult

In order to solve such a problem, this patent newly proposes "Expected input/expected output dynamic generation method based on abstraction high-level model" and "Expected input/expected output dynamic generation method based on abstraction mixed level model" (in this patent, These two methods are collectively referred to as "expected input/expected output dynamic generation method") divides the accurate gate-level timing model, which is the design verification target, in the prediction-based parallel gate-level timing simulation execution that proceeds after the design is changed. By dividing into two or more local design objects, each of them is executed through local simulation of prediction-based parallel simulation, and at the same time, in each local simulation, the entire model at a higher level of abstraction or the entire model at a mixed level of abstraction is also simulated, and expected input / Create the expected output in real time and use it in each local simulation. The method of dynamically generating such expected input/expected output through additional simulation execution in each local simulation can obtain very high prediction accuracy very quickly even when a design change is made. However, there is also a risk that performance degradation of each local simulation may occur if additional simulation execution is performed along with the original simulation for each local design object in each local simulation. However, in order to effectively eliminate this risk, the simulation run, which is additionally performed to dynamically secure prediction input/prediction output along with simulation for each original local design object in each local simulation in this patent (original each Whereas simulation for local design objects is gate-level timing simulation), register-transfer-level functional simulation with a high level of abstraction or mixed-level mostly functional/local timing mixed simulation (largely functional and gate-level mixed register transfer level) minimally timing mixed simulation) (i.e., the part where gate-level timing simulation is locally performed is limited to the minimum design object where the design change part exists, and the rest of the part that occupies most of the entire model is at the register transfer level Functional simulation) prevents performance degradation of each local simulation due to additional simulation execution (register transfer level functional simulation is at least 100 times faster than gate level timing simulation due to its higher level of abstraction) Note that it can be done).

Dynamic generation of expected input/expected output is divided into two types: "dynamic generation method of expected input/expected output based on abstract high-level model" and "dynamic generation method of expected input/expected output based on mixed-level model of abstraction". This is because the functional property of the model can be changed through, or “the functional property remains the same and only the timing is changed”. Here, "the functional properties are kept the same and only the timing is changed" means the difference between the simulation results before the design change (the simulation result value refers to the dynamic information obtained from simulation execution) and the simulation result values after the design change. means that is smaller than one cycle of the clock existing in the design object. In other words, if the design change changes the functionality of the model, the expected input/expected output is generated dynamically and quickly by using the "dynamic generation method of expected input/expected output based on an abstract high-level model". If the design change maintains the functional nature of the model but only changes the timing, use the "dynamic generation method of expected input/expected output based on a mixed level model of abstraction" so that expected input/expected output can be generated dynamically and accurately. . In addition, in the execution process of "Dynamic Generation Method of Expected Input/Expected Output Based on Abstraction Mixed Level Model", the "gate level design object extension in mixed level model" method is additionally used. In the mixed-level model, the gate-level design object extension method is the smallest gate-level design object DO_b that includes the gate-level design object DO_a that already exists in the mixed-level model (ie, DO_b in the model includes DO_a internally as a sub-design object). The smallest design object) is designated as a new gate-level design object in the mixed-level model. The case in which the gate level design object extension method is applied in the mixed level model is a case in which the design change maintains the same functional property but the timing is changed. Useful effects that can be obtained by applying the gate-level design object extension method in mixed-level models include minimizing simulation performance degradation and predicting by increasing the prediction accuracy of "dynamic generation method of expected input/expected output based on abstraction mixed-level model" Enables the operating mode of the underlying parallel gate-level timing simulation to continue operating in the expected I/O use-run mode (which is key to maximizing the performance of prediction-based parallel simulations) without switching to the actual I/O use-run mode.

As described above, the effect of the present invention is three types of prediction input / prediction output that can maintain the maximum performance improvement of simulation through parallelization that minimizes communication overhead and synchronization overhead in the prediction-based parallel simulation method. It is to provide a new prediction-based parallel simulation method that can maintain the overall performance improvement of the simulation as much as possible regardless of whether or not the design change necessary for eliminating design errors is carried out through other methods.

Through the above description, it will be appreciated that various changes and modifications are possible within the range that does not deviate from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be determined by the claims.

1 is a diagram conceptually illustrating the operation principle of two modes of prediction-based parallel simulation, the expected I/O use-run mode and the actual I/O use-run mode.
2 is a diagram conceptually illustrating a pattern-based static expected input/expected output utilization method and a dynamic expected input/expected output generation method.
3 schematically illustrates an example of a multiprocessor computer system configuration for executing predictive-based parallel gate-level timing simulations in accordance with the present invention.
4 is a diagram showing an example of a simulation target model having a total of 10 design objects inside as a register transfer level model and a gate level model, respectively.
5 is a diagram schematically showing an example of the configuration of components constituting the inside of a design code (additional code) added for prediction-based parallel gate-level timing simulation proposed in the present invention with respect to a specific local simulation.
6 is a prediction-based parallel gate-level timing simulation method in this patent for expected input and expected output in a situation in which the simulation target model illustrated in FIG. 4 is divided into six local design objects and six local simulations are performed. A diagram conceptually showing that a pattern-based static expected input/expected output utilization method is used.
Figure 7. The prediction-based parallel gate-level timing simulation method in this patent is divided into 6 local design objects by dividing the simulation target model illustrated in FIG. 4 into 6 local simulations. A diagram conceptually illustrating how the dynamic generation method is used.
8 is a prediction based on mixed level abstraction model in a situation in which the prediction-based parallel gate-level timing simulation method in this patent is divided into six local simulations by dividing the simulation target model illustrated in FIG. 4 into six local design objects. A diagram conceptually showing that the input/expected output dynamic generation method is used.
Figure 9. In FIG. 8, a mixed-level model that generates expected input/expected output in real time is shown including a hierarchical structure in more detail.
FIG. 10 is a diagram specifically showing a situation in which gate-level design object expansion occurs in a mixed-level model in which the expected input/expected output shown in FIG. 9 is generated in real time.
11 is a flowchart illustrating the entire process of the prediction-based parallel gate-level timing simulation method according to the present invention as a flowchart.

Other objects and advantages of the present invention will become apparent through the detailed description of the embodiments with reference to the accompanying drawings.

1 shows two modes of prediction-based parallel simulation, the expected input/output use-run mode that does not generate any communication overhead and synchronization overhead 14 by using expected input/output, and the use of actual input/output. This is a diagram conceptually showing the operating principle of the actual input/output use-run mode, which generates communication overhead and synchronization overhead 14, which are performance degradation factors of parallel simulation.

2 is a diagram conceptually illustrating a pattern-based static expected input/expected output utilization method and a dynamic generation expected input/expected output method. In the pattern-based static expected input/expected output utilization method, "expected input/expected output in pattern format stored in a file" in the form of a simple pattern file of 0 and 1 and unknown values (312) in the previous simulation run process In contrast to the method of statically utilizing the expected input/expected output, the dynamic generation method executes the "simulation model" 412 of all design objects capable of simulation together with local design objects in each local simulation (that is, through simulation execution). ) This is a method of dynamically generating and utilizing expected input/expected output in real time. The simulation model 412 is either an abstraction high-level model (a method of dynamically generating expected input/expected output based on an abstraction high-level model) or a mixed-level abstraction model. (Expected input/expected output dynamic generation method based on abstraction mixed level model).

3 is a diagram schematically illustrating an example of a multiprocessor computer system configuration for executing prediction-based parallel gate-level timing simulation according to the present invention. One processor 77 and memory 79 resources are used for one local simulation.

4 shows an example of a simulation target model having a total of 10 design objects inside as a register transfer level model 80 and a gate level model 90, respectively. The gate level model 90 is automatically created from the register transfer level model 80 through an automatic design process utilizing a logic synthesizer. In this example, by the hierarchical structure, design object 1 and design object 6 have design object 1a and design object 1b, and design object 6a and design object 6b as sub-design objects, respectively.

5 is a diagram schematically showing an example of the configuration of components constituting the inside of a design code (additional code) added for prediction-based parallel gate-level timing simulation proposed in the present invention with respect to a specific local simulation. That is, in this example, it is a diagram schematically showing an example in which the behavior of the additional code added to the local design object 1, which is a part of the simulation target model M performed in the local simulation, is composed of components. Therefore, the above additional code is added to the local design object (1) so that the components shown in FIG. 5 (expected input/output use-run/actual input/output use-run control module (2), expected input/actual input selection module (3) ), expected output / actual output comparison module (4), expected input / actual input comparison module (5), expected input / expected output generation / storage module (8)) of the local design object (1) for output should be able to do The behavior of each module is reorganized as follows. The expected I/O use-run/actual I/O use-run control module (2) is distributed with the expected output/actual output comparison module (4) and expected input/actual input comparison module (5) of the local design object (1) for output. Inputs are received from the communication and synchronization module 7 for parallel simulation, and the values of these inputs and the current state of whether the current local simulation is proceeding in an expected I/O-run method or an actual I/O-run method (thus, the expected The I/O use-run/actual I/O use-run control module (2) internally has a state variable that can determine whether the current local simulation proceeds in the expected I/O use-run method or the actual I/O use-run method. Depending on the expected input/actual input selection module (3), an output is generated and the expected input/actual input selection module (3) selects the expected input, or the actual input, or a rollback is required. This will control the performance of the rollback. That is, while the current local simulation is in progress in the expected input/output use-run method (therefore, the expected input/output use-run/actual input/output use-run control module (2) is currently expected input/actual input selection module (3) is expected input The output to be selected is sent to the expected input/actual input selection module (3) for control) and the expected output and actual output from the expected output/actual output comparison module (4) of all sub-design objects When the judgment that the actual output is different comes as an input, the expected input/output use-run/actual input/output use-run control module (2) selects the expected input/actual input so that the expected input/actual input selection module (3) selects the actual input. module (3), switch the internal current state variable from expected I/O use-run to actual I/O use-run, and at the same time, when a specific rollback time for rollback is input from the communication and synchronization module (7) for distributed parallel simulation, Control is also performed so that rollback can be performed with a specific rollback time, and while the current local simulation is in progress in the actual I/O use-run method (therefore, the expected I/O use-run/actual I/O use-run control module (2) An output that allows the input/actual input selection module (3) to select the actual input is sent to the expected input/actual input selection module (3) for control. When the determination that this is equal to a certain number of times or more comes as an input, the expected input/output use-run/actual input/output use-run control module (2) outputs the output so that the expected input/actual input selection module (3) selects the expected input. It is sent to the input selection module 3, and at the same time, the current state variable inside is switched from actual I/O use-run to expected I/O use-run. In addition, the expected I/O use-run/actual I/O use-run control module (2) has two outputs ( Actual input/output use-run required, expected input/output use-run possible) is sent to the communication and synchronization module (7) for distributed parallel simulation, and the expected input/expected output generation/storage module (8) is controlled to fit the result from (8). It outputs the expected input or expected output. The expected output / actual output comparison module (4) of the local design object (1) for output is generated in real time in the expected input / expected output generation / storage module (8) or previously stored expected output and performed in the local simulator The actual output that is actually produced in the local simulation execution process is compared from part (1) of the design verification target model. output, and if this comparison is inconsistent, send the mismatch to the expected I/O use-run/actual I/O use-run control module (2) as an output, and at the same time send the current value for rollback to the communication and synchronization module (7) for distributed parallel simulation. Sending the simulation time allows other local simulations to pass this information (the current simulation time for rollback). The expected input/actual input comparison module 5 is generated in real time by the expected input/expected output generation/storage module 8 or previously stored expected input and another one coming from the communication and synchronization module 7 for distributed parallel simulation. Actual inputs from the above local simulation are compared, and if the comparison matches a certain number of times, it is sent as an output to the expected I/O use-run/actual I/O use-run control module 2. Finally, the expected input/actual input selection module (3) uses the expected input/output use-run/actual input/output use-run as the output of the control module (2) and the actual input and expected input/expected output coming from the communication and synchronization module (7). In the generation/storage module 8, one of expected inputs generated in real time or previously stored is selected and applied as an input to the local design object 1, which is a part of the design verification target model performed in the local simulator. The expected input/expected output generation/storage module 8 dynamically generates the expected input/expected output in real time during the local simulation run process (used for the dynamic generation method of the expected input/expected output), or already created in a previous simulation. This is a module that statically stores expected input/expected output in the form of a file (used for pattern-based static expected input/expected output utilization method). The expected input/expected output generation/storage module (8) is an abstracted high-level model (i.e., a register transfer level model) of the gate-level timing simulation target design object in order to dynamically generate the expected input/expected output in real time during the local simulation execution process. or a mixed-level model of abstraction. In addition, in FIG. 5, the communication and synchronization module 7 for distributed parallel simulation performs normal communication and synchronization required in a typical distributed parallel simulation.

6 is a prediction-based parallel gate-level timing simulation method in this patent for expected input and expected output in a situation in which the simulation target model illustrated in FIG. 4 is divided into six local design objects and six local simulations are performed. It is a diagram conceptually showing that the pattern-based static expected input/expected output utilization method is used.

Figure 7. The prediction-based parallel gate-level timing simulation method in this patent divides the simulation target model exemplified in FIG. In this example, the register transfer level) model 142 is executed (i.e., simulated) in real time with each local design object in each local simulation, and the expected input/expected output is dynamically generated, that is, the higher level of abstraction (this example In , it is a diagram conceptually showing that the register transfer level) model-based expected input/expected output dynamic generation method is used.

8 shows the prediction-based parallel gate-level timing simulation method in this patent for expected input and expected output in a situation where the simulation target model illustrated in FIG. 4 is divided into six local design objects and six local simulations are performed. Mixed levels of abstraction (mixed register transfer level and gate level in this example) model 146 is run (i.e. simulated) in real time with each local design object in each local simulation, dynamically generating expected inputs/expected outputs. It is a diagram conceptually showing how to do this, that is, a method of dynamic generation of expected input/expected output based on a mixed-level model of abstraction is used.

Figure 9. In FIG. 8, it is a diagram showing the mixed-level model 146 that generates expected input/expected output in real time, including a hierarchical structure in more detail. In the mixed-level model, only the design object 1a (i.e., a design error was found in the design object 1a and a design change was made to eliminate it) is the gate level, and this design Except for object 1a, all other design objects are exemplified at the register transfer level, which has a higher abstraction level than the gate level. When such a mixed level model is placed inside the expected input/expected output generation/storage module 8 in FIG. 5 and the expected input/expected output is generated in real time during the local simulation execution process, the existing pattern-based static expected input/ Compared to prediction-based parallel gate-level timing simulation using the expected output utilization method, expected input/expected output with much higher prediction accuracy after design change can be quickly generated even in prediction-based parallel gate-level timing simulation after design change.

FIG. 10 is a diagram specifically showing a situation in which "gate level design object expansion in mixed level model" occurs in the mixed level model 146 generating the expected input/expected output in real time shown in FIG. 9 . In other words, only the design object 1a where the design change was made is at the gate level, and all other design objects are the prediction accuracy of the expected input/expected output dynamically generated through the mixed-level model, which is the register transfer level, which is the upper level of abstraction (ie, timing prediction accuracy) is not sufficiently accurate, design object 1, which is the smallest design object that contains the design object 1a to which the design change has been made, in order to minimize the degradation of the local simulation and at the same time increase the accuracy of the expected input/expected output. A new mixed-level model is created at the gate level and all other design objects are at the register transfer level, which is the upper level of abstraction, through “expansion of gate-level design objects in mixed-level models” and dynamically new expected input/expected output in each local simulation. is used as a mixed-level model generated in real time.

11 is a flow chart illustrating the entire process of the prediction-based parallel gate-level timing simulation method in the present invention.

First of all, whether to use “pattern-based static expected input/expected output utilization method” or “model-based expected input/expected output dynamic generation method” as expected input/output depending on whether it is simulation after design change or not. Decide. In addition, depending on whether the design change is a functional design change that eliminates functional design errors, whether to use the "dynamic generation method of expected input/expected output based on a high-level abstraction model" or "expected input based on a mixed-level model of abstraction" /Determines whether to use "Expected output dynamic generation method". Afterwards, in the "model-based expected input/expected output dynamic generation method", each local simulation is run in the expected I/O use-run mode, and at the same time, whether the prediction is correct or not is investigated, and the degree of difference between the actual value and the predicted value is called "delay time difference" ( In this patent, the degree of difference is the delay time difference, which defines that there is only a time difference between the actual value and the predicted value in the simulation time, and no value difference. If the actual value is 1 from 112 nanoseconds to 198 nanoseconds and then 0 from 198 nanoseconds, while the actual value is 0 from simulation time 0 to 102 nanoseconds, then 1 from 102 nanoseconds to 188 nanoseconds, and then 0 from 188 nanoseconds, only the delay time difference exists), but only when the difference in delay time is not smaller than one cycle of the clock existing in the design object or when the degree of difference between the actual value and the predicted value is greater than the difference in delay time do. Then, while executing the simulation in the actual I/O use-run mode, investigate whether it is possible to switch to the expected I/O use-run mode, and if possible, switch back (the number of times that the actual input and actual output of all local simulations match the expected input and expected output is checked in advance). It is determined whether a predetermined number of times is reached, and if the matching number reaches a predetermined number in all local simulations, the actual I/O use-run mode is switched from the expected I/O use-run mode). However, in the "model-based expected input/expected output dynamic generation method", each local simulation is executed in the expected I/O use-run mode, and at the same time, whether the prediction is correct or not is investigated, and the degree of difference between the actual value and the predicted value is the difference in delay time If the delay time difference is less than one cycle of the clock existing in the design object, after proceeding with the gate-level design extension in the mixed-level abstraction model, it is continuously executed in the expected I/O-run mode for each local simulation, and at the same time checks whether the prediction is correct or not. We will proceed through the investigation process.

1: Local design object
2: Expected I/O use-run/actual I/O use-run control module
3: expected input/actual input selection module
4: expected output/actual output comparison module
5: expected input/actual input comparison module
6: another local design object
7: Communication and synchronization module for distributed parallel simulation
8: Expected input/expected output generation/save module
10: Additional code added to the design code to be verified as verification software
11: local simulation
12: expected input/output
14: communication overhead and synchronous overhead
35: local computer
61: expected input generation / storage module
63: expected output generation / storage module
71: bus
73: processor core
75 : Cash
77: processor
79: memory
80: register transfer level design object
84: abstraction mixed level design object
90: gate level design object
100: simulation target model
135: connection structure between local computers
140: expected input/expected output pattern file
142: abstract high-level model
146: Abstraction Mixed Level Model
243: local simulator
312: Expected input/expected output of the pattern format stored in the file
343: Additional code and local design objects running in local simulation
412: abstract high-level simulation model

Claims (3)

When performing distributed parallel simulation in which a plurality of simulators used for simulation of a gate-level timing simulation target model composed of two or more design objects are executed in distributed parallel on a plurality of CPUs or CPU cores, (i) Expected I/O use-run As a prediction-based gate-level timing simulation method in which the distributed parallel simulation is performed through a process of alternately executing two execution modes, (ii) using actual I/O-run mode,
The plurality of simulators include a first local simulator that performs at least one local simulation and a second local simulator that performs another local simulation,
Static utilization of pattern-based expected input/expected output saved in previous simulations as expected input/expected output (How to use pattern-based static expected input/expected output), or local design of abstraction high-level model in each local simulation Expected input/expected output is dynamically generated by executing with an object (a method of dynamically generating expected input/expected output based on an abstract high-level model), or by executing a mixed-level model of abstraction with a local design object in each local simulation. Dynamically generate input/expected output (method of dynamic generation of expected input/expected output based on abstraction mixture level model),
(A) The above three methods (pattern-based static expected input/expected output utilization method, abstraction high-level model-based expected input/expected output dynamic) While proceeding to the expected input/output use-run mode, which utilizes the expected input and expected output obtained through one of the expected input/expected output dynamic generation method based on the generation method and the mixed level of abstraction model,
At the same time, grasping the degree of difference between the actual output and the expected output,
(B) In the step of figuring out the degree of difference between the actual output and the expected output, the difference between the actual output and the expected output is the delay time difference, and this delay time difference is greater than one cycle of the clock existing in the design object, or If the degree of difference between actual output and expected output is not only the difference in delay time, or if there is a difference between actual output and expected output and the pattern-based static expected input/expected output utilization method is in use, use expected I/O-Run mode to the real I/O use-run mode and proceeding all local simulations to the real I/O use-run mode;
(C) Actual actual input/output use-while proceeding to run mode,
At the same time, it is determined whether the number of matches between actual inputs and actual outputs of all local simulations and expected inputs and expected outputs reaches a predetermined number of times, and when the number of coincidences reaches a predetermined number of times in all local simulations, actual input/output use- Switching from the run mode to the expected input/output use-run mode to progress all local simulations to the expected input/output use-run mode;
A prediction-based parallel gate-level timing simulation method comprising a. According to claim 1,
When the expected input/expected output dynamic generation method based on the abstracted high-level model is used for expected input/expected output, the prediction-based gate-level timing simulation exists in the simulation target model composed of two or more design objects. It is a simulation that proceeds after a design change to remove one or more design errors is made, and the design change is a functional design change to remove a functional design error,
When the expected input/expected output dynamic generation method based on the mixed-level abstraction model is used for expected input/expected output, the prediction-based gate-level timing simulation exists in the simulation target model composed of the two or more design objects. A simulation that proceeds after a design change is made to remove one or more design errors, and the design change is a timing design change to remove a timing design error,
A predictive-based parallel gate-level timing simulation method. According to claim 1,
When the expected input/expected output dynamic generation method based on the abstracted high-level model is used for expected input/expected output, the prediction-based gate-level timing simulation exists in the simulation target model composed of two or more design objects. It is a simulation that proceeds after a design change to remove one or more design errors is made, and the design change is a functional design change to remove a functional design error,
When the expected input/expected output dynamic generation method based on the mixed-level abstraction model is used for expected input/expected output, the prediction-based gate-level timing simulation exists in the simulation target model composed of the two or more design objects. A simulation performed after a design change to remove one or more design errors is made, the design change is a timing design change to remove a timing design error,
In the step of determining the degree of difference between the actual output and the expected output, the degree of difference between the actual output and the expected output is the delay time difference, and if the delay time difference is smaller than one cycle of the clock existing in the design object, Characterized in that the simulation execution proceeds with the extension of the gate-level design object in the abstraction mixed-level model used in the model-based expected input/expected output dynamic generation method, and then continues in the expected I/O use-run mode.
A predictive-based parallel gate-level timing simulation method.

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