CN104899076B - A kind of accelerated method of super large-scale integration gate level netlist emulation - Google Patents
A kind of accelerated method of super large-scale integration gate level netlist emulation Download PDFInfo
- Publication number
- CN104899076B CN104899076B CN201510342090.7A CN201510342090A CN104899076B CN 104899076 B CN104899076 B CN 104899076B CN 201510342090 A CN201510342090 A CN 201510342090A CN 104899076 B CN104899076 B CN 104899076B
- Authority
- CN
- China
- Prior art keywords
- gate level
- level netlist
- output valve
- critical registers
- simulation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
- Tests Of Electronic Circuits (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
The present invention proposes a kind of accelerated method of super large-scale integration gate level netlist emulation, and step is：1, the proving program progress to integrated circuit modules is individually designed, screens effective register and is configured, forms the simulation excitation simplified；2, register is configured, using the simulation excitation simplified, simulating, verifying is carried out to the rtl code of SOC, critical registers and material time point are set, obtains and preserves output valve of the critical registers in material time point；3, according to the critical registers preserved in the output valve of material time point, filter out the output valve critical registers different from initial value；4, after gate level netlist simulation run starts, at suitable time point, assignment is carried out to the critical registers screened in step 3 using the output valve of the critical registers of acquisition, continues gate level netlist simulation work.The present invention can greatly shorten the simulation time of super large-scale integration gate level netlist, improve verification efficiency.
Description
Technical field
The present invention relates to Computer Applied Technology, is a kind of acceleration side of super large-scale integration gate level netlist emulation
Method, it belongs to super large-scale integration simulating, verifying field.
Background technology
Chip design realization is roughly divided into front end logic design synthesis and two parts of back-end physical design synthesis.Wherein,
It is multiple that back-end physical design realization includes clock tree synthesis, placement-and-routing, power consumption analysis, physical verification and manufacturability design etc.
Step.In a chip design, definition, exploitation, synthesis, the integrated and verification of front end logic are no doubt important.But with semiconductor
The development of manufacturing process, chip piece will go flow, and then volume production, and its rear end physical Design, which is realized, seems very crucial.
For the correctness for ensureing chip functions and realizing, verification will pass through realizes process in entirely designing for chip.Test
Card is the correctness for confirming designed circuit function in the design process.Verification can pass through software emulation (Software
Simulation), hardware accelerator verification (Hardware Emulation) and formal verification (Formal Verification)
The methods of carry out, it is the work to be done before flow.
Software emulation refers to utilize simulation excitation, by simulation software, to SoC architecture progress functional verification.Software
Emulation is divided into front-end simulation and rear end emulation.Front-end simulation refers to emulate the RTL code of SoC, main to verify system knot
The correctness of structure function.Rear end emulation refers to utilize timing information file (Standard Delay File, sdf), to SoC's
Gate level netlist (Gate Level Netlist) is emulated, and the main correctness verified architecture and realized, emphasis is verification
Whether sequential restrains.
As the development of SoC design technological means and more and more diversified application demand, SoC architecture are more and more multiple
Miscellaneous, chip-scale is more and more huger.The simulating, verifying difficulty of super large-scale integration gate level netlist is increasing, is consumed
Time is increasingly longer, the serious progress for hindering verification work, is the work of designer and verification personnel very headache.
For example, using the server of a 64 core 128G memories as verification platform, verification target is about 100,000,000 gate leves
SoC netlists, matching timing message file, emulation tool compilation process need about 40 minutes；During simulation run, processor is read simultaneously
Performing an instruction needs about 5 minutes.So, the program of 100 registers of a configuration, about 250 instructions are performed, rear imitate needs
20 hours of offer.It is not difficult to find out, the simulation velocity of super large-scale integration gate level netlist is very slowly, it is necessary to there is method to add
The fast process, improves verification efficiency.
The content of the invention
In order to solve the problems, such as that the simulation velocity of super large-scale integration gate level netlist is very slow, the present invention proposes
A kind of accelerated method of super large-scale integration gate level netlist emulation, can shorten super large-scale integration with high degree
The simulation time of gate level netlist, improves verification efficiency.
A kind of accelerated method of super large-scale integration gate level netlist emulation proposed by the present invention, including
Step 1, the proving program progress to integrated circuit modules is individually designed, and screens effective register and carry out
Configuration forms the simulation excitation simplified；
Step 2, register is configured, using the simulation excitation simplified, emulation is carried out to the rtl code of SOC and is tested
Card, sets critical registers and material time point, obtains and preserve output valve of the critical registers in material time point；
Step 3, output valve and initial value are filtered out not in the output valve of material time point according to the critical registers preserved
Same critical registers；
Step 4, after gate level netlist simulation run starts, after integrated circuit respective modules are completed to reset and in work
In the preceding time, assignment is carried out to the critical registers screened in step 3 using the output valve of the critical registers of acquisition, so
After continue gate level netlist simulation work.
Preferably, the critical registers described in step 2 are the functional configuration registers of circuit modules；The pass
At the time of key time point is that the functional configuration register configuration of circuit modules finishes.
Preferably, after the output valve critical registers different from initial value are filtered out in step 3, according to the life of gate level netlist
Name rule, non-initialization value is assigned a value of by each output valve of the critical registers.
Preferably, it is follow-up various emulation is carried out based on the state to test after critical registers output valve successfully obtains in step 2
After the work of card starts, in the time after integrated circuit respective modules are completed to reset and before operation, acquisition is utilized
The output valve of critical registers carries out assignment to corresponding register, instead of register configuration process.
Proving program progress of the present invention to integrated circuit modules is individually designed, and screens effective register and carry out
Configuration forms the simulation excitation simplified, and can easily complete very much a degree of netlist emulation and accelerate work；Critical registers
After output valve successfully captures, the follow-up various work that simulating, verifying is carried out based on the state, can be omitted a series of registers
The process of configuration, high degree shorten the simulation time of super large-scale integration gate level netlist, improve verification efficiency.
Brief description of the drawings
Fig. 1 is the method flow schematic diagram of the present invention；
Fig. 2 is the contrast schematic diagram of acceleration effect of the present invention.
Embodiment
In order to make technical scheme and advantage more easily understand, below in conjunction with specific implementation case and attached drawing,
The present invention is described in further detail.
The accelerated method of a kind of super large-scale integration gate level netlist emulation of the present invention, as shown in Figure 1 including following
Step：
Step 1, the proving program progress to integrated circuit modules is individually designed, and screens effective register and carry out
Configuration forms the simulation excitation simplified；
Due to the limitation of time, super large-scale integration gate level netlist simulating, verifying target is mainly critical path or pass
Key IP, verification SoC are after rear end design is realized, whether path meets sequential, and whether IP can normally start.Normal conditions,
Gate level netlist simulating, verifying is all the simulation excitation using the most simple basis of different submodules.Complicated simulation excitation, such as greatly
Data carrying and calculating of scale etc., usually use in RTL level software emulation or hardware accelerator simulating, verifying stage.
Emulated for super large-scale integration gate level netlist, it is necessary to simplify simulation excitation, improve the validity of program.Essence
Simple principle is as follows：
(1) independence of module verification is improved.When front-end simulation is verified or returns verification, designer would generally will be more
A module, the simulation excitation of multiple functions are integrated into a proving program.But in gate level netlist simulating, verifying, it is necessary to simplify
Simulation excitation, individually verifies modules as far as possible, reduces unnecessary block coupled in series verification.So can be with the multiple moulds of parallel proof
Block, improves work efficiency.
(2) when verifying IP, do not configure for register of this authentication function without influence, do not configure and initialization value phase
Same register.The validity of proving program can be so improved, reduces idle work.
(3) when verifying data path, the data volume of transmission is as far as possible few.Because a large amount of, repeatability verification work should
Carried out on the verification platform of speed, such as hardware accelerator.When gate level netlist emulates, it is necessary to the clear and definite master of the verification
Syllabus, i.e., whether chip back-end realization meets timing requirements, covers more paths as far as possible.
The step is a relatively independent and simple step, be can be used alone, and improves gate leve net to a certain extent
The simulation velocity of table.
Step 2, register is configured, using the simulation excitation simplified, emulation is carried out to the rtl code of SOC and is tested
Card, sets critical registers and material time point, obtains and preserve output valve of the critical registers in material time point；
Whether the simulation excitation after verification is simplified in terms of this step 1 is correct, on the other hand obtains material time point as early as possible
When, the output of critical registers.Critical registers are needed with the basis for selecting difference identifying object of material time point and different verifications
Depending on asking.Under normal conditions, critical registers are the functional configuration registers of integrated circuit modules.Material time point is collection
At the time of being finished into the functional configuration register configurations of circuit modules.If identifying object is autonomous Design research and development or source generation
Code is open as it can be seen that the module belonging to functional configuration register is generally easy to position.Equally, according to the design hand of identifying object
Volume, is generally easily determined material time point, such as at the time of identifying object function is enabled, or identifying object initialization is completed
Moment.
Step 3, output valve and initial value are filtered out not in the output valve of material time point according to the critical registers preserved
Same critical registers；
According to the naming rule of gate level netlist, each output valve of these registers is assigned a value of non-initialization value.Separately
Outside, due in logic synthesis and physics realization, electric design automation (Electronic Design Automation) work
Tool can delete the non-loaded circuit in part according to actual functional capability situation optimization circuit.So according to the true of last gate level netlist
Situation, deletes the register being not present.
Here, illustrating why the step selects the critical registers output valve by rtl simulation acquisition and changed
The reason for critical registers output valve being directly acquired when writing, rather than being emulated from gate level netlist：
(1) rtl simulation speed is fast, so the speed of the buffer status obtained is also fast, it is efficient.
(2) since circuit is after physics realization, actual cell is far more than rtl description included in gate level netlist
Unit.So using emulator obtain a certain layer register information when, it is necessary to processing data volume it is huge, then therefrom sieve again
Select required information very difficult.Even, according to the experience of designer, when design scale is too big, simulation software at present
It is difficult to support directly to obtain the state for specifying register from gate level netlist.
Step 4, at the beginning of gate level netlist simulation run, using the critical registers of acquisition output valve to step
The critical registers screened in rapid 3 carry out assignment, then proceed by gate level netlist simulation work.
Assignment is carried out to the critical registers screened in step 3 using the output valve of the critical registers of acquisition, is made whole
A gate level netlist reaches the state that register configuration is completed, so as to continue subsequent authentication work, high degree shortens emulation
Run time.The assignment of critical registers is realized usually using force command statements in the step.Under normal circumstances, integrated
Circuit respective modules are completed to assign after resetting and to the critical registers screened in step 3 in the time before operation
Value, but if authentication module has special functional requirement, then need, in emulation, to navigate to more accurate time point, then
Perform the assignment of buffer status.
The step eliminates the gate level netlist simulation process of register configuration.The reasonability of this patent method processing is to establish
On the basis of the gate level netlist simulating, verifying of register configuration at least once has been correctly completed.Herein, " register configuration
Process " is finger processor instruction fetch, execute instruction, the process of the function register of configuration verification module.
As shown in Fig. 2, traditional simulation process is required to initialization and the configuration of register before each simulating, verifying,
The present invention is after critical registers output valve successfully obtains in step 2, the follow-up various works that simulating, verifying is carried out based on the state
Work is when starting, and is carried out assignment using the output valve of the critical registers of acquisition to corresponding register and is replaced register configuration mistake
Journey, each gate level netlist simulating, verifying work can be omitted a series of process of register configurations, and high degree shortens super
The simulation time of large scale integrated circuit gate level netlist, improves verification efficiency.
In order to preferably be illustrated to technical solution of the present invention, the present embodiment is directed to the SoC gate level netlists of about 100,000,000,
Matching timing message file, verification processing device complete the function of reading and writing data using DDR3 controllers.Wherein, the verification being related to
Point includes processor from flash instruction fetch, configures the register of DDR3 controllers, after DDR3 controllers complete initialization, writes
Enter 5 data and read to compare, terminate emulation.The instrument that software emulation uses is the VCS of synopsys companies.This patent is realized
Comprise the following steps that：
Step L1, simplifies the simulation excitation of DDR3 controller register configurations, improves the validity of proving program.Depositing
In the header file of device configuration, the register that input value is not equal to 0x0000_0000 is found；In simulation excitation, only these are posted
Storage is configured.
Step L2, the DDR3 controller register configuration simulation excitations simplified using step L1, to the rtl code of SoC
Emulated.Simulation run to DDR3 controller initialization completion signals it is effective when suspend.From the hierarchy of objectivies, i.e. DDR3 controllers
Interior register configuration module, wins the current output valve of all registers and preservation.
Step L3, from the information of step L2 preservations, filters out the register different from initial value.In this example, DDR3 controls
The initial value of device register processed is 0, only uses the register for looking for save value to be 1., will according to the naming rule of gate level netlist
The output valve force of each (bit) register that save value is 1 is 1, and deletes the deposit being not present after back-end realization
Device.
Step L4, deletes the configurator of DDR3 controller registers, after gate level netlist simulation run starts, treats that DDR3 is controlled
Device processed is completed after resetting, and before processor is to DDR3 read-write operations, utilizes the output valve of the critical registers of acquisition
Assignment is carried out to the critical registers screened in step 3.So far, processor can read instruction, directly be controlled using DDR3
Device, starts write-read data verification.
If during unused this method, DDR3 controllers configuration register totally 300, processor need to perform 415 instructions and complete
The configuration of DDR3 controllers, about 35 hours of simulation run time.If the emulation of simplifying using only step 1 in this patent method swashs
After encouraging, DDR3 controllers configuration register totally 120, processor need to perform the configuration that DDR3 controllers are completed in 231 instructions, imitate
True about 20 hours of run time, time shorten 42.3%.If after completely using this patent method, the configuration of DDR3 controllers is posted
Storage totally 1, processor need to perform the configuration that DDR3 controllers are completed in 44 instructions, about 4 hours of simulation run time, time
Shorten 82.8%.
The above, is only the embodiment in the present invention, but protection scope of the present invention is not limited thereto, and is appointed
What be familiar with the people of the technology disclosed herein technical scope in, it will be appreciated that the conversion or replacement expected, should all cover
Within the scope of the present invention, therefore, protection scope of the present invention should be subject to the protection domain of claims.
Claims (4)
1. a kind of accelerated method of super large-scale integration gate level netlist emulation, it is characterised in that comprise the following steps：
Step 1, the proving program progress to integrated circuit modules is individually designed, and screens effective register and matched somebody with somebody
Put, form the simulation excitation simplified；
Step 2, register is configured, using the simulation excitation simplified, simulating, verifying is carried out to the rtl code of SOC, if
Critical registers and material time point are put, obtains and preserves output valve of the critical registers in material time point；
Step 3, it is different from initial value to filter out output valve in the output valve of material time point according to the critical registers preserved
Critical registers；
Step 4, after gate level netlist simulation run starts, after integrated circuit respective modules are completed to reset and before operation
In time, assignment, Ran Houji are carried out to the critical registers screened in step 3 using the output valve of the critical registers of acquisition
It is continuous to carry out gate level netlist simulation work.
A kind of 2. accelerated method of super large-scale integration gate level netlist emulation as claimed in claim 1, it is characterised in that
Critical registers described in step 2 are the functional configuration registers of circuit modules；The material time point is circuit
At the time of the functional configuration register configuration of modules finishes.
3. a kind of accelerated method of super large-scale integration gate level netlist emulation as claimed in claim 1 or 2, its feature exist
In after the output valve critical registers different from initial value are filtered out in step 3, according to the naming rule of gate level netlist, by institute
Each output valve for the critical registers stated is assigned a value of non-initialization value.
A kind of 4. accelerated method of super large-scale integration gate level netlist emulation as claimed in claim 3, it is characterised in that step
After critical registers output valve successfully obtains in 2, after the follow-up various work based on state progress simulating, verifying start, collecting
Complete after resetting and in time before operation into circuit respective modules, utilize the output valve of the critical registers of acquisition
Assignment is carried out to corresponding register, instead of register configuration process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510342090.7A CN104899076B (en) | 2015-06-18 | 2015-06-18 | A kind of accelerated method of super large-scale integration gate level netlist emulation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510342090.7A CN104899076B (en) | 2015-06-18 | 2015-06-18 | A kind of accelerated method of super large-scale integration gate level netlist emulation |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104899076A CN104899076A (en) | 2015-09-09 |
| CN104899076B true CN104899076B (en) | 2018-04-27 |
Family
ID=54031754
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510342090.7A Active CN104899076B (en) | 2015-06-18 | 2015-06-18 | A kind of accelerated method of super large-scale integration gate level netlist emulation |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104899076B (en) |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105701294B (en) * | 2016-01-13 | 2018-12-25 | 盛科网络（苏州）有限公司 | Realize the method and system of chip complex engineering modification |
| CN105975664B (en) * | 2016-04-28 | 2019-01-18 | 福州瑞芯微电子股份有限公司 | A kind of appraisal procedure of chip power-consumption Evaluation Platform |
| CN105893707B (en) * | 2016-04-28 | 2019-06-07 | 福州瑞芯微电子股份有限公司 | A kind of SOC chip module verification and power consumption analysis method |
| CN110750946B (en) * | 2018-07-19 | 2023-08-18 | 澜至电子科技（成都）有限公司 | Simulation acceleration method and system for integrated circuit netlist |
| CN110580393B (en) * | 2019-09-09 | 2022-12-27 | 飞腾信息技术有限公司 | Method for quickly converging and establishing time after modification of gate-level netlist |
| CN111104348B (en) * | 2019-12-24 | 2021-10-26 | 江苏芯盛智能科技有限公司 | Simulation method and device for PCIe initialization process and related equipment |
| CN111427794B (en) * | 2020-04-03 | 2023-05-16 | 飞腾信息技术有限公司 | Method, system and medium for accelerating simulation of memory component netlist |
| CN112100952B (en) * | 2020-09-14 | 2021-06-22 | 海光信息技术股份有限公司 | Post-simulation method and device for integrated circuit, electronic equipment and storage medium |
| CN112417798B (en) * | 2020-11-27 | 2023-05-23 | 成都海光微电子技术有限公司 | Time sequence testing method and device, electronic equipment and storage medium |
| CN112613259B (en) * | 2020-12-18 | 2022-06-10 | 海光信息技术股份有限公司 | Post-simulation method and device for system on chip and electronic equipment |
| CN114841103B (en) * | 2022-07-01 | 2022-09-27 | 南昌大学 | Parallel simulation method, system, storage medium and equipment for gate-level circuit |
| CN115841089B (en) * | 2023-02-27 | 2023-05-02 | 合肥六角形半导体有限公司 | System-level chip verification platform and verification method based on UVM |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101183406A (en) * | 2007-12-25 | 2008-05-21 | 盛科网络（苏州）有限公司 | Method for establishing network chip module level function checking testing platform |
| CN101719170A (en) * | 2009-11-27 | 2010-06-02 | 深圳国微技术有限公司 | Simulation test method of integrated circuits |
| CN102110045A (en) * | 2009-12-24 | 2011-06-29 | 上海华虹集成电路有限责任公司 | Simulator for displaying debugging information in real time |
| CN103150440A (en) * | 2013-03-14 | 2013-06-12 | 福州瑞芯微电子有限公司 | Simulation method of module-level circuit netlist |
-
2015
- 2015-06-18 CN CN201510342090.7A patent/CN104899076B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101183406A (en) * | 2007-12-25 | 2008-05-21 | 盛科网络（苏州）有限公司 | Method for establishing network chip module level function checking testing platform |
| CN101719170A (en) * | 2009-11-27 | 2010-06-02 | 深圳国微技术有限公司 | Simulation test method of integrated circuits |
| CN102110045A (en) * | 2009-12-24 | 2011-06-29 | 上海华虹集成电路有限责任公司 | Simulator for displaying debugging information in real time |
| CN103150440A (en) * | 2013-03-14 | 2013-06-12 | 福州瑞芯微电子有限公司 | Simulation method of module-level circuit netlist |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104899076A (en) | 2015-09-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104899076B (en) | A kind of accelerated method of super large-scale integration gate level netlist emulation | |
| JP4994393B2 (en) | System and method for generating multiple models at different levels of abstraction from a single master model | |
| CN101719170B (en) | Simulation test method of integrated circuits | |
| US8898051B2 (en) | System and method for implementing a trace interface | |
| CN107256303A (en) | The method of quick obtaining numeral gate level circuit internal node simulation status | |
| CN110750946A (en) | Integrated circuit netlist simulation acceleration method and system thereof | |
| CN107895087A (en) | The method and system that the emulation of PLD module level automatically generates with code | |
| CN107533473A (en) | Efficient wave for emulation generates | |
| CN105893707B (en) | A kind of SOC chip module verification and power consumption analysis method | |
| CN105975664A (en) | Assessment method for chip power consumption assessment platform | |
| US8418099B2 (en) | Performance counters for integrated circuits | |
| CN108920825A (en) | A kind of SoC visual data manager based on IP kernel | |
| CN105760638B (en) | A method of accelerating SOC chip emulation | |
| CN107608231A (en) | A kind of adjustment method of target seeker stabilized platform | |
| CN111624475B (en) | Method and system for testing large-scale integrated circuit | |
| US10162915B2 (en) | Method and system for emulation of multiple electronic designs in a single testbench environment | |
| CN107784185B (en) | Method and device for extracting pseudo path in gate-level netlist and terminal equipment | |
| JP2009140388A (en) | Method for generating performance evaluation model, method for evaluating system performance, and device for generating performance evaluation model | |
| Sayinta et al. | A mixed abstraction level co-simulation case study using systemc for system on chip verification | |
| Gao et al. | Software and hardware co-verification technology based on virtual prototyping of RF SOC | |
| CN101017513A (en) | Simulating example producing method and device for integrated circuit element | |
| US20160085519A1 (en) | Determination of signals for readback from fpga | |
| CN110135572A (en) | It is a kind of that flexible CNN design method is trained based on SOC | |
| US20110238400A1 (en) | Device for a method of modelling a physical structure | |
| Zheng et al. | Fitvs: A fpga-based emulation tool for high-efficiency hardness evaluation |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20171129 Address after: 102412 Beijing City, Fangshan District Yan Village Yan Fu Road No. 1 No. 11 building 4 layer 402 Applicant after: Beijing Si Lang science and Technology Co.,Ltd. Address before: 100080 Zhongguancun East Road, Beijing, No. 95, No. Applicant before: Institute of Automation, Chinese Academy of Sciences |
|
| TA01 | Transfer of patent application right | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address |
Address after: 201306 building C, No. 888, Huanhu West 2nd Road, Lingang New District, China (Shanghai) pilot Free Trade Zone, Pudong New Area, Shanghai Patentee after: Shanghai Silang Technology Co.,Ltd. Address before: 102412 room 402, 4th floor, building 11, No. 1, Yanfu Road, Yancun Town, Fangshan District, Beijing Patentee before: Beijing Si Lang science and Technology Co.,Ltd. |
|
| CP03 | Change of name, title or address |