CN112542197A - Method and device for improving reading reliability of sensitive amplifier, storage medium and terminal - Google Patents
Method and device for improving reading reliability of sensitive amplifier, storage medium and terminal Download PDFInfo
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- CN112542197A CN112542197A CN202011589852.0A CN202011589852A CN112542197A CN 112542197 A CN112542197 A CN 112542197A CN 202011589852 A CN202011589852 A CN 202011589852A CN 112542197 A CN112542197 A CN 112542197A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
- G11C16/28—Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/08—Control thereof
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Abstract
The invention discloses a method, a device, a storage medium and a terminal for improving the reading reliability of a sensitive amplifier, wherein a path of additional current is superposed on the reference current of the sensitive amplifier, and the sum of the additional current and the current generated when 0V is applied to other storage units on the same bit line with a storage unit in a reading state is increased or decreased, so that the difference value of the bias current of the reference current and the bias current of the storage unit in the reading state is fixed and cannot be changed along with the change of temperature, the reliability of the sensitive amplifier under different temperatures is obviously improved, and the integral reliability of NOR Flash is improved.
Description
Technical Field
The invention relates to the technical field of sensitive amplifiers, in particular to a method, a device, a storage medium and a terminal for improving the reading reliability of a sensitive amplifier.
Background
A Sense amplifier (Sense amplifier) is an important circuit module inside a NOR Flash memory chip, and fig. 1 is a frame diagram of a common NOR Flash internal circuit module, and it can be seen that, if a Sense amplifier reads a memory cell inside a chip to distinguish whether the selected memory cell is data "1" or data "0", if the reliability of the Sense amplifier is a problem, the data inside the memory chip may be read incorrectly, which may cause a problem in an application with NOR Flash, and the consequences may be very serious.
As shown in fig. 2, the principle of the sense amplifier in NOR Flash is to compare the SA _ i2v voltage converted from the current-voltage conversion of the memory cell current biased in a specific state with the SA _ VREF voltage converted from the current-voltage conversion of the reference current (generally 10uA to 20 uA), if the cell current biased in a particular state is greater than the reference current (where the data stored in the NOR Flash memory cell is data "1"), SA _ i2v after the current-voltage transition will be less than SA _ VREF, and conversely, if the memory cell current biased in a particular state is less than the reference current (when the data stored in the NOR Flash memory cell is data "0"), SA _ i2v will be less than SA _ VREF, if the two currents are identical, SA _ i2v will be equal to SA _ VREF (the data stored inside the NOR Flash cell is a data not "0" but "1").
Fig. 3 is a schematic diagram of a conventional NOR Flash memory cell array. Each Bit line (abbreviated as BL) corresponds to a sense amplifier, and each Bit line is connected to the drain of a plurality of memory cells having respective word lines. One bit line in the box in fig. 3 is selected for explanation, and fig. 4 is a schematic diagram of each memory cell connected to one bit line, and the current Icell on this bit line is Icell in the box at the bottom right in fig. 2. Wherein Icell = Icell0+ Icell1+ Icell2+ Icell3+ Icell4+ Icell5+ Icell6+ Icell7, generally, word lines of the memory cells M1 to M7 in fig. 4 are all connected to 0V, and at the normal temperature, currents of the icells 1 to the Icell7 are small and are pA-level (threshold voltages of data "1" and data "0" memory cells in NOR Flash cells are both greater than 0V) and can be basically ignored, so the current of the memory cells biased in a specific state (read state) is Icell ≈ Icell0, and at this time, the circuit structure of the sense amplifier shown in fig. 2 is used without problems. However, at high temperature, Icell 1-Icell 7 are larger than normal temperature, especially in an actual NOR Flash product, the number of actually connected memory cells per bit line is generally 1024 (i.e. M0-M7 in fig. 4 are changed to M0-M1023 accordingly), that is, 1023 memory cells contribute current to Icell, if each of the memory cells with 0V word line connected thereto has 10nA of current, the current contributed to Icell end is 10.23uA, and is very close to 10 uA-20 uA of common reference current (Iref), which may cause abnormal operation of the sense amplifier, seriously reduce reliability of the sense amplifier in NOR Flash, and further reduce overall reliability of NOR Flash.
Therefore, the prior art still needs to be improved and developed.
Disclosure of Invention
The invention aims to provide a method, a device, a storage medium and a terminal for improving the reading reliability of a sensitive amplifier so as to improve the reliability of a NOR Flash sensitive amplifier.
The technical scheme of the invention is as follows: a method for improving the reading reliability of a sensitive amplifier specifically comprises the following steps:
obtaining the current of a storage unit biased in a specific state, and obtaining a bias voltage according to the current of the storage unit;
obtaining a comparison current, and obtaining a comparison voltage according to the comparison current, wherein the comparison current is equal to the sum of a reference current and an additional current, and the sum of the additional current and the current generated when 0V is applied to other memory cells on the same bit line as the memory cell is increased or decreased;
and comparing the bias voltage with the comparison voltage to obtain a comparison result, and reading out the data in the memory cell biased in a specific state according to the comparison result.
The method for improving the reading reliability of the sensitive amplifier is used, wherein the specific state is a reading state.
The method for improving the reading reliability of the sensitive amplifier is characterized in that the additional current is equal to the sum of currents generated when 0V is applied to other memory cells on the same bit line with the memory cell.
The method for improving the reading reliability of the sensitive amplifier is characterized in that the additional current is equal to the sum of currents generated when 0V is applied to all memory cells on one bit line in the NOR Flash, and the bit line and other bit lines in the NOR Flash have the same number of memory cells.
The method for improving the reading reliability of the sensitive amplifier comprises the following specific steps of obtaining a bias voltage according to the current of the memory cell: and obtaining a bias voltage through current-voltage conversion according to the current of the storage unit.
The method for improving the reading reliability of the sensitive amplifier comprises the following specific steps of: and obtaining a comparison voltage through current-voltage conversion according to the comparison current.
An apparatus for improving the read reliability of a sense amplifier, comprising:
the bias voltage acquisition module is used for acquiring the current biased to the storage unit in a specific state and obtaining bias voltage according to the current of the storage unit;
the comparison voltage acquisition module is used for acquiring comparison current and acquiring comparison voltage according to the comparison current, wherein the comparison current is equal to the sum of reference current and additional current, and the sum of the additional current and current generated when 0V is applied to other memory cells on the same bit line as the memory cell is increased or decreased;
and the comparison module is used for comparing the bias voltage with the comparison voltage to obtain a comparison result and reading out the data in the memory cell under the bias in a specific state according to the comparison result.
The device for improving the reading reliability of the sense amplifier is characterized in that a bit line is additionally arranged in the NOR Flash, the bit line and other bit lines in the NOR Flash have the same number of storage units, the sum of currents generated when 0V is applied to all the storage units on the bit line is calculated, and the sum of the currents is the additional current.
A storage medium having stored therein a computer program which, when run on a computer, causes the computer to perform any of the methods described above.
A terminal device comprising a processor and a memory, the memory having stored therein a computer program, the processor being configured to execute the method of any one of the preceding claims by calling the computer program stored in the memory.
The invention has the beneficial effects that: the invention provides a method, a device, a storage medium and a terminal for improving the reading reliability of a sensitive amplifier, wherein a path of additional current is superposed on the reference current of the sensitive amplifier, and the sum of the additional current and the current generated when 0V is applied to other storage units on the same bit line with a storage unit in a reading state is increased or decreased, so that the difference value of the bias current of the reference current and the bias current of the storage unit in the reading state is fixed and cannot be changed along with the change of temperature, the reliability of the sensitive amplifier under different temperatures is obviously improved, and the integral reliability of NOR Flash is improved.
Drawings
Fig. 1 is a block diagram of an internal circuit block of NOR Flash in the related art.
Fig. 2 is a schematic circuit diagram of a NOR Flash sense amplifier in the prior art.
FIG. 3 is a schematic diagram of a NOR Flash memory cell array in the prior art.
Fig. 4 is a schematic diagram of a memory cell connected to one bit line of NOR Flash in the prior art.
FIG. 5 is a flow chart of the steps of the method of the present invention for improving the read reliability of a sense amplifier.
FIG. 6 is a schematic diagram of a sense amplifier of the present invention.
FIG. 7 is a schematic diagram of the present invention in which one bit line is added to NOR Flash.
FIG. 8 is a schematic diagram of an apparatus for improving the read reliability of a sense amplifier according to the present invention.
Fig. 9 is a schematic diagram of a terminal in the present invention.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
As shown in fig. 5, a method for improving the read reliability of a sense amplifier specifically includes the following steps:
s1: obtaining a current Icell biased in a specific state, and obtaining a bias voltage SA _ i2v according to the current Icell of the memory cell;
s2: obtaining a comparison current, and obtaining a comparison voltage SA _ VREF according to the comparison current, wherein the comparison current is equal to the sum of a reference current Ivref and an additional current Iref _ cell, and the sum of the additional current Iref _ cell and the current generated when 0V is applied to other memory cells on the same bit line as the memory cell is increased or decreased;
s3: and comparing the bias voltage with the comparison voltage to obtain a comparison result, and reading out the data in the memory cell biased in a specific state according to the comparison result.
In certain embodiments, the particular state is a read state.
In some embodiments, the additional current Iref _ cell is equal to the sum of the currents generated when 0V is applied to other memory cells on the same bit line as the memory cell.
In some embodiments, as shown in fig. 7, the additional current Iref cell is equal to the sum of currents generated when 0V is applied to all memory cells disposed on one bit line in NOR Flash, which has the same number of memory cells as the other bit lines in NOR Flash.
As shown in fig. 6 and 7, it is more practical that the additional current Iref _ cell is equal to the sum of currents generated when 0V is applied to other memory cells on the same bit line as the memory cell, so that the difference between the comparison current and the current Icell of the memory cell biased in a specific state is fixed (because both currents are added to the sum of currents generated when 0V is applied to other memory cells on the same bit line as the memory cell), and does not change due to temperature change. However, since it is not clear which memory cell on the bit line is actually read during the actual read operation, it is difficult to obtain the sum of currents generated when 0V is applied to the other memory cells on the same bit line as the memory cell, so that in the actual operation, by adding a bit line in NOR Flash, which has the same number of memory cells as the other bit lines in NOR Flash, and by obtaining the sum of currents generated when 0V is applied to all the memory cells on the added bit line as an additional current Iref _ cell, although there is a certain error in the sum of currents generated when 0V is applied to the additional current Iref _ cell and the other memory cells on the same bit line as the memory cell (the source of the error is mainly 1. the additional current Iref _ cell is larger than the current generated when 0V is applied to one memory cell, if there are 1024 memory cells on the bit line, the sum of the currents generated when 1023 memory cells apply 0V should be calculated, but the actual calculation is the sum of the currents generated when 1024 memory cells apply 0V, but the error between the sum of the currents generated when 1024 memory cells apply 0V and the sum of the currents generated when 1023 memory cells apply 0V is small and can be basically ignored. 2. Because the memory cell on the added bit line and the memory cell on the bit line where the memory cell actually performing the read operation is located have various differences (there is a problem of consistency), because the difference causes an error in the sum of the calculated additional current Iref _ cell and the current generated when 0V is applied to the other memory cells on the same bit line as the memory cell), but the error basically does not affect the reliability of the sense amplifier when reading the data of the memory cell, the technical scheme can solve the reliability problem of the sense amplifier in the prior art when reading the data of the memory cell.
As shown in fig. 7 (if one bit line is connected with 1024 memory cells, the number of the memory cells in fig. 7 is correspondingly changed to 1024), no matter what temperature, the additional current Iref _ cell in fig. 7 is similar to the current of all the memory cells connected with 0V by word lines on the bit line required to be read in the memory cell array in the prior art (as shown in fig. 4), for example, Iref =10uA, Iref _ cell =0uA, Iref =10uA +0uA =10uA at normal temperature, and the current on one line in the memory cell array is the sum of Icell0+ other icells (Icell 1-Icell 7), and at this time, Iref _ cell = the sum of other icells, so the difference between Iref and the memory cell0 required to be read is fixed, and no matter normal temperature, high temperature or low temperature, by applying this method, the reliability of the sense amplifier at different temperatures is significantly improved, thereby improving the overall reliability of the Flash.
In some embodiments, in S1, the bias voltage SA _ i2v is obtained by current-to-voltage conversion according to the current Icell of the memory cell.
In some embodiments, in S2, the comparison voltage SA _ VRE is obtained by current-to-voltage conversion according to the comparison current.
As shown in fig. 8, an apparatus for improving the read reliability of a sense amplifier includes:
the bias voltage obtaining module 101 is configured to obtain a current biased to a memory cell in a specific state, and obtain a bias voltage according to the current of the memory cell;
the comparison voltage obtaining module 102 is configured to obtain a comparison current, and obtain a comparison voltage according to the comparison current, where the comparison current is equal to a sum of a reference current and an additional current, and the sum of the additional current and a current generated when 0V is applied to other memory cells on the same bit line as the memory cell is increased or decreased;
and the comparison module 103 compares the bias voltage with the comparison voltage to obtain a comparison result, and reads out data in the memory cell under the specific state according to the comparison result.
Referring to fig. 9, an embodiment of the present invention further provides a terminal. As shown, the terminal 300 includes a processor 301 and a memory 302. The processor 301 is electrically connected to the memory 302. The processor 301 is a control center of the terminal 300, connects various parts of the entire terminal using various interfaces and lines, and performs various functions of the terminal and processes data by running or calling a computer program stored in the memory 302 and calling data stored in the memory 302, thereby performing overall monitoring of the terminal 300.
In this embodiment, the processor 301 in the terminal 300 loads instructions corresponding to one or more processes of the computer program into the memory 302 according to the following steps, and the processor 301 runs the computer program stored in the memory 302, so as to implement various functions: obtaining the current of a storage unit biased in a specific state, and obtaining a bias voltage according to the current of the storage unit; obtaining a comparison current, and obtaining a comparison voltage according to the comparison current, wherein the comparison current is equal to the sum of a reference current and an additional current, and the sum of the additional current and the current generated when 0V is applied to other memory cells on the same bit line as the memory cell is increased or decreased; and comparing the bias voltage with the comparison voltage to obtain a comparison result, and reading out the data in the memory cell biased in a specific state according to the comparison result.
Memory 302 may be used to store computer programs and data. The memory 302 stores computer programs containing instructions executable in the processor. The computer program may constitute various functional modules. The processor 301 executes various functional applications and data processing by calling a computer program stored in the memory 302.
An embodiment of the present application provides a storage medium, and when being executed by a processor, the computer program performs a method in any optional implementation manner of the foregoing embodiment to implement the following functions: obtaining the current of a storage unit biased in a specific state, and obtaining a bias voltage according to the current of the storage unit; obtaining a comparison current, and obtaining a comparison voltage according to the comparison current, wherein the comparison current is equal to the sum of a reference current and an additional current, and the sum of the additional current and the current generated when 0V is applied to other memory cells on the same bit line as the memory cell is increased or decreased; and comparing the bias voltage with the comparison voltage to obtain a comparison result, and reading out the data in the memory cell biased in a specific state according to the comparison result. The storage medium may be implemented by any type of volatile or nonvolatile storage device or combination thereof, such as a Static Random Access Memory (SRAM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), an Erasable Programmable Read-Only Memory (EPROM), a Programmable Read-Only Memory (PROM), a Read-Only Memory (ROM), a magnetic Memory, a flash Memory, a magnetic disk, or an optical disk.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.
In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. A method for improving the reading reliability of a sensitive amplifier is characterized by comprising the following steps:
obtaining the current of a storage unit biased in a specific state, and obtaining a bias voltage according to the current of the storage unit;
obtaining a comparison current, and obtaining a comparison voltage according to the comparison current, wherein the comparison current is equal to the sum of a reference current and an additional current, and the sum of the additional current and the current generated when 0V is applied to other memory cells on the same bit line as the memory cell is increased or decreased;
and comparing the bias voltage with the comparison voltage to obtain a comparison result, and reading out the data in the memory cell biased in a specific state according to the comparison result.
2. The method of claim 1, wherein the specific state is a read state.
3. The method of claim 1, wherein the additional current is equal to a sum of currents generated when 0V is applied to other memory cells on a same bitline as the memory cell.
4. The method of claim 1, wherein the additional current is equal to a sum of currents generated when 0V is applied to all memory cells disposed on one bit line in NOR Flash, the bit line having the same number of memory cells as other bit lines in NOR Flash.
5. The method of claim 1, wherein the obtaining the bias voltage according to the current of the memory cell comprises: and obtaining a bias voltage through current-voltage conversion according to the current of the storage unit.
6. The method of claim 1, wherein the step of obtaining the comparison voltage according to the comparison current comprises the following steps: and obtaining a comparison voltage through current-voltage conversion according to the comparison current.
7. An apparatus for improving the read reliability of a sense amplifier, comprising:
the bias voltage acquisition module is used for acquiring the current biased to the storage unit in a specific state and obtaining bias voltage according to the current of the storage unit;
the comparison voltage acquisition module is used for acquiring comparison current and acquiring comparison voltage according to the comparison current, wherein the comparison current is equal to the sum of reference current and additional current, and the sum of the additional current and current generated when 0V is applied to other memory cells on the same bit line as the memory cell is increased or decreased;
and the comparison module is used for comparing the bias voltage with the comparison voltage to obtain a comparison result and reading out the data in the memory cell under the bias in a specific state according to the comparison result.
8. The apparatus of claim 7, wherein a bit line is added in the NOR Flash, the bit line has the same number of memory cells as other bit lines in the NOR Flash, and a sum of currents generated when 0V is applied to all the memory cells on the bit line is calculated, and the sum of the currents is an additional current.
9. A storage medium having stored thereon a computer program which, when run on a computer, causes the computer to perform the method of any one of claims 1 to 6.
10. A terminal device, characterized in that it comprises a processor and a memory, in which a computer program is stored, said processor being adapted to execute the method of any one of claims 1 to 6 by calling said computer program stored in said memory.
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| CN111782145A (en) * | 2020-06-30 | 2020-10-16 | 深圳市芯天下技术有限公司 | Answer-type or-type flash memory digital verification method, system, storage medium and terminal |
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| US20050213387A1 (en) * | 2004-03-29 | 2005-09-29 | Renesas Technology Corp. | Semiconductor memory device enhancing reliability in data reading |
| JP2008097758A (en) * | 2006-10-13 | 2008-04-24 | Renesas Technology Corp | Semiconductor memory device |
| JP2013246857A (en) * | 2012-05-29 | 2013-12-09 | Rohm Co Ltd | Semiconductor storage device, on-vehicle equipment, and vehicle |
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