CN102568578A - Semiconductor storing apparatus, testing method thereof, and controlling method thereof - Google Patents
Semiconductor storing apparatus, testing method thereof, and controlling method thereof Download PDFInfo
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- CN102568578A CN102568578A CN2010105792672A CN201010579267A CN102568578A CN 102568578 A CN102568578 A CN 102568578A CN 2010105792672 A CN2010105792672 A CN 2010105792672A CN 201010579267 A CN201010579267 A CN 201010579267A CN 102568578 A CN102568578 A CN 102568578A
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Abstract
The invention discloses a semiconductor storing apparatus, a testing method thereof, and a controlling method thereof. According to the invention, a variable voltage is inputted into a memory unit control grid. The voltage level of the voltage in the control grid can be changed from a voltage level applied for normal memory unit operations (for example reading and writing operations) to a voltage level used for detecting memory apparatus defects. During a test, the voltage level applied to the control grid is lower than that applied to a second terminal (for example a drain terminal) of the memory unit. In some embodiments of the invention, in defect tests, negative voltage is applied to the control grid, and positive voltage is applied to the drain terminal, such that the existence of leakage current defect from grid to drain can be revealed.
Description
Technical field
The invention relates to a kind of semiconductor storage, and particularly relevant for a kind of semiconductor storage and method of testing and control method.
Background technology
Electronic memory device is known, and can in various electronic systems, come to light usually.For example, electronic memory device (representing with computer memory sometimes) can come to light in computing machine and other calculation elements.Various separate types or independent electronic storage arrangement are also known, for example storage card or solid-state data storage system.For example, using a kind of separate type storage card to belong in digital camera or in order to the film that storage utilizes digital VTR to record with storing images knows.
Most electronic memory device can be classified into volatibility or non-volatile.The volatile, electronic memory device is normally a kind of to need electric power so that preserve the device of the information that stores.One example of volatile, electronic memory device is the computer memory device of static RAM (SRAM) or dynamic RAM (DRAM); It only preserves the data that store when computer booting, and it can lose the data that store when computer shutdown or outage.In comparison, the non-volatile electronic memory device is normally a kind of can be at the device that does not have to preserve under the situation of external power source the data that store.One example of nonvolatile memory is a flash memory.The flash memory of two main patterns is NOR flash memory and nand flash memory.
A kind of typical NOR flash cell comprises floating grid transistor, like Fig. 1 and shown in Figure 2.The NOR flash cell has the suitable narrow space between grid and drain electrode.Yet the NOR flash memory device uses quite high voltage to give memory cell for programming and erase operation.Generally speaking, being located at the grid of the floating grid transistor within the storage unit and the defective workmanship of drain electrode can easily respond to generation programming fault, wipe fault and/or some other fault.Therefore, semiconductor memory manufacturer carries out the loop test in advance of a plurality of bouts usually, in order to detect and to screen most defectives as far as possible, in order to before delivery, to reach the target that reduces the fault ratio.Because carrying out the loop test in advance of a plurality of bouts can cause extra cost and reduce the test carrying capacity; So for semiconductor memory manufacturer; For quality and the cost of attempting the balance semiconductor storage, suitable method of testing becomes important key point.
Therefore, be to seek on the ideal in order to the new method of measuring semiconductor memory storage, it will allow the improvement of quality and/or the minimizing of the cost relevant with test procedure.
Summary of the invention
The invention relates to a kind of System and method in order to the measuring semiconductor memory storage.Use System and method for of the present invention, can detect and eliminate defective about the grid within the floating grid transistor of semiconductor storage to drain short circuit.For example; According to the System and method for that is illustrated in this; For example before delivery, can eliminate in the manufacturing environment of these defectives; Can easily detect transistorized grid (or word line) and the crossing defective of the current potential between the drain electrode (or bit line) in memory array, can reduce testing cost and to improve testing efficiency.
According to a first aspect of the invention, propose a kind of method of testing of semiconductor storage, it can comprise and applies first voltage to the first call wire, and it is transistor drain or the source terminal that is connected to the memory cell of semiconductor storage.The method also comprises and applies second voltage to the second call wire, and it is the transistorized grid that is connected to the memory cell of semiconductor storage.First and second voltage application is to be performed so that first call wire is in the voltage potential that is higher than second call wire.The method more comprises at least, and part determine whether defective comes across semiconductor storage, and first and second voltage is to be applied to each call wire based on the level of the electric current of second call wire.
In certain embodiments, semiconductor storage can be a kind of NOR flash memory, and other embodiment can comprise the semiconductor storage of other patterns, comprises for example nand flash memory.In certain embodiments, first call wire can be a bit line, and second call wire can be a word line.Perhaps, first and second call wire can be included in the call wire of other combinations in the memory array.For example, first and second call wire can be respectively global bit line and word line, or is respectively global bit line and Overall word line, or is respectively bit line and Overall word line.
In certain embodiments, the high voltage on first call wire can be reached through applying negative voltage to the second call wire.
In certain embodiments, the method comprises detecting one grid to the defective that drains, and for example is diode-add-resistance pattern defective and/or resistance pattern defective.
According to a second aspect of the invention, propose a kind of semiconductor storage, it can comprise memory array, and it comprises a memory cell, and one is connected to first call wire of memory cell, and one be connected to memory cell second call wire.Semiconductor storage also can comprise a circuit in order to positive voltage to the first call wire to be provided and in order to optionally to provide in positive voltage and the negative voltage any to second call wire.This circuit can be designed in order to negative voltage to be provided during test procedure, and positive voltage was provided during the fetch program.
In certain embodiments, this circuit can comprise: first input end, in order to receive first control signal; Second input terminal is in order to receive second control signal; And lead-out terminal, in order to export an output voltage according to first and second control signal.The transistor seconds that some embodiment of sort circuit can more comprise the first transistor, be connected in series with the first transistor; And the 3rd transistor that is connected in parallel with the first transistor; Each grid that is connected with in it in this first and second transistor receives first control signal, and the 3rd transistor is connected to receive second control signal in its grid.The first transistor can be connected receiving positive voltage in its source electrode, and transistor seconds can be connected to receive negative supply voltage in its source electrode.
In certain embodiments, test procedure can allow the detecting of the leakage current defective in the memory array between first and second call wire.
According to a third aspect of the invention we, propose a kind of semiconductor storage, it can comprise memory array, and it comprises floating grid transistor, is connected to the word line of the grid of floating grid transistor, and the bit line that is connected to the drain electrode of floating grid transistor.Semiconductor storage also can comprise a circuit in order to positive voltage to the first call wire to be provided and in order to optionally to provide in positive voltage and the negative voltage any to word line.This circuit can be designed in order to negative voltage to be provided during test procedure, and positive voltage was provided during the fetch program.
In certain embodiments, this circuit can comprise: first input end, in order to receive first control signal; Second input terminal is in order to receive second control signal; And lead-out terminal, in order to export an output voltage to word line according to first and second control signal.Some embodiment of sort circuit can more comprise the first transistor, the transistor seconds that is connected in series with the first transistor and the 3rd transistor that is connected in parallel with the first transistor.First and second transistor can be connected receiving first control signal in its each grid, and the 3rd transistor can be connected to receive second control signal in its grid.The first transistor can be connected receiving positive voltage in its source electrode, and transistor seconds can be connected to receive negative supply voltage in its source electrode.
In certain embodiments, test procedure can allow the detecting of the leakage current defective in the memory array between bit line and word line.
According to a forth aspect of the invention; Propose a kind of method, in order to the control semiconductor storage, it comprises memory array; Memory array comprises memory cell, is connected to first call wire of memory cell, and second call wire that is connected to memory cell.The method can comprise and applies positive voltage to the first call wire, and optionally applies one of them voltage level to the second call wire.At least one voltage level is preferably and is lower than the positive voltage that is applied to first call wire.The method more comprises: when first call wire is when being in the voltage potential that is higher than second call wire, part is based on the level of the electric current of second call wire at least, and whether the detecting defective appears in the semiconductor storage.
In certain embodiments, memory cell can comprise transistor, and it has the drain electrode that is connected to first call wire, and the grid that is connected to second call wire.Therefore, apply positive voltage to the first call wire and comprise and apply positive voltage, and selectivity applies one of them voltage level to the second call wire and comprises and optionally apply one of them voltage level to grid to drain electrode.
In certain embodiments, whether whether the detecting defective appear at and can comprise detecting grid to the defective that drains in the semiconductor storage and appear in the semiconductor storage, for example diode-add-defective of resistance pattern and/or the defective of resistance pattern.
For there is better understanding above-mentioned and other aspects of the present invention, hereinafter is special lifts preferred embodiment, and cooperates appended graphicly, elaborates as follows:
Description of drawings
Fig. 1 shows the summary view of existing floating grid transistor.
The sectional view of the floating grid transistor of Fig. 2 displayed map 1.
Fig. 3 shows the calcspar according to the storage arrangement 100 of embodiments of the invention.
The more detailed synoptic diagram of the demonstration part of the memory array of Fig. 4 displayed map 3.
Fig. 5 show have diode-add-the summary view of the memory cell of the memory array of Fig. 4 of resistive defects.
Fig. 6 shows the summary view of memory cell of the memory array of the Fig. 4 with resistive defects.
The summary view of the test circuit of the storage arrangement of Fig. 7 displayed map 3.
Fig. 8 show have diode-add-the summary view of the memory cell of Fig. 5 of resistive defects, in order to its drain current path to be described.
Fig. 9 shows the summary view of the memory cell of the Fig. 6 with resistive defects, in order to its drain current path to be described.
[main element symbol description]
+ V: positive voltage
WL: word line
BL: bit line
-V: negative supply voltage
PA: first control signal
NA: second control signal
Q1, Q2, Q3: transistor
LP1: drain current path
LP2: drain current path
100: storage arrangement
102: memory array
104: word line (WL) code translator
106: bit line (BL) code translator
108: logical circuit
110: positive high voltage source
112: the negative high-voltage source
114: test circuit
120: flash cell
130: diode/diode defective
132: resistance
134: resistance
Embodiment
Fig. 3 shows the calcspar according to the storage arrangement 100 of the embodiment of the invention.Storage arrangement 100 can comprise a memory array 102, a word line (WL) code translator 104 and bit line (BL) code translator 106.Storage arrangement 100 also can comprise the logical circuit 108 that supplies user function (for example read, programming and erase feature) usefulness.Storage arrangement 100 also can comprise positive high voltage source 110 and a negative high-voltage source 112, for example a voltage pump circuit.Storage arrangement 100 can more comprise test circuit 114, and it will be illustrated further in following.
The more detailed maps of the demonstration part of Fig. 4 display-memory array 102.Memory array 102 comprises a plurality of flash cells 120, is configured to the NOR flash memory structure.Memory array 102 also comprises multiple bit lines (bit line n to bit line n+3 be shown); Many word lines (word line n to word line n+3 be shown); And many power leads, it allows the communication between the element of memory cell 120 storage arrangement 100 outside with being positioned at memory array 102 (for example WL code translator 104, BL code translator 106, logical circuit 108, just high voltage source 110, negative high-voltage source 112 and test circuit 114).Below table 1 show to supply programming, wipe and the summary of the voltage level of the memory cell 120 that read operation is used.
Table 1
Fig. 5 and Fig. 6 show the example of the pattern of the defective that can during the manufacturing of the memory cell 120 of memory array 102, produce.Fig. 5 shows the defective of representing with " diode-add-resistance " defective, and Fig. 6 shows the defective of representing with the resistance-type defective.Two kinds of defectives relate to unnecessary grid to drain leakage.In Fig. 5, unnecessary grid to drain leakage is symbolically to be shown as and resistance 132 diode in series 130, and it is illustrated in the drain electrode of contiguous flash cell 120 and the short circuit between the word line WL together.In Fig. 6, unnecessary grid to drain leakage is symbolically to be shown as resistance 134, and it is illustrated in the drain electrode of contiguous flash cell 120 and the short circuit between the word line WL.Test circuit 114 can be designed in order to this grid of detecting in flash cell 120 to the defective that drains.Below table 2 be presented at the summary of voltage level of the control memory cell 120 down of test circuit 114, in order to detect this grid in flash cell 120 to the defective that drains.
Table 2
As shown in table 2, can comprise the word line that applies a negative voltage to memory cell in order to the test of detecting grid to the defective that drains, apply the bit line of a little positive voltage (for example ,～1 volt) to memory cell simultaneously, trap and source electrode are set to earth level simultaneously.
Fig. 7 shows the synoptic diagram of the demonstration part of test circuit 114.The practical embodiments of test circuit 114 can comprise one of them about the circuit that is shown in Fig. 7 of every word line of storage arrangement 100.The circuit that is shown in Fig. 7 allows negative voltage to be applied to word line, uses for the detecting of the grid that is summarized in table 2 to drain short circuit.
Transistor Q3 is connected in parallel with transistor Q1.Clearer and more definite, the drain electrode of transistor Q3 is connected positive voltage+V, and the source electrode of transistor Q3 is connected to the drain electrode of lead-out terminal and transistor Q1 and Q2.The grid of transistor Q3 is connected to one second input terminal, and it receives one second control signal NA.
The test circuit 114 that is shown in Fig. 7 can be the special operational circuit, and it can be by operation to export an adjustable output voltage V _ WL.Circuit 114 exportable one can be used for doing the positive voltage of read operation, or one can be used for doing test operation negative voltage, depend on the numerical value of first and second control signal PA and NA.Below table 3 be presented at summary in order to the voltage level that (reading) or negative (test) output voltage input and lead-out terminal as the circuit 114 of signal V_WL just is being provided.
Table 3
According to a preferred embodiment, test circuit 114 is operated to provide a negative voltage V_WL (being associated with the voltage level of bit-line voltage) as a word line voltage so that detect a grid to the defective that drains, for example be shown in Fig. 5 and Fig. 6 those.Fig. 8 and Fig. 9 explicit declaration use the test operation of negative word line WL voltage how in the memory array of for example memory array 102, can detect the synoptic diagram of grid to drain short circuit fault effectively.
Referring to Fig. 8, with the voltage level of bit line BL comparatively speaking, can manifest a kind of diode-add-resistive defects, through test circuit 114 to applying of the relative negative voltage level of word line WL as combining Fig. 5 illustrated.Arrow LP1 shows because diode-add-existence of resistive defects allows the drain current path of electric current leakage.Applying negative word line WL voltage can cause flowing along the electric current of drain current path LP1.With the electric current that is produced of the existence of representing diode-add-resistive defects, can be calculated according to expression formula 1:
In expression formula 1, I
WLBe word line current, V
BLBe bit line BL voltage, V
WLBe word line WL voltage, V
ThBe the diode defective threshold voltage of diode defective 130, and R is the resistance of defect resistance 132.
About a specific examples, 1 volt voltage V
BLCan be applied to bit line BL, and-3 volts negative V
WLVoltage is to be applied to word line WL.Therefore, the relative voltage of bit line BL is to be higher than word line WL to reach 4 volts.Therefore, for example, about having 2 volts diode defective threshold voltage V
ThDiode defective 130 and the about resistive defects of 200K ohm, the electric current of the about 10 μ amperes on word line WL is shown in expression the existence of the diode of Fig. 8-add-resistive defects.Likewise, the electric current of the about 5 μ amperes on word line WL will be represented the existence of diode-add-resistive defects, and it comprises the diode defective threshold voltage V with 3 volts
ThDiode defective 130 and the about resistive defects of 200K ohm.On the other hand, if do not have grid, then will there be electric current to be positioned on the word line WL to the defective that drains.
Then with reference to Fig. 9, with the voltage level of bit line BL comparatively speaking, through the applying also can appear and combine the illustrated resistive defects of Fig. 6 to the relative negative voltage level of word line WL of test circuit 114.Arrow LP2 shows the drain current path that allows the electric current leakage owing to the existence of resistive defects.Applying negative word line WL voltage can cause flowing along the electric current of drain current path LP2.The electric current that is produced of the existence of representing resistive defects can be calculated according to expression formula 2:
In expression formula 2, I
WLBe word line current, V
BLFor bit line BL voltage, VWL are word line WL voltage, and R is the resistance of defect resistance 134.
About a specific examples, 1 volt voltage V
BLCan be applied to bit line BL, and-3 volts negative V
WLVoltage is to be applied to word line WL.Therefore, the relative voltage of bit line BL is to be higher than word line WL to reach 4 volts.Therefore, for example, about the resistive defects of about 500K ohm, the electric current I of the about 8 μ amperes on word line WL
WLExpression is shown in the existence of the resistive defects of Fig. 9.Likewise, under the situation of the approximately existence of the resistive defects of 500K ohm ,-8 volts negative V to the word line WL
WLVoltage application will cause the electric current I of the about 18 μ amperes on word line WL
WLOn the other hand, if do not have grid, then will not have electric current on word line WL to the defective that drains.
Test macro that is disclosed and method also between all call wires (for example between word line and bit line; Between word line and global bit line; Between Overall word line to global bit line, and between Overall word line to bit line) the induction defective workmanship detecting that generates leakage current appear effectively.About various manufacturing defect; For example diode defective, resistive defects or hybrid defective; The suitable level of negative high-voltage in order to detecting grid to drain leakage can be selected by those skilled in the art, in order to through applying the quantity that suitable bigger voltage differences suitably amplifies leakage current.
All word lines of individual segment (or block) unit through a kind of adjustable negative voltage to storer is provided read memory array simultaneously, can significantly shorten section (or block) the needed time of unit in order to testing memory.Use this configuration,, can detect grid Anywhere within section (or block) unit at storer to the defective that drains through reading a word line of individual segment (or block) unit.
Test macro that is disclosed and method are not the application that is restricted to the NOR flash memory, but also can be applied to any other storer, such as nand flash memory.
In sum, though the present invention discloses as above with preferred embodiment, so it is not in order to limit the present invention.Those skilled in the art are not breaking away from the spirit and scope of the present invention, when doing various changes and retouching.Therefore, protection scope of the present invention is when looking being as the criterion that the claim scope of enclosing defined.
In addition, meet 37C.F.R.1.77 or organized prompting is provided in addition in the chapter title system that this provided.These titles should not made restriction or characterization to any claim scope that originates from this disclosure that is set forth in of the present invention.For example in detail, though title is mentioned " technical field under the invention ", these claim scopes should not be subject to selected language under this title, so that so-called technical field to be described.Again, in this disclosure, the explanation of background technology is not interpreted into admits that this technology is to belong to prior art for any invention." brief summary of the invention " should not be considered to be the trend that the present invention that the claim scope in issue is proposed has characterization yet.Moreover any list of references of " embodiment " of the odd number in this disclosure is not used the novelty that only has single-point in this disclosure to argue.Restriction according to originating from the multiple claim of this disclosure possibly propose multiple invention, and therefore these claim scopes define the present invention and protected equivalence design thereof.In all instances, the category of these claim scopes should to they advantage and be considered according to this disclosure, but should be by in the restriction that title forces of this proposition.
Claims (24)
1. the method for testing of a semiconductor storage is characterized in that, comprises following steps:
Apply one first voltage to one, first call wire, this first call wire is connected to a transistorized drain electrode or a source electrode of a memory cell of this semiconductor storage;
Apply one second voltage to one, second call wire; This second call wire is connected to this transistorized grid of this memory cell of this semiconductor storage, wherein apply this first and second voltage and be performed so that this first call wire be in one be higher than this second call wire voltage potential; And
During applying this first and second voltage, part determines based on a level of an electric current of this second call wire whether a defective appears in this semiconductor storage at least.
2. method according to claim 1 is characterized in that this semiconductor storage comprises the NOR flash memory.
3. method according to claim 1 is characterized in that, this first call wire is a bit line.
4. method according to claim 3 is characterized in that, this second call wire is a word line.
5. method according to claim 1 is characterized in that, the step that applies this second voltage comprises and applies a negative voltage to this second call wire.
6. method according to claim 1 is characterized in that, this deciding step comprises: determine whether a grid to the defective that drains appears in this semiconductor storage.
7. method according to claim 6 is characterized in that, determines this grid to this step whether defective that drains occurs to comprise: determine whether a kind of diode-add-resistance pattern defective appears in this semiconductor storage.
8. method according to claim 6 is characterized in that, determines this grid to this step whether defective that drains occurs to comprise: determine whether a resistance pattern defective appears in this semiconductor storage.
9. a semiconductor storage is characterized in that, comprises:
One memory array, it comprises second call wire that first call wire and that a memory cell, is connected to this memory cell is connected to this memory cell;
One circuit, in order to circuit that positive voltage to this first lead is provided and positive voltage and negative voltage optionally be provided any to this second call wire;
Wherein this circuit is to be designed in order to this negative voltage to be provided during a test procedure, and this positive voltage was provided during a fetch program.
10. semiconductor storage according to claim 9 is characterized in that, this circuit comprises:
One first input end is in order to receive one first control signal;
One second input terminal is in order to receive one second control signal; And
One lead-out terminal is in order to export an output voltage according to this first and second control signal.
11. semiconductor storage according to claim 10 is characterized in that, this circuit more comprises:
One the first transistor;
One transistor seconds is connected in series with this first transistor;
One the 3rd transistor is connected in parallel with this first transistor,
Wherein this first and second transistor is connected receiving this first control signal in its each grid, and
Wherein the 3rd transistor is connected to receive this second control signal in its grid.
12. semiconductor storage according to claim 11 is characterized in that, this first transistor is connected receiving a positive voltage in its source electrode, and wherein this transistor seconds is connected to receive a negative supply voltage in its source electrode.
13. semiconductor storage according to claim 9 is characterized in that, this test procedure allows the detecting of a leakage current defective of this memory array between this first and second call wire.
14. a semiconductor storage is characterized in that, comprises:
One memory array, it comprises the word line that bit line and that a floating grid transistor, is connected to the drain electrode of this floating grid transistor is connected to the grid of this floating grid transistor;
One circuit, in order to circuit that positive voltage to this bit line is provided and positive voltage and negative voltage optionally be provided any to this word line;
Wherein this circuit is to be designed in order to this negative voltage to be provided during a test procedure, and this positive voltage was provided during a fetch program.
15. semiconductor storage according to claim 14 is characterized in that, this circuit comprises:
One first input end is in order to receive one first control signal;
One second input terminal is in order to receive one second control signal; And
One lead-out terminal is in order to export an output voltage to this word line according to this first and second control signal.
16. semiconductor storage according to claim 15 is characterized in that, this circuit more comprises:
One the first transistor;
One transistor seconds is connected in series with this first transistor;
One the 3rd transistor is connected in parallel with this first transistor,
Wherein this first and second transistor is connected receiving this first control signal in its each grid, and
Wherein the 3rd transistor is connected to receive this second control signal in its grid.
17. semiconductor storage according to claim 16 is characterized in that, this first transistor is connected receiving a positive voltage in its source electrode, and wherein this transistor seconds is connected to receive a negative supply voltage in its source electrode.
18. semiconductor storage according to claim 14 is characterized in that, this test procedure allows the detecting of the leakage current defective in this memory array between this bit line and this word line.
19. the control method of a semiconductor storage; This semiconductor storage comprises a memory array; This memory array comprises a memory cell; One is connected to first call wire of this memory cell, and one be connected to this memory cell second call wire, the method includes the steps of:
Apply a positive voltage to this first call wire;
One of them that optionally applies a plurality of voltage levels be to this second call wire, and wherein at least one of those voltage levels is to be lower than this positive voltage that is applied to this first call wire; And
When this first call wire was in a voltage potential that is higher than this second call wire, whether part was detected a defective and is appeared in this semiconductor storage based on a level of an electric current of this second call wire at least.
20. method according to claim 19; It is characterized in that; This memory cell comprises a transistor; It has one be connected to this first call wire drain electrode and be connected to the grid of this second call wire comprise so that apply the step of this positive voltage to this first call wire: apply this positive voltage and drain to this, and one of them step to this second call wire that optionally applies those voltage levels comprises: one of them that optionally applies those voltage levels is to this grid.
21. method according to claim 20 is characterized in that, this first call wire is a bit line, and wherein this second call wire is a word line.
22. whether method according to claim 19 is characterized in that, detect the step whether this defective appear in this semiconductor storage and comprise: detect a grid to the defective that drains and come across in this semiconductor storage.
23. method according to claim 22 is characterized in that, determines this grid to the step whether defective that drains occurs to comprise: determine whether a kind of diode-add-resistance pattern defective comes across in this semiconductor storage.
24. method according to claim 22 is characterized in that, determines this grid to the step whether defective that drains occurs to comprise: determine whether a resistance pattern defective comes across in this semiconductor storage.
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| CN102867544A (en) * | 2012-09-19 | 2013-01-09 | 上海宏力半导体制造有限公司 | Method of testing storage array and control device |
| CN104425036A (en) * | 2013-08-26 | 2015-03-18 | 北京兆易创新科技股份有限公司 | Method for enhancing electric leakage of storage array bit line defect |
| CN104575614A (en) * | 2015-02-10 | 2015-04-29 | 武汉新芯集成电路制造有限公司 | Invalid screening method of memory units |
| CN105118530A (en) * | 2015-09-12 | 2015-12-02 | 上海华虹宏力半导体制造有限公司 | Testing method for allowing flash memory units to read voltage in wafer-level testing and wafer-level testing |
| CN110706732A (en) * | 2019-10-14 | 2020-01-17 | 长江存储科技有限责任公司 | Failure analysis method of memory chip |
| CN111445938A (en) * | 2020-03-26 | 2020-07-24 | 北京大学 | Coding type flash memory structure and data processing method |
| CN113012745A (en) * | 2021-03-23 | 2021-06-22 | 长鑫存储技术有限公司 | Memory detection method and detection device |
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| CN104425036A (en) * | 2013-08-26 | 2015-03-18 | 北京兆易创新科技股份有限公司 | Method for enhancing electric leakage of storage array bit line defect |
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| CN105118530A (en) * | 2015-09-12 | 2015-12-02 | 上海华虹宏力半导体制造有限公司 | Testing method for allowing flash memory units to read voltage in wafer-level testing and wafer-level testing |
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| CN110706732A (en) * | 2019-10-14 | 2020-01-17 | 长江存储科技有限责任公司 | Failure analysis method of memory chip |
| CN110706732B (en) * | 2019-10-14 | 2021-04-13 | 长江存储科技有限责任公司 | Failure analysis method of memory chip |
| CN111445938A (en) * | 2020-03-26 | 2020-07-24 | 北京大学 | Coding type flash memory structure and data processing method |
| CN111445938B (en) * | 2020-03-26 | 2022-03-18 | 北京大学 | Coding type flash memory structure and data processing method |
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