CN113409839A - Storage unit threshold voltage reading method and device, electronic equipment and storage medium - Google Patents
Storage unit threshold voltage reading method and device, electronic equipment and storage medium Download PDFInfo
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Abstract
The invention discloses a method and a device for reading threshold voltage of a storage unit, electronic equipment and a storage medium, wherein the method comprises the following steps: writing checkerboard data into the whole chip programming; adjusting the internal reference voltage of the chip, and recording the number of storage units with data change information in the adjustment process of the internal reference voltage of the chip and the addresses of the corresponding storage units; drawing a threshold voltage distribution graph according to the numerical value of the reference voltage and the number of the storage units with data change information under the corresponding reference voltage; the method for reading the threshold voltage of the storage unit can visually and accurately reflect the distribution condition of the threshold voltage in the storage unit in the chip, and visually show the data retention capability of the chip.
Description
Technical Field
The present disclosure relates to the field of chip technologies, and in particular, to a method and an apparatus for reading a threshold voltage of a memory cell, an electronic device, and a storage medium.
Background
With the development of the NOR FLASH technology, the physical size of the memory cell is smaller and smaller, the data retention capability of the memory cell is poorer and poorer, and the reliability test of the data retention capability of the NOR FLASH is more and more important. The memory cell data retention is generally evaluated by using the threshold voltage of the memory cell as a function of the baking time at high temperature. The Nor Flash data retention capability test is a very important test item for Flash reliability assessment.
In the prior art, an ATE tester is generally used to read the threshold voltage of a chip, and the reading process is as follows: programming all '0' data in a whole slice; and changing the internal READ reference voltage of the chip from low to high, and reading the total number of the memory cells with the lowest threshold voltage of data 0. The reading mode has the following defects: meanwhile, the retention capacity of one type of data in the stored data can only be READ, the change of the total amount of the data along with the voltage reference READ reference voltage can only be reflected, and the number of the storage units in a local reference voltage interval cannot be intuitively reflected.
In view of the above problems, no effective technical solution exists at present.
Disclosure of Invention
An object of the embodiments of the present application is to provide a method, a system, an electronic device, and a storage medium for reading a threshold voltage of a storage unit, which can visually and accurately reflect a distribution of the threshold voltage in the storage unit in a chip, thereby visually representing a data retention capability of the chip.
In a first aspect, an embodiment of the present application provides a method for reading a threshold voltage of a memory cell in NOR Flash, where the method includes:
s1, writing checkerboard data into the whole chip programming;
s2, adjusting the internal reference voltage of the chip, and recording the number of memory cells with data change information in the adjustment process of the internal reference voltage of the chip and the addresses of the corresponding memory cells;
s3, drawing a threshold voltage distribution diagram according to the value of the reference voltage and the number of the storage units with data change information under the corresponding reference voltage;
the data change information includes a change from 0 to 1 of data and a change from 1 to 0 of data.
The method for reading the threshold voltage of the memory cell, wherein the step S1 includes the following sub-steps:
s11, carrying out whole erasing treatment on the chip;
s12, programming and recording checkerboard data for the chip;
and S13, carrying out full-chip reading on the chip and checking the checkerboard data.
The method for reading the threshold voltage of the memory cell, wherein the step S2 includes the following sub-steps:
s21, adjusting the internal reference voltage of the chip in an incremental mode, and recording the number of memory cells with data of 0 in the chip under the corresponding reference voltage and the addresses of the corresponding memory cells;
and S22, adjusting the internal reference voltage of the chip in a descending manner, and recording the number of the memory cells with the data of 1 in the chip under the corresponding reference voltage and the addresses of the corresponding memory cells.
The method for reading the threshold voltage of the memory cell, wherein the step S21 includes the following sub-steps:
s211, changing the internal reference voltage of the chip according to the first set voltage;
s212, carrying out full-chip reading on the chip, acquiring the number of storage units of which the data in the storage array is converted into 0 under the current reference voltage, and recording the addresses of the corresponding storage units;
and S213, increasing the voltage value of the first setting voltage, judging whether the increased first setting voltage is smaller than the upper limit of the reference voltage regulation range, if not, ending, and if so, jumping to the step S211.
In the method for reading the threshold voltage of the memory cell, in step S212, the number of memory cells in which data in the memory array is converted into 0 under the current reference voltage is obtained by calculating the difference between the number of memory cells in which data in the whole chip obtained under the current reference voltage is 1 and the number of memory cells in which data in the whole chip obtained under the previous reference voltage is 1.
The method for reading the threshold voltage of the memory cell, wherein the step S22 includes the following sub-steps:
s221, changing the internal reference voltage of the chip according to a second set voltage;
s222, carrying out full-chip reading on the chip, acquiring the number of storage units of which the data in the storage array is converted into 1 under the current reference voltage, and recording the addresses of the corresponding storage units;
and S223, reducing the second setting voltage, judging whether the reduced second setting voltage is larger than the lower limit of the reference voltage regulation range, if not, ending, and if so, jumping to the step S221.
In the method for reading the threshold voltage of the memory cell, in step S3, a first threshold voltage distribution map and a second threshold voltage distribution map are respectively drawn according to the number of memory cells with data of 0 in the chip corresponding to the reference voltage recorded in step S21 and the number of memory cells with data of 1 in the chip corresponding to the reference voltage recorded in step S22.
In a second aspect, an embodiment of the present application further provides a memory cell threshold voltage reading apparatus, configured to read a threshold voltage of a memory cell in NOR Flash, including:
the programming module is used for programming and writing checkerboard data into the whole chip;
the voltage regulation module is used for regulating the reference voltage of the chip and regulating the internal reference voltage of the chip in an increasing or decreasing mode;
the data reading module reads and records the number of memory cells with data of 1 or 0 in the chip under different reference voltages and the addresses of the corresponding memory cells;
and the drawing module is used for drawing a threshold voltage distribution diagram according to the data acquired by the reading module.
In a third aspect, an embodiment of the present application further provides an electronic device, including a processor and a memory, where the memory stores computer-readable instructions, and when the computer-readable instructions are executed by the processor, the steps in the method as provided in the first aspect are executed.
In a fourth aspect, embodiments of the present application further provide a storage medium, on which a computer program is stored, where the computer program runs the steps in the method provided in the first aspect when executed by a processor.
Therefore, the threshold voltage reading method for the memory cell provided by the embodiment of the application provides a data basis for ensuring the measurement accuracy of the threshold voltage by programming and writing checkerboard data into the whole chip, adjusts the threshold voltage of the memory cell in the reference voltage reading chip in an increasing and decreasing mode, draws the limit voltage distribution diagram on the basis, can intuitively and accurately reflect the distribution condition of the threshold voltage in the memory cell in the chip, and realizes the visual representation of the data retention capability of the chip.
Drawings
Fig. 1 is a flowchart of a method for reading a threshold voltage of a memory cell according to an embodiment of the present disclosure.
Fig. 2 is a flowchart illustrating a step S21 in a method for reading a threshold voltage of a memory cell according to an embodiment of the present disclosure.
Fig. 3 is a flowchart illustrating a step S22 in a method for reading a threshold voltage of a memory cell according to an embodiment of the present disclosure.
Fig. 4 is a schematic structural diagram of a memory cell threshold voltage reading apparatus according to an embodiment of the present disclosure.
Fig. 5 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
In a first aspect, referring to fig. 1-3, fig. 1-3 illustrate a method for reading a threshold voltage of a memory cell in NOR Flash according to some embodiments of the present application, the method comprising:
s1, writing checkerboard data into the whole chip programming;
specifically, the checkerboard data is CKBD data, which means that the data of the memory cell is designed to be 0 and 1 alternately, that is, the data in the four directions of the data 0 is 1, and similarly, the data in the four directions of the data 1 is 0, the checkerboard data can effectively prevent the leakage of the memory cell from affecting the voltage measurement result of the adjacent memory cell, thereby improving the measurement accuracy of the threshold voltage.
S2, adjusting the internal reference voltage of the chip, and recording the number of memory cells with data change information in the adjustment process of the internal reference voltage of the chip and the addresses of the corresponding memory cells;
s3, drawing a threshold voltage distribution diagram according to the value of the reference voltage and the number of the storage units with data change information under the corresponding reference voltage;
the data change information includes a change from 0 to 1 of data and a change from 1 to 0 of data.
Wherein, since the data change information includes a change from 0 to 1 and a change from 1 to 0, the changes of the two data can respectively reflect the holding capacity of the memory unit in the chip for 1 and 0, specifically, the change of the data from 0 to 1 reflects the holding capacity for 0, and the change of the data from 1 to 0 reflects the holding capacity for 1.
In step S2, the read reference voltage inside the chip is adjusted, and the checkerboard data is not erased.
In some preferred embodiments, the adjustment of the reference voltage is a fixed value adjustment, that is, the reference voltage is quantitatively increased each time and then the current data condition is read, and the fixed value adjustment is beneficial to data arrangement to draw a distribution diagram, so that the distribution diagram can more effectively reflect the distribution condition of the whole threshold voltage of the chip.
According to the method for reading the threshold voltage of the storage unit, the chessboard data is written in through the whole programming of the chip to provide a data basis for ensuring the measurement precision of the threshold voltage, the threshold voltage of the storage unit in the reference voltage reading chip is adjusted in an increasing and decreasing mode, the distribution condition of the threshold voltage in the storage unit in the chip can be obtained, and the holding capacity of the storage unit to 0 and 1 can be reflected visually; in addition, the address of the storage unit corresponding to the threshold voltage is recorded, the address position of the storage unit can be tracked according to the threshold voltage, and assessment and partition assessment of the retention capacity of the storage unit in different areas are facilitated.
In some preferred embodiments, the threshold voltage distribution graph drawn in step S3 is a normal distribution graph, that is, a distribution graph drawn by using the threshold voltage as the abscissa and the number of the memory cells as the ordinate, and the distribution of the threshold voltage of the whole memory cells can be visually observed, so as to reflect the retention capability of the corresponding memory cells with respect to data 0 and/or data 1.
In some preferred embodiments, step S1 includes the following sub-steps:
s11, carrying out whole erasing treatment on the chip;
specifically, the chip is subjected to full-chip erasing by applying erasing voltage, and over-erasing detection and repair are performed, so that the memory unit is prevented from being in an over-erasing state to influence data programming.
S12, programming and recording checkerboard data to the chip, and enabling the data of the memory cells to be 0 and 1 to be alternately arranged, namely the data in the four directions of the upper direction, the lower direction, the left direction and the right direction of the data 0 are 1, and the data in the four directions of the upper direction, the lower direction, the left direction and the right direction of the data 1 are 0;
s13, carrying out whole-chip reading on the chip and checking the checkerboard data to ensure that the whole storage units of the chip are in checkerboard data distribution, if a non-checkerboard data area exists, programming and correcting the area, and then carrying out whole-chip reading and checking on the chip again until the checkerboard data is programmed on the whole chip.
In the chip programming process of the embodiment of the application, the whole erasing treatment is carried out before programming, so that the programming can be ensured to be smooth, the whole chip is read and verified after the programming is finished, the programming quality can be ensured, and the whole chip data is checkerboard data, so that the subsequent reading of the threshold voltage is facilitated.
In some preferred embodiments, step S2 includes the following sub-steps:
s21, adjusting the internal reference voltage of the chip in an incremental mode, and recording the number of memory cells with data of 0 in the chip under the corresponding reference voltage and the addresses of the corresponding memory cells;
the step is used for recording the number of the storage units which are changed from 1 to 0 in the data change information, and can be used for constructing a threshold voltage distribution diagram for reflecting the holding capacity of the chip pair 1.
And S22, adjusting the internal reference voltage of the chip in a descending manner, and recording the number of the memory cells with the data of 1 in the chip under the corresponding reference voltage and the addresses of the corresponding memory cells.
The step is used for recording the number of storage units which are changed from 0 to 1 in the data change information, and can be used for constructing a threshold voltage distribution diagram for reflecting the holding capacity of the chip to 0.
In some preferred embodiments, the reference voltage is adjusted in the range of 3V to 10V in steps S21 and S22.
Specifically, threshold voltages of storage units in NOR Flash are mainly and intensively distributed between 5V and 6V, so that the threshold voltage range of the whole storage unit can be effectively covered by setting 3V to 10V of reference voltage, and the accuracy and the coverage of data reading are ensured.
More specifically, in step S21, the threshold voltage reading is terminated when the reference voltage is set to 3V or more as the starting point and gradually increases to more than 10V.
More specifically, in step S22, the reading of the threshold voltage is terminated when the reference voltage is set to 10V or less from the start point and gradually decreased to less than 3V.
In some preferred embodiments, step S21 includes the following sub-steps:
s211, changing the internal reference voltage of the chip according to the first set voltage;
specifically, the initial value of the first setting voltage is defined as 3V, so that when the step S21 is executed for the first time, the internal reference voltage of the chip is changed to 3V, and the quality of the chip is qualified, and in this case, all or most of the memory cell data is represented as 1; therefore, the voltage value of the first set voltage is increased upwards to read the first threshold voltage, the first threshold voltage of the whole memory cell can be covered, and the holding capacity of the whole memory cell to 1 is clearly reflected.
S212, carrying out full-chip reading on the chip, acquiring the number of storage units of which the data in the storage array is converted into 0 under the current reference voltage, and recording the addresses of the corresponding storage units;
specifically, when the reference voltage is 3V, the number of memory cells with the threshold voltage below 3V can be correspondingly reached, and so on, when the reference voltage is 3.3V, the number of memory cells with the threshold voltage below 3.3V is read, and then calculation is performed based on the data read in two adjacent times to obtain the number of memory cells with the data converted into 0 in the memory array under the current reference voltage, that is, when the reference voltage is 3.3V, the number of memory cells with the threshold voltage greater than 3V and less than or equal to 3.3V is obtained by calculation.
More specifically, when the reference voltage is 3V, the number of memory cells with the reference voltage being above 3V may be read first, and by analogy, when the reference voltage is 3.3V, the number of memory cells with the threshold voltage being above 3.3V is read, and then calculation is performed based on the data read in two adjacent times, so that the number of memory cells with the data converted into 0 in the memory array at the current reference voltage can be obtained.
S213, increasing the voltage value of the first setting voltage, judging whether the increased first setting voltage is smaller than the upper limit of the reference voltage regulation range, if not, ending, and if so, jumping to the step S211;
specifically, the voltage value of the first setting voltage is increased, and if the value is within the reading range of the reference voltage, the method returns to step S211, and continues to read more threshold voltage data until the voltage value of the first setting voltage exceeds the reading range of the reference voltage, so as to implement a cyclic logic to obtain multiple sets of threshold voltage data, and establish a data basis for subsequently drawing a threshold voltage distribution diagram.
Specifically, by repeatedly performing steps S211 to S213, a plurality of sets of threshold voltage data, that is, the number of corresponding memory cells having threshold voltages respectively located in a plurality of voltage segment ranges can be obtained, so that a distribution diagram in which the threshold voltages are plotted on the abscissa and the number of memory cells is plotted on the ordinate can be drawn in step S3, so as to obtain the retention capability of the on-chip memory cell pair 1.
More specifically, in other embodiments, the loop condition may be increased in step S213: judging whether all the storage unit data in the whole slice are 0, if so, ending, otherwise, jumping to the step S211; the loop condition is prior to "judging whether the increased first set voltage is smaller than the reference voltage regulation range upper limit", so that when the reference voltage is increased to make all the memory cells in the whole slice become 0, indicating that the first threshold voltage data of the whole slice of memory cells are all under the current reference voltage, the steps S211-S213 can be ended in advance, the program operation amount is reduced, and the reading efficiency of the first threshold voltage is improved.
In some preferred embodiments, in step S212, the number of memory cells of which data is changed to 0 in the memory array at the current reference voltage is obtained by calculating the difference between the number of memory cells of which data is 1 in the whole chip obtained at the current reference voltage and the number of memory cells of which data is 1 in the whole chip obtained at the last reference voltage; if the number of memory cells with the data of 1 obtained when the reference voltage is 3V is subtracted from the number of memory cells with the data of 1 obtained when the reference voltage is 3.3V, the number of memory cells with the data of 1 to 0 in the interval, that is, the number of memory cells with the first threshold voltage in the interval of 3V-3.3V, can be obtained.
In some preferred embodiments, in step S213, the first setting voltage is increased by 0.2-0.4V for a single time; setting an interval of 0.2V-0.4V for reading the threshold voltage, wherein the number of the memory cells measured each time represents the number of the threshold voltage in the voltage interval, so that the normal distribution image about the threshold voltage distribution can be drawn, and the distribution condition of the threshold voltage in the whole chip is reflected.
In some preferred embodiments, in step S213, the first setting voltage is preferably increased by 0.3V for a single time; specifically, the first setting voltage is initially set to 3V, and is increased by 0.3V each time step S213 is performed, so that when the first setting voltage is increased to 10.2V, step S24 is performed, and the reading of the threshold voltage in step S2 is ended; in the reading process of steps S211 to S213, 24 groups of data under the reference voltage are measured in total, and a threshold voltage distribution graph drawn based on the data is used to clearly reflect the threshold voltage distribution of the storage unit for the data 1 retention capability.
In some preferred embodiments, step S22 includes the following sub-steps:
s221, changing the internal reference voltage of the chip according to a second set voltage;
specifically, the initial value of the second setting voltage is defined as 9.9V, so that when the step S221 is executed for the first time, the internal reference voltage of the chip is changed to 9.9V, and the memory cell data of the qualified chip in this case is generally all or most of 0; therefore, the voltage value of the second set voltage is reduced downwards to read the second threshold voltage, the second threshold voltage of the whole memory cell can be covered, and the holding capacity of the whole memory cell to 0 is clearly reflected.
S222, carrying out full-chip reading on the chip, acquiring the number of storage units of which the data in the storage array is converted into 1 under the current reference voltage, and recording the addresses of the corresponding storage units;
specifically, when the reference voltage is 9.9V, the number of memory cells with the threshold voltage below 9.9V is correspondingly reached, and so on, when the reference voltage is 9.6V, the number of memory cells with the threshold voltage below 9.6V is read when the second set voltage is 9.6V, and then calculation is performed based on the data read in two adjacent times, so that the number of memory cells with the threshold voltage converted into 1 in the memory array under the current reference voltage can be obtained, that is, when the reference voltage is 9.6V, the number of memory cells with the threshold voltage being greater than 9.6V and less than or equal to 9.9V is obtained by calculation.
More specifically, when the reference voltage is 9.9V, the number of memory cells with the reference voltage being 9.9V or more is read first, and so on, when the reference voltage is 9.6V, the number of memory cells with the threshold voltage being 9.6V or more is read, and then calculation is performed based on the data read in two adjacent times, so that the number of memory cells with data converted into 1 in the memory array under the current reference voltage can be obtained.
S223, reducing the second setting voltage, judging whether the reduced second setting voltage is larger than the lower limit of the reference voltage adjusting range, if not, ending, and if so, jumping to the step S221;
specifically, the voltage value of the second setting voltage is reduced, and if the value is within the reading range of the reference voltage, the step S221 is returned to continue to read more threshold voltage data until the voltage value of the second setting voltage exceeds the reading range of the reference voltage, so that a cyclic logic is implemented to obtain multiple sets of threshold voltage data, and a data basis is laid for subsequently drawing the threshold voltage distribution diagram.
Specifically, by repeatedly executing steps S221 to S223, a plurality of sets of threshold voltage data, that is, the number of corresponding memory cells having threshold voltages respectively located in a plurality of voltage segment ranges may be obtained, so that a distribution diagram drawn by using the threshold voltage as an abscissa and the number of memory cells as an ordinate may be drawn, and the retention capability of the whole chip memory cell to 0 may be obtained in this range.
More specifically, in other embodiments, the loop condition may be increased in step S223: judging whether all the storage unit data in the whole slice are 1, if so, ending, otherwise, jumping to the step S221; the loop condition is prior to "judging whether the reduced second set voltage is greater than the lower limit of the reference voltage regulation range", so that when the reference voltage is reduced to enable all the memory cells in the whole memory cell to become 1, the second threshold voltage data of the whole memory cell are all at the current reference voltage, the steps S221-S223 can be ended in advance, the program operation amount is reduced, and the reading efficiency of the second threshold voltage is improved.
In some preferred embodiments, in step S222, the number of memory cells of which data is 0 in the whole chip obtained at the current reference voltage is obtained by calculating the difference between the number of memory cells of which data is 0 in the whole chip obtained at the last reference voltage and the number of memory cells of which data is 0 in the whole chip obtained at the last reference voltage, so as to obtain the number of memory cells of which data is converted into 1 in the memory array at the current reference voltage; if the number of the memory cells of which the data is changed from 0 to 1 in the interval, namely the number of the memory cells of which the second threshold voltage is in the interval of 9.6V-9.9V, is subtracted from the number of the memory cells of which the data is 0 and which is obtained when the reference voltage is 9.9V.
In some preferred embodiments, in step S223, the single reduction value of the second setting voltage is 0.2-0.4V; setting an interval of 0.2V-0.4V for reading the threshold voltage, wherein the number of the memory cells measured each time represents the number of the threshold voltage in the voltage interval, so that the normal distribution image about the threshold voltage distribution can be drawn, and the distribution condition of the threshold voltage in the whole chip is reflected.
In some preferred embodiments, in step S223, the single reduction value of the second setting voltage is preferably 0.3V; specifically, the second setting voltage is initially 9.9V, and is decreased by 0.3V each time step S33 is performed, so that, when the second setting voltage is decreased to 2.7V, step S34 is performed, and reading of the threshold voltage in step S3 is ended; in the reading process of steps S31-S34, 24 groups of data under reference voltage are measured and taken together, and a threshold voltage distribution graph is drawn based on the measured data, so that the threshold voltage distribution of the storage unit for the data 0 retention capability can be clearly reflected.
In some preferred embodiments, in step S3, the first threshold voltage distribution map and the second threshold voltage distribution map are respectively drawn according to the number of memory cells with data of 0 in the chip under the corresponding reference voltage recorded in step S21 and the number of memory cells with data of 1 in the chip under the corresponding reference voltage recorded in step S22.
The first threshold voltage distribution graph and the second threshold voltage distribution graph are normal distribution graphs, and the first threshold voltage distribution graph and the second threshold voltage distribution graph can respectively reflect the holding capacity of the memory unit pair 1 and 0 in the chip.
In some preferred embodiments, the method further includes step S4, combining the first threshold voltage distribution diagram and the second threshold voltage distribution diagram; the combination of the two threshold voltage distribution maps can reflect the holding capacity of the chip for 0 and 1 in the same image, so that the data holding capacity of the chip can be reflected intuitively.
In some preferred embodiments, the method for reading the threshold voltage of the memory cell according to the embodiment of the present application performs test reading of the threshold voltage based on the STM32 test system, and has the characteristics of low equipment cost, high detection efficiency, and high accuracy.
As can be seen from the above, in the method for reading the threshold voltage of the memory cell provided in the embodiment of the present application, the data basis is provided for ensuring the measurement accuracy of the threshold voltage by writing checkerboard data on the whole chip in a programming manner, the threshold voltage of the memory cell in the chip is read by adjusting the reference voltage in an increasing and decreasing manner, and the first threshold voltage distribution diagram and the second threshold voltage distribution diagram are drawn based on the adjustment, so that the distribution condition of the threshold voltage in the memory cell in the chip can be intuitively and accurately reflected, and the data retention capability of the chip can be visually expressed.
In a second aspect, please refer to fig. 4, fig. 4 is a memory cell threshold voltage reading apparatus for reading a threshold voltage of a memory cell in NOR Flash according to some embodiments of the present application, including:
the programming module is used for programming and writing checkerboard data into the whole chip;
the voltage regulation module is used for regulating the reference voltage of the chip and regulating the internal reference voltage of the chip in an increasing or decreasing mode;
the data reading module reads and records the number of memory cells with data of 1 or 0 in the chip under different reference voltages and the addresses of the corresponding memory cells;
and the drawing module is used for drawing a threshold voltage distribution diagram according to the data acquired by the reading module.
According to the device for reading the threshold voltage of the storage unit, the method for reading the threshold voltage of the storage unit can be executed, chessboard data is written in by programming a whole chip through a programming module, a data basis is provided for ensuring the measurement precision of the threshold voltage, the reference voltage is adjusted in an increasing and decreasing mode through a voltage adjusting module, the threshold voltage of the storage unit in the chip is read through a data reading module, a threshold voltage distribution diagram is drawn by using a drawing module on the basis, the distribution condition of the threshold voltage in the storage unit in the chip can be reflected visually and accurately, and the data retention capability of the chip can be expressed visually.
In a third aspect, referring to fig. 5, fig. 5 is a schematic structural diagram of an electronic device according to an embodiment of the present application, where the present application provides an electronic device 3, including: the processor 301 and the memory 302, the processor 301 and the memory 302 being interconnected and communicating with each other via a communication bus 303 and/or other form of connection mechanism (not shown), the memory 302 storing a computer program executable by the processor 301, the processor 301 executing the computer program when the computing device is running to perform the method of any of the alternative implementations of the embodiments described above.
In a fourth aspect, the present application provides a storage medium, and when being executed by a processor, the computer program performs the method in any optional implementation manner of the foregoing embodiments. The storage medium may be implemented by any type of volatile or nonvolatile storage device or combination thereof, such as a Static Random Access Memory (SRAM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), an Erasable Programmable Read-Only Memory (EPROM), a Programmable Read-Only Memory (PROM), a Read-Only Memory (ROM), a magnetic Memory, a flash Memory, a magnetic disk, or an optical disk.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.
In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. A method for reading the threshold voltage of a memory cell in NOR Flash is characterized by comprising the following steps:
s1, writing checkerboard data into the whole chip programming;
s2, adjusting the internal reference voltage of the chip, and recording the number of memory cells with data change information in the adjustment process of the internal reference voltage of the chip and the addresses of the corresponding memory cells;
s3, drawing a threshold voltage distribution diagram according to the value of the reference voltage and the number of the storage units with data change information under the corresponding reference voltage;
the data change information includes a change from 0 to 1 of data and a change from 1 to 0 of data.
2. The method of claim 1, wherein step S1 includes the following sub-steps:
s11, carrying out whole erasing treatment on the chip;
s12, programming and recording checkerboard data for the chip;
and S13, carrying out full-chip reading on the chip and checking the checkerboard data.
3. The method of claim 1, wherein step S2 includes the following sub-steps:
s21, adjusting the internal reference voltage of the chip in an incremental mode, and recording the number of memory cells with data of 0 in the chip under the corresponding reference voltage and the addresses of the corresponding memory cells;
and S22, adjusting the internal reference voltage of the chip in a descending manner, and recording the number of the memory cells with the data of 1 in the chip under the corresponding reference voltage and the addresses of the corresponding memory cells.
4. The method as claimed in claim 3, wherein the step S21 includes the following sub-steps:
s211, changing the internal reference voltage of the chip according to the first set voltage;
s212, carrying out full-chip reading on the chip, acquiring the number of storage units of which the data in the storage array is converted into 0 under the current reference voltage, and recording the addresses of the corresponding storage units;
and S213, increasing the voltage value of the first setting voltage, judging whether the increased first setting voltage is smaller than the upper limit of the reference voltage regulation range, if not, ending, and if so, jumping to the step S211.
5. The method for reading the threshold voltage of the memory cell according to claim 4, wherein in step S212, the difference between the number of memory cells with data of 1 in the whole chip obtained under the current reference voltage and the number of memory cells with data of 1 in the whole chip obtained under the previous reference voltage is calculated to obtain the number of memory cells with data converted to 0 in the memory array under the current reference voltage.
6. The method as claimed in claim 3, wherein the step S22 includes the following sub-steps:
s221, changing the internal reference voltage of the chip according to a second set voltage;
s222, carrying out full-chip reading on the chip, acquiring the number of storage units of which the data in the storage array is converted into 1 under the current reference voltage, and recording the addresses of the corresponding storage units;
and S223, reducing the second setting voltage, judging whether the reduced second setting voltage is larger than the lower limit of the reference voltage regulation range, if not, ending, and if so, jumping to the step S221.
7. The method for reading the threshold voltage of the memory cell of claim 3, wherein the first threshold voltage distribution map and the second threshold voltage distribution map are respectively generated in step S3 according to the number of the memory cells with data of 0 in the chip under the corresponding reference voltage recorded in step S21 and the number of the memory cells with data of 1 in the chip under the corresponding reference voltage recorded in step S22.
8. A memory cell threshold voltage reading apparatus for reading a threshold voltage of a memory cell in NOR Flash, comprising:
the programming module is used for programming and writing checkerboard data into the whole chip;
the voltage regulation module is used for regulating the reference voltage of the chip and regulating the internal reference voltage of the chip in an increasing or decreasing mode;
the data reading module reads and records the number of memory cells with data of 1 or 0 in the chip under different reference voltages and the addresses of the corresponding memory cells;
and the drawing module is used for drawing a threshold voltage distribution diagram according to the data acquired by the reading module.
9. An electronic device comprising a processor and a memory, said memory storing computer readable instructions which, when executed by said processor, perform the steps of the method of any of claims 1-7.
10. A storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, performs the steps of the method according to any one of claims 1-7.
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