JP4940757B2 - Mobile radio communication terminal, information collecting method and program when abnormality occurs - Google Patents

Description

  The present invention relates to an information communication apparatus, and more particularly, to a mobile radio communication terminal, method, and program suitable for application to failure analysis and the like.

  In the development of a mobile radio terminal, at the initial stage of development, an evaluation board for development is manufactured, and software development and debugging / testing are performed. The evaluation board is equipped with a function and a circuit for enabling efficient execution of debugging, and debugging is performed using a debugging tool such as an ICE (in-circuit emulator).

  Recent mobile radio terminals are required to shorten the development period, and the opportunity loss due to development delay is the largest business loss, so it is required to bring the product to the market at just timing. For this reason, from the middle stage of development, a development method is generally used in which a mobile radio terminal that is almost the same as mass production is prototyped and debugging is performed using an evaluation board. In particular, a prototype of a mobile radio terminal is used for a field test, and is tested and verified in an actual environment.

  In this field test, when problems occur and problem analysis / investigation, prototypes of mobile radio terminals are equipped with functions and circuits that enable more efficient debugging than evaluation boards. Basically, it is difficult to execute debugging using a debugging tool such as ICE (in-circuit emulator).

  In addition, it is difficult to use the evaluation board for field tests due to various restrictions, and there are no problems in the laboratory test environment. The problem becomes apparent for the first time in the actual operating environment such as field test by trial production of mobile radio terminals. There are many things to do. Thus, it is extremely difficult to find and analyze bugs that are difficult to reproduce.

  There is a demand for strengthening a mechanism for storing information necessary for evaluation and verification of software and system operation, factors in the event of an abnormality, and information indicating the operating state of software.

  The same can be said about the cause investigation when the shipped product (mobile radio terminal) has a defect / defect and returns from the market. That is, there is a demand for speeding up the cause identification / analysis process. However, even in this case, as described above, it is extremely difficult to find and analyze a bug that is difficult to reproduce.

  In the case of analysis of defects occurring in the market or field test, the information at the time of the defects needs to be securely stored, accumulated and accumulated, and is stored even if the mobile radio terminal battery is removed. It must be stored in a non-volatile ROM such as Electrically Erasable and Programmable Read Only Memory.

  Adopting a 2CPU architecture that comprises two CPUs, a CCPU (Communication CPU) for controlling the communication part and an ACPU (Application CPU) for controlling the application part, a program for performing communication control is stored on the CCPU side. There is no ROM, which is a non-volatile memory, the CCPU side program is held in the ACPU side ROM, and from the ACPU side ROM to the CCPU side via the interface (I / F) between the ACPU and CCPU when the device starts up There is a mobile wireless terminal having a sequence and configuration for starting the program transferred to the RAM. In this case, compared to a device having a ROM that is a non-volatile memory that stores a program for performing communication control on the CCPU side, it is impossible to realize a function for retaining information for improving debugging efficiency at the time of abnormality or the like. There are challenges.

  Specifically, since the conventional 2-CPU configuration has a ROM on the CCPU side, if an abnormality occurs on the CCPU side, only the CCPU side can save debug information in the ROM when the abnormality occurs. However, in the case of a 2-CPU configuration that does not have a ROM on the CCPU side, it must be held in the ROM on the ACPU side. In this case, in order to write through the interface between the ACPU and CCPU immediately after the occurrence of an abnormality, a variety of controls are required. However, because of the abnormal state, it is difficult to complete the control normally, leaving information. There is a high possibility that it will not be possible. In the conventional method of leaving a history in the ROM when an abnormality occurs, it is difficult to complete control normally.

  As a configuration for determining the cause of the occurrence of the reset and saving and loading data between the RAM and the EEPROM, Patent Document 1 discloses a volatile storage means (RAM) for storing data volatilely. When it is determined that the reset cause is a predetermined cause by the non-volatile storage means (flash EEPROM) for storing data in a non-volatile manner and the determination means for determining the cause of the reset that has occurred, the reset cause is stored in the volatile storage means. Saving means for saving the stored data in the non-volatile storage means, and when the determination means determines that the reset cause is not a predetermined cause, the data stored in the non-volatile storage means is stored in the volatile storage means. An information processing apparatus having a loading means for loading is disclosed. Further, in relation to a configuration (used in the present invention described later) that holds RAM (Random Access Memory) data at the time of resetting, Patent Document 1 causes a reset by pressing a power button or a reset button. However, a configuration is disclosed in which power is supplied to the RAM as usual, a clock signal for refreshing is supplied, and thereby the boot process is executed while effectively holding the contents of the RAM.

  In addition, as a trace data storage device including a nonvolatile memory and a nonvolatile memory, Patent Document 2 discloses a first data storage unit including a nonvolatile memory for storing data and a second data including a nonvolatile memory. A memory having an accumulation unit that accumulates data acquired by the trace control unit in the first data accumulation unit, and copies the data in the first data accumulation unit to the second data accumulation unit when the external bus traffic is small A configuration including a control unit is disclosed. Further, Patent Document 3 discloses a configuration of a radio base station that stores a diagnosis result in a nonvolatile memory. In Patent Document 4, a memory device with an information holding function is built in a work computer, and when a failure occurring in the work computer is analyzed by an analysis computer, the memory device with an information holding function is a memory at the time of failure. A configuration that can be transferred to an analysis computer while maintaining the state is disclosed. Note that each of the configurations described in each of the above patent documents only partially corresponds to a part of the present invention (or example) described later.

Republished patent WO 2000/54133 JP 2004-070420 A JP 2004-280340 A JP 09-006683 A

As described above, in the mobile radio terminal,
(A) Improvement of efficiency in development and evaluation of evaluation and verification of software and system operation,
(B) Improvement of defect analysis is required when a defect or defect occurs after product shipment and returns from the market.

  That is, a debugging method for improving debugging efficiency in a prototype of a mobile radio terminal and a function for narrowing down defects after product shipment are required. As one of the methods of the function, information that leads to the analysis of the cause and type of the abnormality that occurred and the software operation status at the time of the abnormality is stored in the ROM, the data is collected and used for analysis However, in the case of a two-CPU configuration that does not have a ROM on the CCPU side, there is a problem that there is a high possibility that information cannot be left in the method of leaving a history in the ROM when an abnormality occurs.

  Accordingly, an object of the present invention is to provide a terminal, a method, and a program that realize a function of retaining information for improving debugging efficiency in an abnormal time and the like, and that can improve analysis of defects.

  In order to solve the above-described problems, the invention disclosed in the present application is generally configured as follows.

  An apparatus according to one aspect of the present invention includes a first unit including a volatile first memory in which data is held with respect to reset at the time of restart of a return process, and a rewritable nonvolatile first. A second unit having two memories, and when an abnormality occurs on the first unit side, the abnormality information is not immediately stored in the second memory, but temporarily stored in the first memory. The abnormality information is temporarily stored, and information can be transmitted and received between the first and second units by restarting recovery from the abnormality, and then temporarily stored in the first memory. The held abnormality information is transferred from the first unit to the second unit and stored in the second memory.

  A mobile communication terminal according to an aspect of the present invention includes a first CPU including a volatile first memory in which data is held with respect to reset at the time of restart of a return process, and a rewritable nonvolatile memory. A second CPU having a second memory having a first and second memory, wherein the first CPU and the second CPU can transmit and receive information to and from each other via an interface. After the abnormality information is temporarily stored in the first memory in the CPU, and information can be transmitted and received between the first and second CPUs by restarting from the abnormality, The first CPU transmits the abnormality information temporarily stored in the first memory to the second CPU via the interface, and the second CPU receives the first CPU from the first CPU, Temporarily stored in the first memory Receives abnormality information is configured to be stored in the second memory.

  In the mobile communication terminal according to the present invention, when the first CPU writes abnormality information to the first memory, the abnormality information storage flag is validated, and when the abnormality is restarted, the abnormality information storage flag is valid. In the case shown, the first CPU makes a request to the second CPU to write abnormality information temporarily held in the first memory to the second memory.

  In the mobile communication terminal according to the present invention, the first CPU is a CCPU (Communication CPU) that controls a communication part, and the second CPU is an ACPU (Application CPU) that controls an application part. is there.

  In the mobile communication terminal according to the present invention, the first memory is built in the first CPU, and includes a built-in RAM that retains data when the system reset is started. The ROM includes a rewritable ROM accessed by a second CPU, and the first and second CPUs further include first and second RAMs for storing programs and temporarily storing data, respectively. The programs executed by the first and second CPUs are held in the ROM on the second CPU side, and the second CPU is connected via the interface between the first and second CPUs at startup. Is transferred from the ROM on the CPU side to the first RAM on the first CPU side, and when the abnormality is detected on the first CPU side, the cause of the abnormality, the operating state of the software, the software At least one piece of information necessary for evaluation and verification of system operation and system operation is temporarily stored in the built-in RAM of the first CPU, and the first and Through the interface between the two CPUs, the first CPU transmits information temporarily stored in the internal RAM to the second CPU, and the second CPU temporarily stores the information in the internal RAM. The received information is received and stored in a predetermined information storage area of the ROM.

A method according to another aspect of the present invention includes a first unit including a volatile first memory in which data is held against a reset at the time of restart of a return process, and a rewritable nonvolatile first. An information collection method when an abnormality occurs in an information communication device including a second unit including two memories,
When an abnormality occurs on the first unit side, the abnormality information is not temporarily stored in the second memory, but temporarily stored in the first memory.
After the information is transmitted / received between the first unit and the second unit by restarting the recovery from the abnormality, the abnormality information temporarily stored in the first memory is stored in the first unit. Are transferred to the second unit and stored in the second memory.

In the method according to another aspect of the present invention, the first CPU is provided with a volatile first memory that retains data even when a reset occurs in the return processing, and the second CPU is rewritable. A non-volatile second memory, wherein the first CPU and the second CPU are capable of transmitting and receiving information to and from each other.
Temporarily storing abnormality information in the first memory in the first CPU when an abnormality occurs;
After restarting the recovery from the abnormality, after the information can be transmitted and received between the first and second CPUs, the first CPU stores the abnormality information temporarily stored in the first memory, Transmitting to the second CPU side via the interface;
The second CPU receives the temporarily stored information and stores it in the second memory;
including.

  In the method according to the present invention, when the first CPU writes abnormality information to the first memory, the abnormality information storage flag is validated, and when the abnormality information storage flag indicates validity upon restarting, The first CPU makes a request to the second CPU to write abnormal information temporarily held in the first memory to the second memory.

A computer program according to another aspect of the present invention includes a first unit including a volatile first memory in which data is held with respect to reset at the time of restart of a return process, and a rewritable nonvolatile memory A computer constituting the information communication device including the second unit including the second memory;
A process of temporarily storing the abnormality information in the first memory temporarily without storing the abnormality information in the second memory immediately when an abnormality occurs on the first unit side;
After the information is transmitted / received between the first unit and the second unit by restarting the recovery from the abnormality, the abnormality information temporarily stored in the first memory is stored in the first unit. To transfer to the second unit and store in the second memory;
It consists of a program that executes

In a computer program according to another aspect of the present invention, a first CPU is provided with a volatile first memory that retains data even if a reset occurs in the return processing, and the second CPU includes: A computer that constitutes a mobile communication terminal is provided with a rewritable nonvolatile second memory, and the first CPU and the second CPU can transmit and receive information to and from each other.
A process of temporarily storing information in the first memory in the first CPU when an abnormality occurs;
At the time of restart of recovery from an abnormality, after the information can be transmitted and received between the first and second CPUs, the first CPU stores the information temporarily stored in the first memory. Processing to transmit to the second CPU side via an interface;
The second CPU receives the temporarily stored information and stores it in the second memory;
It consists of a program that executes

  According to the present invention, it is possible to realize a function of holding information for improving debugging efficiency in the event of an abnormality.

  The present invention will be described in detail below with reference to the accompanying drawings. The present invention includes two CPUs, a CCPU (Communication CPU) 104 of the communication unit (100) and an ACPU (Application CPU) 108 of the application unit (107), and the application unit includes a ROM (111). When an abnormality occurs, the abnormality information is not immediately written to the ROM (111), but is temporarily stored in the memory area of the CCPU built-in RAM (105) that retains data even if a reset occurs in the recovery process from the abnormality. The ACPU and the CCPU can exchange information with each other via the interface (I / F) (120) by restarting the recovery from the abnormality, and then temporarily store in the built-in RAM (105) of the CCPU. The stored abnormality information is transmitted to the ACPU side via the interface (I / F) (120), and the ACPU stores the received information in a predetermined CCPU information storage area of the ROM (111). To control. Hereinafter, description will be made with reference to examples.

  FIG. 1 is a diagram showing the configuration of an embodiment of the present invention. Figure 1 shows the development of software and system operation evaluation / verification in the development of mobile radio terminals, the improvement of evaluation efficiency, and the purpose of analysis of defects when defects are found after product shipment and return from the market. 1 shows a basic configuration of a mobile radio communication terminal adopting a 2CPU architecture in which a platform is constituted by two CPUs having a debugging function as described above. The basic configuration of the mobile radio communication terminal is widely known to operators. The architecture that constitutes a platform by two CPUs, that is, a communication unit 100 on the CCPU (Communication CPU) side that controls the communication part and an application unit 107 on the ACPU (Application CPU) side that controls the application part, is generally “2CPU. Called “configuration”. Data can be transmitted and received between the ACPU and the CCPU via an interface (I / F) 120 (I / F between A and C).

  The communication unit 100 includes an antenna 101, a radio unit 102, a baseband unit 103, and a RAM 106. The baseband unit 103 includes a CCPU 104 with a built-in RAM 105.

  The antenna 101 is a transmission / reception shared antenna that transmits and receives data to a base station (not shown).

  The radio unit (RF unit) 102 performs radio signal transmission / reception control corresponding to the radio communication scheme of each mobile communication system.

  The baseband 103 performs a modulation / demodulation processing operation of a transmission / reception digital signal. Control of the baseband 103 is controlled by the CCPU 104 according to a program.

  The application unit 107 includes an ACPU 108, a codec 109, a speaker 113, a microphone 114, an operation unit 115, a display unit 116, an external interface 117, a ROM 111 such as an electrically rewritable EEPROM, and a storage unit 110 including a RAM 112. .

  In this embodiment, the CCPU does not have a ROM which is a nonvolatile memory for storing a program for performing communication control, and the CCPU-side program is held in the ACPU-side ROM 111. The data is transferred from the ROM 111 on the ACPU 108 side to the RAM 106, which is a volatile memory on the CCPU 104 side, via the (I / F) 120.

  The CCPU 104 performs control by executing the program transferred to the RAM 106. In addition to storing programs, the RAM 106 can temporarily store data.

  Similarly, the built-in RAM 105 writes and reads data necessary for program execution and the like, and performs faster access than the RAM 106.

  In the application unit 107, the ACPU 108 controls various application functions and user interfaces. During a call, the audio input from the microphone 114 is processed by the codec 109 and transmitted as audio data to the CCPU 104 by the ACPU 108 for communication. It is processed on the unit 100 side and transmitted from the terminal.

  The audio data on the receiving side is processed by the communication unit 100, transmitted to the ACPU 108 by the CCPU 104, and the electrical signal decoded by the codec 109 is output as audio from the speaker 113.

  The operation unit 115 is a key input unit, such as a power ON / OFF key, a numeric keypad for inputting a dial number for voice communication, a voice incoming call start / end key, an input key for data communication (all not shown), and the like. A key for operating the mobile communication radio terminal is provided.

  The display unit 116 displays out-of-service / in-service display, received electric field level, date / time / operational message information.

  The storage unit 110 stores a program and data executed by the ACPU 108, and the ACPU 108 is configured to control each of the above units according to the program. The storage unit 110 includes a ROM 111 that is a nonvolatile memory that retains data even when the power is turned off, and a RAM 112 that is a volatile memory that loses data when the power is turned off.

  The ROM 111 also stores a program executed by the CCPU 104. In addition, the ROM 111 stores information necessary for terminal operation that is required to be retained even when the apparatus power is turned off, user data, and abnormality information (such as software status at the time of abnormality occurrence and abnormality occurrence factor).

  The RAM 112 is mainly used as a work area for storing information necessary for program operation.

  An external interface (I / F) 117 is connected to an inspection jig (not shown), and controls mobile radio terminals using control software for inspection and debugging mounted on a PC (not shown). Inspection and debugging are performed.

  In this embodiment, information is not written to the ROM immediately when an abnormality occurs, but is temporarily held in a memory area such as the RAM 105 in the CCPU where data is held even if a reset occurs in the recovery process from the abnormality. When the ACPU 108 and the CCPU 104 can transmit and receive information to and from each other via the interface (I / F) 120 between the ACPU and the CCPU by restarting the recovery from the abnormality, they are temporarily stored in the RAM 105 on the CCPU side. The transmitted information is transmitted to the ACPU 108 side via the interface (I / F) 120, and the ACPU 108 stores the information in a predetermined information storage area of the CCPU.

  FIG. 2 is a flowchart showing the control of this embodiment. Hereinafter, the control operation of this embodiment will be described with reference to FIGS.

  When an abnormality occurs on the CCPU 104 side (step S201), after the abnormality is detected by the CCPU 104, the factors at the time of occurrence of the abnormality, the operation state of the software, and information necessary for the evaluation verification of the software and system operation are temporarily The data is stored in the RAM 105 built in the CCPU 104 (step S202). Note that the data format of the information stored in the RAM 105 needs to be specified in advance by the designer. The data format is provided with a flag (referred to as “abnormal information storage flag”) indicating the validity / invalidity of data temporarily stored in the internal RAM 105.

  When the abnormality information is stored in the built-in RAM 105, the abnormality information storage flag is validated and written according to this data format. At this point, there is a high possibility that the ACPU 108 and the CCPU 104 will not normally send and receive information to and from each other via the interface (I / F) 120.

  A system reset is performed for recovery processing from an abnormality (step S203). Even in this reset, the data in the built-in RAM 105 of the CCPU 104 is retained. Data retention in the RAM 105 built in the CCPU 104 is destroyed and not retained when power supply from a battery or the like is stopped. Accordingly, power is supplied to the internal RAM 105 at the time of reset (during boot processing), the internal RAM 105 is not cleared by initialization, refresh is performed, and data before reset is held.

  Activation processing after reset is performed (step S204). By this restart process (return process), the ACPU 108 and the CCPU 104 can transmit and receive information to and from each other via the interface (I / F) 120.

  Next, the CCPU 104 reads the abnormality information storage flag (step 205), and checks the flag of the read data (step S206).

  If the abnormality information is temporarily stored in the built-in RAM 105 in step S202, a valid flag is set in the abnormality information storage flag.

  When the valid flag is confirmed in the abnormality information storage flag (“valid” branch of step S206), the process proceeds to step S207. On the other hand, when the valid flag is not raised, that is, when the flag is invalid, it means that the information is not saved, and thus the abnormal time information saving process ends.

  In step S207, the CCPU 104 makes a request (data write request) for saving to the information storage area of the CCPU 104 in the ROM 111 on the ACPU 108 side via the interface (I / F) 120.

  When the ACPU 108 receives a data write request from the CCPU 104, the abnormal information storage process is started (step S210).

  The CCPU 104 reads information temporarily stored in the built-in RAM 105 (step S208), and transmits the read data to the ACPU 108 via the interface (I / F) 120 (step S209).

  The ACPU 108 writes and saves the data transmitted from the CCPU 104 and received via the interface (I / F) 120 in the information storage area assigned to the CCPU 104 in the ROM 111 on the ACPU 108 side (step S210). . When the write storage process is completed, the ACPU 108 transmits a write completion notification to the CCPU 104 (step S210).

  After receiving the write completion notification from the ACPU 108, the CCPU 104 clears the information stored in the CCPU built-in RAM 105 in step S211, and the process ends.

  By using such control, it is possible to reliably save information necessary for evaluating and verifying the cause of abnormality, the operating state of software, and the software and system operation.

  The effects of the present embodiment will be described below.

  In the conventional 2-CPU configuration, since the ROM is provided on the CCPU side, when an abnormality occurs on the CCPU side, it is possible to save debug information in the ROM when the abnormality occurs only on the CCPU side. For the purpose of further reducing the cost and size of the terminal, a terminal having a 2-CPU configuration without a ROM on the CCPU side has been developed. However, in the case of a terminal having such a configuration, it is necessary to store it in the ROM on the ACPU side as a storage destination of information at the time of abnormality on the CCPU side. Immediately after the occurrence of an abnormality, writing through the interface between the ACPU and CCPU requires a wide variety of controls. However, because of the abnormal state, it is difficult to complete the control normally and information can be left. Most likely not.

  According to the present invention, when an abnormality occurs, the abnormality information is not directly written to the ROM, but is stored in a memory area such as a RAM in the CCPU in which data is retained even if a reset is generated in the recovery process from the abnormality. Temporarily stored, and after restarting from recovery from an abnormality, the ACPU and CCPU can exchange information with each other via the interface (I / F), and then temporarily stored in the RAM on the CCPU side. Information is transmitted to the ACPU side via the interface (I / F) between the ACPU and CCPU, and the ACPU side is provided with a control for storing the information in a predetermined information storage area of the CCPU. Information necessary for evaluation and verification of software factors, software operating status, and software and system operation can be reliably stored. Based on the stored information, software and system Evaluation and development of developers and evaluators of the verification of the operation, has achieved a reduction of the analysis improved and analysis period of a problem when return from failure, failure occurs market after shipment evaluation efficiency and product.

  In the above embodiment, the mobile radio terminal has been described as an example, but it is needless to say that the present invention can also be applied to other information communication apparatuses. Although the present invention has been described with reference to the above-described embodiments, the present invention is not limited to the configurations of the above-described embodiments, and various modifications that can be made by those skilled in the art within the scope of the present invention. Of course, including modifications.

It is a figure which shows the structure of one Example of this invention. It is a flowchart for demonstrating operation | movement of one Example of this invention.

Explanation of symbols

100 Communication Unit 101 Antenna 102 Radio Unit 103 Baseband Unit 104 CCPU
105 Built-in RAM
106 RAM
107 Application unit 108 ACPU
109 Codec 110 Storage unit 111 ROM
112 RAM
113 Speaker 114 Microphone 115 Operation Unit 116 Display Unit 117 External Interface 120 ACPU-CCPU (A-C) Interface

Claims (5)

Comprising first and second CPUs capable of transmitting and receiving information to and from each other via an interface;
A mobile communication terminal for holding abnormality information of the first CPU in a rewritable ROM (read only memory) connected to the second CPU,
The first CPU includes a built-in RAM (random access memory) in which data is held with respect to a reset,
Wherein the time of occurrence of abnormality in the first CPU, writing the abnormality information in said internal RAM in the first CPU, and enable the abnormality information storage flag,
Restarting recovery from the abnormality, after becoming ready to exchange information between said first and second CPU, said first CPU, when the abnormality information storage flag indicates valid, the built - in RAM abnormality information is sent to the second CPU via the interface,
The mobile communication terminal, wherein the second CPU receives the abnormality information from the first CPU and stores it in the ROM. The first CPU is a CCPU (Communication CPU) that controls a communication part,
The mobile communication terminal according to claim 1, wherein the second CPU is an ACPU (Application CPU) that controls an application part. The first and second CPUs further include first and second RAMs for storing programs and temporarily storing data, respectively.
The programs executed by the first and second CPUs are held in the ROM on the second CPU side, and the second CPU is connected via the interface between the first and second CPUs at startup. Transferred from the ROM on the CPU side to the first RAM on the first CPU side,
On the first CPU side, at the time of detecting an abnormality, at least one of information necessary for evaluation and verification of the cause of the abnormality, the operating state of the software, and the software and the system operation is temporarily stored in the first CPU. Stored in the built-in RAM,
When restarting from recovery from an abnormality, the first CPU transmits information temporarily stored in the built-in RAM to the second CPU via the interface between the first and second CPUs. ,
3. The mobile communication according to claim 1, wherein the second CPU receives information temporarily stored in the built-in RAM and stores the information in a predetermined information storage area of the ROM. 4. Terminal. Comprising first and second CPUs capable of transmitting and receiving information to and from each other via an interface;
The abnormality information of the first CPU is held in a rewritable ROM (read only memory) connected to the second CPU, and the first CPU has a built-in RAM (data that is held for resetting). A method of collecting information in the event of an abnormality with a random access memory),
Wherein the time of occurrence of abnormality in the first CPU, writing the abnormality information in said internal RAM in the first CPU, and enable the abnormality information storage flag,
Restarting recovery from the abnormality, after becoming ready to exchange information between said first and second CPU, said first CPU, when the abnormality information storage flag indicates valid, the built - in RAM abnormality information is sent to the second CPU via the interface,
The method for collecting abnormality information of a mobile communication terminal, wherein the second CPU receives the abnormality information from the first CPU and stores the abnormality information in the ROM. Comprising first and second CPUs capable of transmitting and receiving information to and from each other via an interface;
The abnormality information of the first CPU is held in a rewritable ROM (read only memory) connected to the second CPU, and the first CPU has a built-in RAM (data that is held for resetting). In a computer constituting a mobile communication terminal equipped with a random access memory)
Wherein the time of occurrence of abnormality in the first CPU, writing the abnormality information in said internal RAM in the first CPU, a process of validating the abnormality information storage flag,
Restarting recovery from the abnormality, after becoming ready to exchange information between said first and second CPU, said first CPU, when the abnormality information storage flag indicates valid, the built - in RAM abnormality information is sent to the second CPU via the interface,
The second CPU receives the abnormality information from the first CPU and stores it in the ROM;
A program that executes

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