JP4893028B2 - Chipset emulation apparatus and method - Google Patents

Description

The present invention is, inside the computer, RAM, relates emulation apparatus and method of configuration space chipset for managing the transfer of data between the expansion cards.

  When configuring the BIOS of the computer system, if the computer system to be designed is not realized, emulation for checking the operation of the BIOS is performed using hardware different from the computer system to be designed (for example, Patent Document 1 (Japanese Patent Laid-Open No. 5-46406)).

  In conventional BIOS development, if there is no chipset to be controlled, whether the program at the location that accesses the configuration space of the BIOS chipset is changed so that it does not work, or whether the program has run It was necessary to verify the operation of the BIOS with the change as described above.

In order to verify the operation without changing the BIOS, it is necessary to separately prepare dedicated hardware for testing.
JP-A-5-46406

  The prior art described above has the following problems.

  In the absence of hardware, in order to perform a BIOS test, the BIOS to be tested is changed. This means that the actual BIOS test is not performed and the test is effective. There is a problem that the property is low.

  When verifying the operation using dedicated hardware for testing without changing the BIOS, the above problem does not occur, but when configuring a computer system with abundant configuration variations, it takes time. At the same time, it is difficult to realize hardware for testing, and testing that considers completeness cannot be performed. For this reason, there is still a problem that the effectiveness of the test is low.

  The present invention has been made in view of the problems of the conventional techniques as described above, and has an object to realize an apparatus and a method capable of increasing the effectiveness of a test on a chip set and performing it quickly. To do.

The emulation device of the chipset of the present invention is
A memory that stores multiple configuration patterns of a new computer system;
Registers that set the characteristics, types, and operations of the devices that make up the chipset of a conventional computer system;
For the new model configuration pattern stored in the memory, a chipset configuration table that stores an address corresponding to each new model configuration pattern;
A maintenance console which is a terminal for operating the computer system of the new model and the conventional model;
BIOS that stores characteristics, types, configuration information of operation and environment information of devices constituting conventional and new model chip sets, controls setting and writing operations to the memory and registers, and executes BIOS for performing emulation An execution unit, and
When the test operation is started, the maintenance console starts the computer system after designating a configuration pattern for a new model to be evaluated by the conventional machine held in the chipset configuration table, and then the conventional machine Specify environment / configuration information and handoff to the BIOS execution unit,
The chipset configuration table outputs an address storing a new model configuration pattern designated by the maintenance console to the memory,
The memory outputs the specified address to the BIOS execution unit,
When the BIOS execution unit is handed off from the maintenance console, the hardware initial value of the chipset of the conventional machine and the environment / configuration information of the conventional machine specified by the maintenance console are set in the register. addresses the sent as an active, characterized in that to create a pseudo-configuration space in memory.

The chipset emulation method of the present invention includes:
A memory that stores multiple configuration patterns of a new computer system;
Registers that set the characteristics, types, and operations of the devices that make up the chipset of a conventional computer system;
For the new model configuration pattern stored in the memory, a chipset configuration table that stores an address corresponding to each new model configuration pattern;
A maintenance console which is a terminal for operating the computer system of the new model and the conventional model;
BIOS that stores characteristics, types, configuration information of operation and environment information of devices constituting conventional and new model chip sets, controls setting and writing operations to the memory and registers, and executes BIOS for performing emulation An emulation method performed by a chipset emulation device comprising:
When the test operation is started, the maintenance console starts the computer system after designating a configuration pattern for a new model to be evaluated with the conventional machine held in the chipset configuration table, and then Designating machine environment / configuration information and handing off to the BIOS execution unit;
Outputting the address at which the chipset configuration table stores a new model configuration pattern designated by the maintenance console to the memory;
And outputting an address where the memory is designated to the BIOS execution unit,
After the BIOS execution unit is handed off from the maintenance console, the hardware initial value of the chipset of the conventional machine and the environment / configuration information of the conventional machine specified by the maintenance console are set in the register, and the memory and having the steps of: creating a pseudo configuration space in the memory by an address which has been sent more active.

  The present invention configured as described above has the following effects.

  The first effect is that the BIOS can be developed and tested at an early stage and can be tested in a short period of time until hardware is shipped.

  The reason is that the pseudo configuration space emulated instead of the new model returns a response to the BIOS, so that the BIOS test can be promoted at an early stage without using the hardware that is originally targeted using the conventional machine. Because.

  The second effect is that a BIOS with stable quality can be developed.

  The reason is that in the pseudo-configuration space, a variety of configurations can be easily assembled, so that the test is not hindered due to lack of equipment or configuration assembly.

  Next, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing a main configuration of an emulation apparatus according to the present invention.

  In this embodiment, a BIOS execution unit 1, a chipset initialization processing unit 2, a conventional machine processing unit 3, a new model processing unit 4, a real configuration space unit 5, a pseudo configuration space unit 6, a maintenance console 7, a chipset It consists of a configuration table 8.

  In this example, it is possible to test a BIOS for a new model using the hardware of a conventional machine without using the hardware of the target new model in the BIOS development for a new chipset in a computer system. It is what. The BIOS execution unit 1, the actual configuration space unit 5, and the pseudo configuration space unit 6 in FIG. 1 are arranged in a conventional machine.

  In FIG. 1, a chipset initialization processing unit 2 in the BIOS execution unit 1 is implemented by using a PCI configuration cycle that is a method for accessing a device connected to the PCI bus. The chipset initialization processing unit 2 includes an interface to the configuration space of the chipset, and is activated during POST (Power On Self Test) that tests each device constituting the conventional machine when the conventional machine is powered on. The In this embodiment, the chipset initialization processing unit 2 has two tasks: a task by the conventional machine processing unit 3 that initializes the conventional chipset and a task by the new model processing unit 4 that initializes the chipset for the new model. To work.

  The new model processing unit 4 originally directs the access to the actual configuration space unit 5 to the pseudo configuration space unit 6 mapped on the memory (not shown). A register indicating system configuration information exists in the configuration space, and configuration information is set in the pseudo configuration space unit 6 based on a chipset configuration table 8 created in advance.

  In this way, it is possible to access the pseudo-configuration space 6 without using the chipset to be controlled, and to check the result output to the memory to take into account the configuration variations of firmware for new models Tests can be performed.

  Each component will be described below.

  The BIOS execution unit 1 is a firmware that holds the BIOS and manages startup control / operation control of the computer system, and includes a chipset initialization processing unit 2 as one of them.

  The chipset initialization processing unit 2 is one of the POST processes, and executes a routine for performing initialization processing such as resource allocation to the configuration space of the chipset. The processing unit 4 is configured.

  The conventional machine processing unit 3 is in charge of initialization processing for the conventional machine chip set, and the conventional machine accesses the actual configuration space part 5 and does not operate on the new model chip set.

  The new model processing unit 4 is in charge of initialization processing for the new model chipset, accesses the pseudo configuration space unit 6 in the conventional machine, and accesses the actual configuration space unit 5 when the new model is transferred. This switching of operation is realized by switching a terminal process for accessing the configuration space on the BIOS code with a compile switch.

  The actual configuration space unit 5 shows a configuration space of various devices constituting the chipset. This configuration space part is created on a register for setting device characteristics, types, operations, etc., and reading / writing to the actual configuration space part 5 enables operation as a chip set. In the actual configuration space unit 5, unique information of various devices is set as a hardware initial value, and configuration information of the conventional machine itself is set before handing off to the BIOS execution unit 1.

  The pseudo configuration space section 6 is a pseudo configuration space created on a memory, and can be used to emulate a chipset by showing it as an access to the configuration space for the new model processing section 4 on a conventional machine. Enable.

  The maintenance console 7 is a terminal for environment setting and operation. The contents of the chipset configuration table 8 specified here are reflected in the pseudo configuration space section 6 of the chipset.

  The chip set configuration table 8 holds a new model configuration pattern for evaluating each of the mounting information of various devices that constitute the chip set. Then, the BIOS execution unit 1 creates a pseudo configuration space according to the configuration designated by the maintenance console 7.

  Next, the operation of the present embodiment on the conventional machine will be described in detail with reference to the flowchart of FIG.

  When the test operation is started (step A1), the maintenance console 7 designates a new model configuration pattern which is a configuration pattern for a new model to be evaluated by the conventional machine held in the chipset configuration table 8. (Step A2).

  The new model configuration pattern includes the number of CPU ports and the number of PCIBOX, and is registered in advance in the chipset configuration table 8 as a table. The maintenance console 7 selects a new model configuration pattern by designating a number corresponding to INDEX in the chipset configuration table 8.

  The specific configuration of the new model configuration pattern is stored in the memory where the pseudo configuration space section 6 is created, and the chipset configuration table 8 stores the new model configuration pattern specified by the maintenance console 7. Output address to memory. At this time, the memory in which the pseudo configuration space unit 6 is created outputs the designated address to the new model processing unit 4. The new model processing unit 4 can know the configuration information pattern of the new model specified by the maintenance console 7 by referring to the address.

  Thereafter, the maintenance console 7 starts up the system, and then hands off to the BIOS execution unit 1 after designating the environment / configuration information of the conventional machine (step A3). At this time, the conventional machine processing unit 5 registers the initial hardware value of the chip set of the conventional machine and the environment / configuration information of the conventional machine itself specified by the maintenance console 7 in which the actual configuration space unit 5 is created. These contents are reflected in the actual configuration space section 5.

  Subsequently, the new model processing unit 4 creates the pseudo configuration space unit 6 with the address obtained in step A2 as active (step A4). Further, ALL1 is set in the pseudo configuration space other than the designated address. As a result, the pseudo configuration space unit 6 storing the new model configuration pattern designated for the access from the new model processing unit 4 can be shown as a master abort.

  After creating the pseudo configuration space section 6, the new model processing section 4 initializes the chip set to the pseudo configuration space section 6 (step A5).

  After the initialization of the chipset by the new model processing unit 4 is completed, the conventional machine processing unit 5 executes the POST process for the conventional machine, which is the original process (step A6). After the POST process is completed, a pseudo dump created by the new model processing unit 4 is obtained by collecting a memory dump of the pseudo configuration space unit 6 and comparing it with an expected value held in advance (step A7). It is possible to confirm whether the operation of the modulation space 6 is normal, and a subsequent test can be performed.

  In addition, since the setting of the conventional machine itself is completed in step A6, the OS is started as it is (step A8), and the BIOS operation for the new chipset can be verified.

  FIG. 3 is a block diagram showing the configuration of the emulation device according to the present invention mounted on a new model, and FIG. 4 is a flowchart showing the operation thereof.

  In the state shown in FIG. 3, since the installed model is a new model, the conventional machine processing unit 3, the pseudo configuration space unit 6, and the chipset configuration table 8 are placed in a non-operating state. Further, the new model processing unit 4 accesses the actual configuration space 5.

  When the test operation is started (step B1), the system is started by the maintenance console 7, initialization by hardware is started, and then handed off to the BIOS execution unit 1 (step B2). At this time, the new model processing unit 4 reflects the initial value of the hardware of the new model and the environment / configuration information specified by the maintenance console 7 in the actual configuration space unit 5.

  The new model processing unit 4 initializes the chip set for the actual configuration space (step B3). The POST process is executed and the OS is started as it is (step B4).

  The operation switching between the conventional machine shown in FIGS. 1 and 2 and the new model shown in FIGS. 3 and 4 is performed by a compile switch, and the source code is unified.

It is a block diagram which shows the principal part structure of the emulation apparatus by this invention. It is a flowchart which shows operation | movement of the apparatus shown in FIG. It is a block diagram which shows the principal part structure of the emulation apparatus by this invention. It is a flowchart which shows operation | movement of the apparatus shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 BIOS execution part 2 Chipset initialization process part 3 Conventional machine process part 4 New model process part 5 Real computer fog space part 6 Pseudo configuration space part 7 Maintenance console 8 Chipset configuration table

Claims (2)

A memory that stores multiple configuration patterns of a new computer system;
Registers that set the characteristics, types, and operations of the devices that make up the chipset of a conventional computer system;
For the new model configuration pattern stored in the memory, a chipset configuration table that stores an address corresponding to each new model configuration pattern;
A maintenance console which is a terminal for operating the computer system of the new model and the conventional model;
BIOS that stores characteristics, types, configuration information of operation and environment information of devices constituting conventional and new model chip sets, controls setting and writing operations to the memory and registers, and executes BIOS for performing emulation An execution unit, and
When the test operation is started, the maintenance console starts the computer system after designating a configuration pattern for a new model to be evaluated by the conventional machine held in the chipset configuration table, and then the conventional machine Specify environment / configuration information and handoff to the BIOS execution unit,
The chipset configuration table outputs an address storing a new model configuration pattern designated by the maintenance console to the memory,
The memory outputs the specified address to the BIOS execution unit,
When the BIOS execution unit is handed off from the maintenance console, the hardware initial value of the chipset of the conventional machine and the environment / configuration information of the conventional machine specified by the maintenance console are set in the register. emulation system chipset, characterized in that to create an address sent to you as an active pseudo configuration space in memory. A memory that stores multiple configuration patterns of a new computer system;
Registers that set the characteristics, types, and operations of the devices that make up the chipset of a conventional computer system
For the new model configuration pattern stored in the memory, a chipset configuration table that stores an address corresponding to each new model configuration pattern;
A maintenance console which is a terminal for operating the computer system of the new model and the conventional model;
BIOS that stores characteristics, types, configuration information of operation and environment information of devices constituting conventional and new model chip sets, controls setting and writing operations to the memory and registers, and executes BIOS for performing emulation An emulation method performed by a chipset emulation device comprising:
When the test operation is started, the maintenance console starts the computer system after designating a configuration pattern for a new model to be evaluated with the conventional machine held in the chipset configuration table, and then Designating machine environment / configuration information and handing off to the BIOS execution unit;
Outputting the address at which the chipset configuration table stores a new model configuration pattern designated by the maintenance console to the memory;
And outputting an address where the memory is designated to the BIOS execution unit,
After the BIOS execution unit is handed off from the maintenance console, the hardware initial value of the chipset of the conventional machine and the environment / configuration information of the conventional machine specified by the maintenance console are set in the register, and the memory emulation method chipset and having the steps of: creating a pseudo configuration space in the memory by an address which has been sent more active.

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