JP5387521B2 - Logic verification scenario generation device and logic verification scenario generation program - Google Patents

Description

  The present invention relates to a logic verification scenario generation device and a logic verification scenario generation program.

  In recent years, an integrated circuit (for example, LSI: Large Scale Integration) used in an electronic device or the like is generally designed by RTL (Register Transfer Level) description using HDL (Hardware Description Language). Then, logic verification is performed in order to check whether the designed integrated circuit operates normally.

  The logic verification of the integrated circuit is performed in a logic verification environment such as a simulator constructed on a computer, for example. The verifier manually prepares a test pattern including an input signal pattern or the like based on a specification or the like, and executes and verifies the integrated circuit to be verified on the simulator based on the test pattern. In addition, the verifier prepares in advance an expected output value as a result of the simulation, and verifies whether or not the output value obtained as a result of the simulation matches the expected value.

  However, in recent years, the number of test patterns has become enormous due to large-scale integration of integrated circuits and complicated functions, and the load on generation has increased. In addition, there are problems with verification omissions and verification errors caused by manually generating test patterns. Therefore, input condition information such as a peripheral device list connected to the integrated circuit to be verified and parameter setting information of the device list is prepared in advance, and the verification scenario executed by the simulator is automatically based on the input condition information. The technique to generate | occur | produce is known (patent document 1).

JP 2008-210004 A

  However, when the integrated circuit to be verified is a CPU (Central Processing Unit), the processing operation of the integrated circuit based on the input signal is affected by a combination of instructions executed before and after the instruction executed by the CPU. Therefore, when the verification target integrated circuit is a CPU, logic verification based on a test program having a plurality of instructions is required. Further, the processing operation based on the input signal of the CPU is also affected by external input factors such as an interrupt instruction generated when the instruction is executed. Therefore, in addition to the combination of a plurality of instructions, logic verification for an external input factor is also necessary.

  In addition, with the increase in test patterns due to the increase in scale and complexity of integrated circuits, the amount of expected values for verifying simulation output values has become enormous, and the load on generating expected values has been high.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a verification scenario used for CPU logic verification described in RTL (Register Transfer Level), a logic verification scenario generation device and a logic verification scenario generation program that suppress generation load of expected values. And

A first aspect is a logic verification scenario generation device for generating a test program for CPU logic verification described in RTL,
A test library for storing a verification instruction list having a plurality of verification instructions, a front instruction executed before the verification instruction, and a front and rear instruction combination list having a plurality of front and rear instruction combinations of subsequent instructions executed after the verification instruction;
An expected value format storage unit that stores an expected value format having one or a plurality of output signal items that the CPU executes and outputs the instructions;
A verification instruction address for storing the verification instruction, a previous instruction space for storing the previous instruction, a subsequent instruction space for storing the subsequent instruction, and a data space to be accessed when the instruction is a data access instruction A memory module having a branch instruction space for storing a branch destination instruction when the instruction is a branch instruction, and a stack space for storing return information when the instruction is a return instruction after branching, Based on the verification instruction sequentially selected from the test library and the combination of the preceding and following instructions, the verification instruction is stored in the verification instruction address, the previous instruction is stored in the previous instruction space, and the subsequent instruction is stored in the subsequent instruction space. In addition, when the previous instruction is the branch instruction, a memory module storing the verification instruction address in the branch destination address of the previous instruction is stored in the test module. And test program generation unit for generating as a program,
For each instruction of the generated test program, the expected value format corresponding to the instruction is acquired from the expected value format storage unit, and an expected value corresponding to the output signal item is obtained based on decoding information obtained by decoding the instruction. An expected value generator to generate;
Have

  According to the first aspect, it is possible to suppress the load for generating the verification scenario and the expected value.

It is a figure showing an example of the input-output signal of CPU for logic verification. It is a figure showing an example of CPU described in RTL in this embodiment. It is a figure showing an example of the module and the test bench which a simulator performs. It is a figure showing the structure of the logic verification scenario production | generation apparatus in this Example. It is a flowchart figure showing the process of a logic verification scenario production | generation part. It is a figure showing a test library. It is a figure showing the memory space which the memory module in this embodiment defines. It is an example of the test program in a 1st embodiment. It is a flowchart figure showing the process of expected value generation. It is a flowchart figure showing the verification scenario element decomposition | disassembly process of an expected value production | generation part. It is a flowchart figure showing expected value format selection processing. It is a figure showing the expected value format in the example of this Embodiment. It is a figure showing the expectation value format corresponding to the test program of FIG. It is a figure showing the expectation value corresponding to the test program of FIG. It is a figure showing an external input factor list | wrist and an external input timing list | wrist. It is a figure showing an example of the external input signal generation module of interruption. It is an example of a test program in the second embodiment. It is a figure showing the expected value format corresponding to the test program of FIG. It is a figure showing the expected value corresponding to the test program of FIG. It is a block diagram of the computer with which the simulator in this embodiment operates.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the technical scope of the present invention is not limited to these embodiments, but extends to the matters described in the claims and equivalents thereof.

  The logic verification scenario generation device according to the present exemplary embodiment includes verification scenario conditions such as “verification instruction”, “verification instruction” stored before and after “verification instruction”, and “verification instruction combination” executed before and after “verification instruction”. Select from the test library. Then, the logic verification scenario generation device defines a memory space that is divided in advance according to usage, and stores the “verification instruction” in the “verification instruction address”, the previous instruction in the previous instruction space, and the subsequent instruction in the subsequent instruction space. When the previous instruction is a branch instruction, a test program is generated by generating, as a test program, a memory module described so that “verification instruction address” is stored in the branch destination address of the previous instruction. Then, the logic verification scenario generation device acquires, for each instruction of the test program, an expected value format corresponding to the instruction from the expected value format storage unit, and an output signal of the expected value format based on the decode information obtained by decoding the instruction An expected value corresponding to the item is generated.

  FIG. 1 is a diagram illustrating an example of input / output signals of a CPU (Central Processing Unit) 10 to be logically verified. In the figure, the CPU 10 is described in RTL (Register Transfer Level), and similarly inputs / outputs signals to / from the memory module 12, external input signal generation module 11, and output signal trace module 13 described in RTL via a bus. .

  In general, the CPU 10 performs an instruction cycle such as fetching, decoding, and executing an instruction by inputting and outputting signals to and from a memory. Specifically, the input signal from the memory module 12 to the CPU 10 includes a read data signal for instruction fetch and a data access generated by execution of the instruction. Output signals from the CPU 10 to the memory module 12 include an access strobe signal, an access size signal, a read / write signal, a write data signal, an address signal, and the like.

  Further, the CPU 10 receives an interrupt request from the external input signal generation module 11 and an external input signal for controlling the state of the CPU 10. Specifically, input signals from the external input signal generation module 11 to the CPU 10 include signals such as a clock signal CLK, a reset signal RST, a mode signal, an interrupt signal, an exception signal, and a break signal. When the CPU 10 receives the external input signal, the CPU 10 interrupts the process being executed, for example, executes a predetermined processing routine according to the external input signal, controls the CPU state, and the like.

  The memory module 12 of the present embodiment is a memory such as a RAM (Random Access Memory) described in RTL, and stores a test program for logically verifying the CPU 10. The CPU 10 inputs and outputs signals as shown in FIG. 1 through execution of instructions of the test program. The external signal generation module 11 is a peripheral resource such as a pseudo timer, interrupt controller, and debugger described in RTL, and inputs an external input signal as shown in FIG.

  The output signal trace module 13 acquires an access size signal, a read / write signal, a write data signal, an address signal, and the like at the time of data access that are output from the CPU 10 to the memory module 12 through execution of the instruction. The output signal trace module 13 also outputs an instruction address signal indicating the address of the execution instruction from the CPU 10, a branch information signal indicating that the instruction is a branch source and a branch destination, a branch factor signal indicating a branch factor, and an instruction externally. An EIT factor signal indicating a factor such as an interrupt or an exception when an input signal is generated, a CPU status signal indicating a state of the CPU 10 such as a debug mode, and the like are acquired. The output signal acquired by the output signal trace module 13 is compared with an expected value to be described later in order to verify the logical correctness of the instruction processing of the CPU 10.

  FIG. 2 is a diagram illustrating an example of the CPU 10 described in RTL according to the present embodiment. The CPU 10 is described in RTL level HDL such as verilog HDL (Hardware Description Language) and VHDL (VHSIC Hardware Description Language), and has the function of each block as shown in FIG.

  In the “definition of signal” block 101, signals input / output by the CPU 10 and signals used in the CPU 10 are declared. In the “instruction fetch” block 102, a process of reading out an instruction to be executed from the memory module 12, and in a “decode” block 103, a process of decoding an instruction read out by the fetch into an instruction executable by the CPU 10, and A data selection process necessary for the arithmetic process is described. The “arithmetic” block 104 describes numerical arithmetic and PC (program counter) calculation processing, and the “memory access” block 105 describes memory read / write processing when the execution instruction is a load / store instruction. The Further, the “write back” block 106 describes a process of writing data to the register.

  Although not shown, the memory module 12, the external input signal generation module 11, and the output signal trace module 13 are similarly described in HDL such as verilog HDL and VHDL.

  The CPU 10, memory module 12, external input signal generation module 11, and output signal trace module 13 described in FIGS. 1 and 2 are executed by software such as a simulator that runs on an OS on a computer. The simulator simulates each module based on a test bench describing initial value settings and simulation procedures for each module. The test bench is also described in HDL.

  FIG. 20 is a diagram illustrating a configuration of a computer 200 on which a simulator operates. The computer 200 includes a CPU 202, a RAM 203, an external I / F 204, and a memory (file group) 205. The simulator is realized by the CPU 202 executing the logic verification simulation program 201 stored in the memory (file group) 205.

  The simulator according to the present embodiment is provided with a CPU (RTL) 10 to be logically verified, a test library 214 having a verification instruction group and the like, and an expected value format storage unit 221. The simulator first executes logic verification scenario generation programs (RTL) 21 and 22, and stores a test program used for logic verification of the CPU (RTL) 10 based on the test library 214 and the expected value format storage unit 221. Memory module (RTL) 12, external input signal generation module (RTL) 11 that generates an external input signal to CPU (RTL) 10, and expected value data having an expected value of a signal output from CPU (RTL) 10 by simulation (Data file) 25 is generated (206).

  Then, the simulator causes the CPU (RTL) 10 to execute the test program stored in the memory module 12, and also causes the external input signal module (RTL) 11 to input an external input signal. Logic verification is performed (207). Further, the simulator executes the output signal trace module (RTL) 13 and acquires an output signal from the CPU (RTL) 10 (207).

  FIG. 3 is a diagram illustrating an example of a module and a test bench 30 executed by the simulator according to the present embodiment. The logic verification scenario generation unit 21 and the expected value generation unit 22 are an example of the logic verification scenario generation device according to the present embodiment. The logic verification scenario generation programs (RTL) 21 and 22 in FIG. 20 are executed by a simulator. It is realized by doing.

  The logic verification scenario generation unit 21 generates the memory module 12 storing the test program and the external input signal generation module 11 based on the sequentially selected verification scenario conditions. Then, the expected value generation unit 22 obtains an expected value format corresponding to each instruction from the expected value format storage unit 221 for each instruction of the generated test program, and expects an output signal item corresponding to the expected value format. Value data 25 is generated. The expected value is a value obtained by predicting in advance an output signal output by the CPU 10 by executing a test program instruction. Details of the processing of each unit will be described later.

  The result comparison unit 23 compares the trace data having the output signal acquired by the output signal trace module 13 with the expected value data 25 generated by the expected value generation unit 22, and compares the comparison result with the simulator output unit 24. Write to log file. However, instead of the result comparison unit 23, the verifier may compare the trace data with the expected value data 25. The result comparison unit 23 is similarly described in HDL.

  The logic verification scenario generation unit 21 and the expected value generation unit 22 in the first embodiment are storage addresses in the memory module 12 of “verification instructions” and “verification instructions” to be executed by the CPU 10 as verification scenario conditions. A memory module 12 storing a test program based on a combination of “verification instruction address” and a “previous instruction combination” representing a combination of a previous instruction to be executed by the CPU 10 before the “verification instruction” and a subsequent instruction to be executed later. And expected value data 25 are generated.

  The logic verification scenario generation unit 21 and the expected value generation unit 22 in the second embodiment further include an “external input factor” input to the “verification instruction” as the verification scenario condition, and the “external input factor” The memory module 12 storing the test program, the expected value data 25, and the external input signal generation module 11 are generated based on the combination of the verification scenario conditions including the “external input timing”.

[First Embodiment]
FIG. 4 is a diagram illustrating the configuration of the logic verification scenario generation device according to the present embodiment. In the figure, the external input signal generation unit 213 and the external input signal generation module 11 represented by dotted lines will be described later in the second embodiment.

  The logic verification scenario generation unit 21 includes a test library 214, a verification scenario condition input unit 210, a program condition determination unit 211, and a test program generation unit 212, and generates the memory module 12 storing the test program. In addition, the expected value generation unit 22 selects the corresponding expected value format from the expected value format storage unit 221 for each instruction of the test program, and generates expected value data 25 corresponding to the output signal item of the expected value format. .

  FIG. 5 is a flowchart showing processing of the logic verification scenario generation unit 21 in the present embodiment. Hereinafter, description will be given based on a flowchart. First, the verification scenario condition input unit 210 of the logic verification scenario generation unit 21 receives an input of the verification scenario condition 215 (S101). The verification scenario condition input unit 210 receives a combination of “verification instruction”, “verification instruction address”, and “previous instruction combination” stored in the test library 214 as the verification scenario condition 215.

  FIG. 6 is a diagram illustrating the test library 214. The test library 214 stores a verification instruction list CM having a plurality of “verification instructions”, a verification instruction address list CM @ having a plurality of “verification instruction addresses”, and a front / rear instruction combination list CML having a plurality of “front / rear instruction combinations”. . Each list is prepared in advance by a verifier or the like, for example.

  Specifically, the “verification instruction” is an instruction such as “ADD R1, R2”, “JMP @ R6”, and the “verification instruction address” is an address on the memory space defined by the memory module 12, for example, “0x00000100” "0x00000050". The “front / rear instruction combination” is a combination of processes to be executed by the CPU 10 before and after the “verification instruction”. For example, “(previous instruction) arithmetic processing A / (post instruction) arithmetic processing B” “(previous instruction) arithmetic” Process A / (post instruction) branch process A ”and the like. Each of the front instruction and the rear instruction has one or a plurality of instructions.

  As shown in FIG. 6, in the test library 214, “verification instruction”, “verification instruction address”, and “before / after instruction combination” are associated with identification symbols such as numbers “1 to n”, for example. The verification scenario condition input unit 210 receives a combination of identification symbols as the verification scenario condition 215.

  Returning to the flowchart of FIG. 5, the verification scenario condition input unit 210 verifies whether or not the selected verification scenario condition 215 corresponds to the specification restriction of the CPU 10 (S102). The verification scenario condition input unit 210 compares the combination of identification symbols of the selected verification scenario with the combination of identification symbols of the verification scenario condition corresponding to the specification restriction (YES in S102), and generates a test program Exit. The combination information of the verification scenario conditions corresponding to the specification restriction is prepared in advance by a verifier or the like.

  On the other hand, when the selected verification scenario condition does not correspond to the specification limitation of the CPU 10 (NO in S102), the verification scenario condition input unit 210 divides the selected verification scenario condition 215 as the verification scenario condition determination process, The “instruction” is passed to the verification instruction selection process S104, the “front and rear instruction combination” is passed to the front and rear instruction selection process S105, and the “verification instruction address” is passed to the verification instruction address selection process S106 (S103). Then, the program condition determination unit 211 selects “verification instruction” from the test library 214 based on the identification symbol of “verification instruction” as verification instruction selection processing (S104). Similarly, the logic verification scenario generation unit 21 sets the previous instruction and the subsequent instruction based on the identification symbol of “front / rear instruction combination” as the preceding / following instruction selection process (S105) and sets the “verification instruction address” as the verification instruction address selection process. Based on the identification symbol, “verification instruction address” is selected from the test library 214 (S106).

  Subsequently, the test program generation unit 212 of the logic verification scenario generation unit 21 generates a test program based on the selected “verification instruction”, “verification instruction address”, and “before / after instruction combination” (S107). The test program generating unit 212 assigns the “verification instruction address” in the memory space to the “verification instruction address” on the memory space divided according to the use defined by the memory module 12, and the previous instruction and the subsequent instruction of the “previous instruction combination” in the memory space. The memory module 12 is described and generated so as to be stored in the preceding instruction space and the subsequent instruction space. That is, the generation of the test program means generation of the memory module 12 accessed by the simulation target CPU 10, and the test program is described in association with each space address defined by the memory module 12 described in RTL.

  FIG. 7 is a diagram showing a memory space defined by the memory module 12 in the present embodiment. The memory space in this embodiment is divided according to use, and the address of each space is determined in advance. First, the “preceding instruction space” 71 is a space for storing the preceding instruction, the “following instruction space” 72 is a space for storing the following instruction, and the “branch destination instruction space” 73 is a case where the instruction of the test program is a branch instruction. Branch destination instructions are stored in advance. The “data space” 74 is an access space when the test program instruction is a data access instruction. For example, access data is stored in advance.

  The “stack space” 75 is a space in which, for example, information on the next instruction at the branch source is stored as return information to the branch source when the instruction of the test program is a branch instruction. Further, the “break space” 76 stores in advance branch destination instructions when the test program instruction is, for example, a break instruction for debugging. The “vector table” 78 stores the address of the “EIT routine space” 77 that stores the post-branch instruction when a branch instruction such as a trap instruction is executed. The “vector table” 78 is also referred to when an external input factor occurs, but details will be described later in the second embodiment.

  Specifically, the test program generation unit 212 stores “verification instruction” in the “verification instruction address” in the memory space, the previous instruction in the “previous instruction space” 71, and the subsequent instruction in the “rear instruction space” 72. Describes the memory module 12. In addition, when the previous instruction is a branch instruction, the test program generation unit 212 describes the memory module 12 so that the “verification instruction address” is stored in the branch destination address of the previous instruction. Thus, during the logic verification simulation, when the previous instruction is a branch instruction, the CPU 10 branches to the “verification instruction address” by the branch instruction and executes the “verification instruction”.

  Here, a test program generation process of the logic verification scenario generation unit 21 will be described based on a specific example. For example, the verification scenario condition input unit 210 includes “3 (CALL @ R6)” in the verification instruction list, “1 (0x00000100)” in the verification instruction address list, and “3 ((previous instruction) in the preceding and following instruction combination list” in FIG. A verification scenario condition of a combination of “branch process A / (post instruction) arithmetic process A)” is received (S101). When the received verification scenario condition does not correspond to the specification limitation of the CPU 10 (NO in S102), the program condition determination unit 211 passes the divided verification scenario condition to each selection process (S103).

Subsequently, the program condition determination unit 211 sets “CALL @ R6” corresponding to “3” in the verification instruction list CM to “1” in the verification instruction address list CM @ from the test library 214 of FIG. “0x00000100” is acquired as “(previous instruction) branch process A / (post instruction) arithmetic process A” corresponding to “3” in the preceding / following instruction combination list CML (S104 to 106). Specifically, the branch process A is the next instruction.
“LDI: 32 (branch destination address), R5”
“LDI: 32 0x00000500, R6”
"JMP @ R5"
The arithmetic processing A is the next instruction.
“LDI: 320 × 00000300, R1”
Then, the test program generation unit 212 sends the verification instruction “CALL @ R6” to the verification instruction address “0x00000100” in the memory space, and the branch process A “LDI: 32 (branch destination address), R5” to the “previous instruction space” 71. “LDI: 32 0x00000500, R6” and “JMP @ R5” describe the memory module 12 so that arithmetic processing A “LDI: 32 0x00000300, R1” is stored in the “rear instruction space” 72. Further, since the previous instruction is a branch instruction, the test program generating unit 212 describes the memory module 12 so that the verification instruction address “0x00000100” is stored in the (branch destination address) 81 of the previous instruction.

  FIG. 8 is an example of the memory module 12 that stores a test program generated based on the verification scenario condition. As shown in the figure, the branch processing A is stored in the “previous instruction space” 71, the arithmetic processing A is stored in the “following instruction space” 72, and the verification instruction “CALL @ R6” is stored in the verification instruction address “0x00000100”. Further, the verification instruction address “0x00000100” is stored in the (branch destination address) 81 of the branch process A.

  According to the memory module 12 of FIG. 8, in the logic verification simulation, the CPU 10 first executes the previous instructions “LDI: 32 0x00000100, R5”, “LDI: 32 0x00000500, R6”, and “JMP @ R5”. Since “JMP @ R5” is a branch instruction, the CPU 10 then branches to the branch destination address indicated by “@ R5”. Since the verification instruction address “0x00000100” 81 is assigned to “@ R5”, the CPU 10 branches to the verification instruction address and executes the verification instruction “CALL @ R6”.

  Since the verification instruction “CALL @ R6” is also a branch instruction, the CPU 10 branches to the branch destination address “0x00000500” 82 indicated by “@ R6”, that is, the address of the “branch destination instruction space” 73, “ADD R7, R8” and “RET” are stored. Since “RET” is a return instruction to the branch source, the CPU 10 returns to the branch source and executes the next instruction “LDI: 32 0x00000300, R1” which is the next instruction. In this way, the test program is executed.

  As described above, when the previous instruction is a branch instruction in the memory module 12 described in RTL, the test program generation unit 212 describes the “verification instruction address” in the branch destination address of the previous instruction, so that the previous instruction is Even for a branch instruction (JMP in the above example), it is possible to generate a memory module 12 of a test program in which instructions are executed in the order of “verification instruction” after the previous instruction and then the subsequent instruction.

  When the “verification instruction” or the subsequent instruction is a branch instruction, the address of the “branch destination instruction space” 73 in which the branch destination instruction is stored in advance is specified as the branch destination address of the instruction (CALL in the above example). Therefore, the test program generation unit 212 can use a branch destination instruction prepared in advance, and does not have to generate a branch destination instruction.

  In this way, the test program generation unit 212 designates a branch instruction (branch instruction, break instruction, etc.) that designates a space address that stores a branch destination instruction as a branch destination address, and designates a space address for data access as an access address. The data access command thus prepared is prepared in advance as a “verification command” and a front and rear command. As a result, the test program generation unit 212 stores “verification instruction” in “verification instruction address” and “previous instruction space” 71 “after instruction space” 72 in the memory space defined by the memory module 12. In addition, when the previous instruction is a branch instruction, the memory module of the test program having a plurality of instructions is simply described so that the “verification instruction address” is stored in the branch destination address of the previous instruction. 12 can be generated.

  Next, expected value generation processing will be described.

  FIG. 9 is a flowchart showing the expected value generation process. First, the expected value generation unit 22 reads the first instruction from the start address in the test program of the memory module 12 (S121). Next, the expected value generation unit 22 performs element decomposition processing on the read instruction (S122).

  FIG. 10 is a flowchart showing the verification scenario element decomposition process (S122 in FIG. 9) of the expected value generation unit 22. The expected value generation unit 22 decodes the read instruction to generate decode information, and passes it to the instruction type determination process S123 (S141). The process of S142 will be described in the second embodiment. Next, based on the decode information, the expected value generation unit 22 passes the branch presence / absence information of the instruction to the branch determination process S125 (S143), and passes the decode information and the address information of the instruction to the data extraction process S126 ( S144).

  Returning to FIG. 9, subsequently, the expected value generation unit 22 determines the instruction type based on the decode information as the instruction type determination process, and sets the format number of the expected value format corresponding to the instruction type as the expected value format selection process. It passes to S127 (S123). In this case, the expected value generation unit 22 can determine the content of the instruction and the instruction type such as the operation system, the load / store system, the branch system (1 to 4), and the trap system based on the instruction decode information. . In addition, as the branch determination process, the expected value generation unit 22 passes the branch format number to the expected value format selection process S127 when there is a branch based on the branch presence / absence information (S125).

  FIG. 12 is a diagram illustrating an expected value format. The expected value format is prepared for each instruction type having one or a plurality of output signal items to be output by executing a certain instruction by the CPU 10 and outputting the same output signal item. The output signal item in the expected value format includes a fixed value in which the expected value is predicted in advance based on the instruction type and the external input factor, and a non-fixed value generated on the basis of instruction decoding information and the like. In the figure, fixed values are underlined and unfixed values are italicized. The output signal items are not limited to the example shown in the figure, and differ depending on the CPU 10 to be verified.

  Each output signal item will be described. The “instruction address” is an address of a memory space where an instruction is stored. The “branch information” is information indicating whether the instruction is a branch source or a branch destination, and “branch factor” is the branch factor. The “EIT factor” will be described later in the second embodiment. “CPU state” is information representing the state of the CPU 10. “Access address” is the address at which the data to be accessed by the data access instruction is stored, “RW information” is information about writing or reading, “Access size” is the data size to be accessed, “Write data” “Read data” "Is data information to be accessed.

  The expected value format for an instruction of the “(1) arithmetic system” type has output signal items of “instruction address” and “CPU state”, for example. The expected value format corresponding to the “(2) load type” and “(3) store type” instructions includes “access address” and “RW information” in the load and store processes in addition to “instruction address” and “CPU state”. ”,“ Access size ”, and“ read data / write data ”output signal items. The “RW information” is a fixed value because it can be predicted in advance based on the types of “(2) load system” and “(3) store system”.

  The expected value format for an instruction of the type “(4) Branch 1 (JMP system)” includes, for example, “branch information” and “branch factor” output signal items in addition to “instruction address” and “CPU state”. Have. Since JMP instructions always have “branch information / branch source” and “branch factor / instruction branch”, “branch information” and “branch factor” are fixed values.

  When the CALL instruction is executed, the CPU 10 writes the return information (address of the next instruction) from the branch by the CALL instruction in the “stack space” 75. Therefore, the expected value format for an instruction of the type “(5) Branch 2 (CALL type)” is, for example, in addition to the output signal item similar to “(4) Branch 1 (JMP type)”, It has output signal items of “access address”, “RW information”, “access size”, and “write data” in the process of writing the return information to the “stack space” 75. Note that “RW information” in the restoration information writing process is a fixed value “W”, and “access size” is a fixed value “4” determined based on the specifications of the CPU 10.

  The RET instruction (return instruction) is an instruction executed to return from the branch destination to the branch source. By reading the return information (the address of the next instruction of the branch source) from the “stack space” 75, the branch source is read. Return. Therefore, the expected value format for the instruction of the type “(6) Branch 3 (RET)” includes two lines in addition to “instruction address”, “branch information”, “branch factor”, and “CPU state” on the first line. It has output signal items of “access address”, “RW information”, “access size”, and “read data” in the read information read processing from the “stack space” 75 of the eye. Similarly, “branch information”, “branch factor”, “RW information”, and “access size” are fixed values for which expected values are predicted in advance depending on the instruction type.

  Similar to the RET instruction, the RETI instruction is an instruction executed to return from the branch destination to the branch source, and reads the program status from the “stack space” 75 in addition to the address of the next instruction as return information. Therefore, the expected value format for the instruction of the “(7) Branch 4 (RETI)” type is the same as the expected value format of the “(6) Branch 3 (RET)” type. And an output signal item in the program status read processing in the third row. The fixed value is the same as the expected value format of “(6) Branch 3 (RET)” type.

  When executing an instruction of “(8) trap system” type, the CPU 10 reads out the address of the trap routine in the “EIT routine space” 77 from the “vector table” 78 and returns information (program status) from the branch by the trap instruction. , The address of the next instruction) is written into the “stack space” 75. Therefore, the expected value format for the instruction of the “(8) trap system” type includes “instruction address”, “branch information”, “branch factor”, and “CPU state” in the first line, It has an output signal item in the read processing from the “vector table” 78 and the return information write processing in the “stack space” 75 in the third, fourth and fourth lines. The fixed value is “EIT factor / trap” in addition to the output signal item similar to the expected value format of the “(6) branch 3 (RET)” type.

  Note that the “(12) branch instruction” expected value format is an expected value format for branch added when the instruction is a branch instruction, and the value of the “format composition” item of the other expected value formats is “ In contrast to “OFF”, the value of the item is “ON”. The expected value format “(12) for branch instruction” is added to the expected value format corresponding to the instruction type when the instruction is a branch instruction, and is synthesized with the expected value format of the instruction to be executed next. Note that the expected value format (9 to 11) corresponding to the external input factor will be described later in the second embodiment.

  Returning to FIG. 9, the expected value generation unit 22 selects the expected value format of the instruction based on the format number by the instruction type determination process and the format number for branch by the branch determination process as the expected value format selection process. (S127).

  FIG. 11 is a flowchart showing the expected value format selection process (S127). The expected value generation unit 22 acquires the expected value format of the format number corresponding to the instruction type from the expected value format storage unit 221 (S151). Then, if there is a branch (YES in S152), the expected value generation unit 22 acquires the expected value format for branch from the expected value format storage unit 221 and adds it to the expected value format corresponding to the instruction type (S153). ), And confirms the format (S154). On the other hand, when there is no branch (NO in S152), the expected value generation unit 22 determines the expected value format corresponding to the instruction type as the format (S154).

  Returning to FIG. 9, the expected value generation unit 22 performs decoding information, memory space address, based on the decoding information obtained by decoding the instruction passed from the verification scenario element decomposition processing (S122) as the data extraction processing. Data is extracted from the memory information or the like stored at the address and passed to the expected value generation process (S126). The expected value generation unit 22 generates an expected value corresponding to the output signal item in the expected value format based on the extracted data (S128), and stores it as expected value data 25 in a memory or the like (S129).

  Then, the expected value generation unit 22 confirms whether expected values have been generated for all the instructions of the test program after the expected value generation processing (S130). Specifically, the expected value generation unit 22 determines whether or not expected values have been generated for all the instructions of the test program depending on, for example, whether or not the instruction address has reached the end of the “rear instruction space” 72. .

  If there is an instruction that has not generated an expected value (NO in S130), the instruction length is added to the instruction address of the instruction that generated the expected value, and the instruction address of the next instruction is acquired (S131). At this time, if the instruction that generated the expected value is a branch instruction, the branch destination instruction address of the branch instruction is acquired. Then, the next instruction is read from the test program in the memory module 12 based on the acquired instruction address, and an expected value is generated (S121 to S129). As described above, the expected value generation unit 22 generates expected values in the order of execution from the first instruction of the test program.

  On the other hand, when expected values are generated for all the instructions of the test program (YES in S130), the expected value generating unit 22 ends the expected value generating process. Then, the simulator performs logic verification of the CPU 10 based on the generated memory module 12 and the expected value of the test program. Then, after the logic verification, the logic verification scenario generation unit 21 receives the next verification scenario condition and similarly performs the generation process of the memory module 12 and the expected value of the test program.

  A specific example of expected value generation based on the test program of FIG. 8 will be described below. The expected value generation unit 22 reads the first instruction “LDI: 32 0x100000100, R5” of the test program (S121). Then, as the verification scenario element decomposition process (S122), the expected value generation unit 22 decodes the instruction to determine that the instruction is “LDI: 32” and that there is no branch, and to the instruction type determination process At the same time (S141 in FIG. 10), the information indicating no branch is passed to the branch determination process (S143 in FIG. 10). Further, the expected value generation unit 22 passes the decode information and the address information “0x00000000” of the instruction “LDI: 32” to the data extraction process (S144 in FIG. 10).

  Subsequently, since the “LDI: 32” instruction is an arithmetic instruction, the expected value generation unit 22 sets the format number “1” corresponding to the arithmetic instruction (S123), based on information indicating no branching. Then, the information without the expected value format for branching is passed to the format selection process (S125). Then, based on the format number “1” (S151) corresponding to the instruction type and the information on the absence of the expected value format for branching (NO in S152), the expected value generation unit 22 is based on the flowchart of FIG. The expected value format “1” is acquired from the expected value format storage unit 221 to determine the format (S154). In this way, the expected value format “1” corresponding to the instruction “LDI: 32 0x00000100, R5” is selected.

  FIG. 13 is a diagram showing an expected value format corresponding to each instruction of the test program of FIG. As described above, the expected value format corresponding to the instruction “LDI: 32 0x00000100, R5” is “1” (a). Since the instruction “JMP @ R5” is a JMP branch instruction, in addition to the expected value format “(4) branch 1 (JMP system)” (c), the expected value format for branch “(12) branch” “For command” (d) is selected. Similarly, since the verification instruction “CALL @ R6” is a CALL branch instruction, in addition to the expected value format “(5) branch 2 (CALL system)” (e−1, 2), the expected value for branching The format “(12) for branch instruction” (f) is selected.

  FIG. 14 is a diagram showing expected values corresponding to the test program of FIG. In the drawing, (a) “instruction address / 0x00000000” and “CPU state / state A” are generated as expected values of output signal items of the instruction “LDI: 32 0x00000100, R5”. Specifically, the expected value generation unit 22 performs the data extraction process of the instruction “LDI: 32 0x100000100, R5” based on the fact that the instruction “LDI: 32” is not an instruction that controls the state of the CPU based on the decode information. An initial CPU state “state A” and an instruction address “0x00000000” are extracted (S126). Then, based on the extracted data, the expected value generation unit 22 generates expected values “CPU state / state A” and “instruction address / 0x00000000” of the output signal item of the expected value format “1” (S128).

  Further, for the instruction “JMP @ R5”, the expected value generation unit 22 similarly determines that “state A” and the instruction of the instruction “JMP” are not instructions that control the state of the CPU based on the decode information. Extract the address "0x0000000C". As a result, for the expected value format (c in FIG. 14) of the instruction “JMP @ R5”, in addition to the fixed values “branch information / branch source” and “branch factor / instruction branch”, “instruction address / 0x0000000C”, “CPU State / state A "is generated as the expected value. Similarly, for the expected value format for branching (d in FIG. 14), “branch information / branch destination”, “branch factor / instruction branch”, and “CPU state / state A” are generated as expected values.

  With respect to the instruction “CALL @ R6”, the expected value generation unit 22 uses “decoding information” in addition to “CPU state” and “instruction address”, “access address in writing processing of return information accompanying the CALL instruction to the stack space ”Is extracted as the write address“ 0x000007FC ”of the stack space, and“ 0x00000102 ”of the next instruction of the branch source is extracted as“ write data ”. As a result, the fixed value “branch information / branch source”, “branch factor / branch source”, “RW information / W”, “access” for the expected value format (e-1, 2 in FIG. 14) of the instruction “CALL @ R6”. In addition to “size / 4”, “instruction address / 0x00000100”, “CPU state / state A”, “access address / 0x000007FC”, and “write data / 0x00000102” are generated as expected values.

  In addition, the expected value generation unit 22 generates an expected value format (d) for a branch whose format composition item is “ON” and an expected value format (e-1) at the beginning of the next instruction “CALL @ R6”. The combined expected value format (d, e-1) is generated. Specifically, the expected value generating unit 22 combines the expected value for output signal items having the same expected value, and the synthesized value “branch information / branch destination” (d, e) for output signal items having different expected values. -1) is generated as an expected value.

  As described above, the expected value format of “(12) for branch instruction” shown in FIG. 12 is combined with the expected value format of the next instruction, so that the expected value generation unit 22 can execute the branch destination instruction (above In the example, for CALL), an expected value indicating that it is a branch destination instruction can be generated. In addition, since the expected value format has a fixed value (expected value) predicted in advance based on the instruction type, the expected value generation unit 22 may generate the expected value only for the non-fixed value.

  In this way, the expected value generation unit 22 acquires an expected value format having an output signal item corresponding to an instruction, and generates an expected value corresponding to the output signal item based on the decode information of the instruction. In addition, the expected value generation unit 22 further generates an expected value based on the address of the instruction, the address of the memory space divided according to the application based on the decode information, and the memory information stored in advance at the address. Thereby, the expected value generation unit 22 can generate an expected value in which a signal output by the CPU 10 executing each instruction of the test program is predicted.

  As described above, the logic verification scenario generation device according to the present embodiment sequentially selects combinations of “verification instruction”, “verification instruction address”, and “previous instruction combination” from each list of the test library 214 as verification scenario conditions. . Then, the logical verification scenario generation device, based on the selected verification scenario condition, the previous instruction in the “previous instruction space” 71 of the memory space classified by use, the subsequent instruction in the “rear instruction space” 72, and the “verification instruction” A memory module for storing a test program by describing the memory module 12 so as to store “verification instruction” in “address” and “verification instruction address” in the branch destination address when the previous instruction is a branch instruction 12 are generated. Then, the logic verification scenario generation device acquires, for each instruction of the test program, a corresponding expected value format from the expected value format storage unit 221 based on the instruction decoding information, and corresponds to the output signal of the expected value format. Generate the expected value.

  As a result, the logic verification scenario generation device comprehensively automatically generates the expected value corresponding to each instruction of the memory module 12 that stores the test program and the test program based on the combination of the verification scenario conditions that are sequentially selected. And can reduce the load and mistakes in the generation.

  The output signal of the CPU 10 is also affected by the combination and order of instructions. Therefore, the logic verification scenario generation device according to the present embodiment generates a memory module 12 for storing a test program having a plurality of instructions by comprehensively combining the verification scenario conditions of “verification instruction” and “previous instruction combination”. By doing so, logic verification suitable for the CPU 10 can be realized.

  In addition, the logic verification scenario generation device according to the present exemplary embodiment selects the “verification instruction address” of the memory space storing the “verification instruction” as the verification scenario condition, so that the instruction is stored on the memory space. Can be verified. The logic verification scenario generation device may cause the “verification instruction address” to select the address of the “branch destination instruction space” 73 or the “break space” 76. However, when the address of the “branch destination instruction space” 73 or “break space” 76 is selected as the “verification instruction address”, a branch process including a branch instruction or a break instruction needs to be selected as the previous instruction.

  Further, the example in which “verification instruction address” is selected as the verification scenario condition has been described above, but the logical verification scenario generation apparatus may not include “verification instruction address” in the verification scenario condition. The logic verification scenario generation device may determine a fixed “verification instruction address” in advance, and generate the memory module 12 storing the test program and the expected value based on the “verification instruction” and the “before / after combination”.

[Second Embodiment]
In the second embodiment, in addition to the “verification instruction”, “verification instruction address”, and “before / after instruction combination” described in the first embodiment as verification scenario conditions, The “external input factor” to be input and “external input timing” of the “external input factor” are selected.

  The CPU 10 and the memory module 12 in the present embodiment are the same as those shown in FIGS. However, the logic verification scenario generation device according to the present embodiment further generates the external input signal generation module 11 (FIG. 3) described in RTL based on the verification scenario condition. The external input signal generation module 11 outputs a signal based on the “external input factor” at the “external input timing” of the “verification instruction” executed by the CPU 10 when executing the logic verification simulation.

  FIG. 15 is a diagram showing an external input factor list EX and an external input timing list EXT in the test library 214. The test library 214 includes an external input factor list EX having a plurality of “external input factors” and an external input having a plurality of “external input timings” in addition to the verification command list CM, the verification command address list CM @, and the preceding and following command combination list CML. The timing list EXT is stored in advance by a verifier or the like. Further, in the test library 214 in the figure, each “external input factor” and “external input timing” are associated with an identification symbol such as a number “1 to n”, for example.

  The “external input factor” is an input signal based on factors such as an interrupt, an exception, and a trap. An interrupt is an external hardware interrupt that occurs regardless of the instruction being executed, and an exception is an address exception that occurs due to an error or violation associated with instruction execution. A trap is an interrupt that is intentionally generated during a program. When an “external input factor” such as an interrupt or exception occurs in the instruction during the simulation, the CPU 10 corresponds to the “external input factor” from the “vector table” 78 in the memory space defined by the memory module 12 in FIG. A start address of an “EIT routine space” 77 in which predetermined processing (EIT routine) is stored in advance is acquired, and the EIT routine is executed after branching to the start address.

  The “external input timing” in the present embodiment is a stage for generating “external input factor” in the pipeline processing of the “verification instruction” of the CPU 10, and “verification instruction fetch timing” and “verification instruction decode timing”. “Verification instruction execution timing” or the like.

  The generation processing of the memory module 12 for storing the test program and the external input signal generation module 11 in the present embodiment will be described based on the flowchart of FIG. The verification scenario condition input unit 210 according to the present embodiment receives “external input factor” and “external input timing” as verification scenario conditions from the test library 214 in addition to “verification instruction”, “verification instruction address”, and “previous instruction combination”. Is received (S101).

  The verification scenario condition input unit 210 divides the selected verification scenario condition as a verification scenario condition determination process when the selected verification scenario condition does not correspond to the specification restriction of the CPU 10 to be verified (NO in S102). The “instruction” is passed to the verification instruction selection process S104, the “front and rear instruction combination” is passed to the front and rear instruction selection process S105, the “verification instruction address” is passed to the verification instruction address selection process S106, and the “external input factor” is passed to the external input factor selection process. The “external input timing” is passed to S110 to the external input timing selection process S111 (S103).

  The verification instruction selection process (S104), the preceding and following instruction selection process (S105), and the test program generation process (S107) are the same as those in the first embodiment. However, the program condition determination unit 211 further passes “verification instruction address” to the external input signal parameter generation process S112 as the verification instruction address selection process (S106). Then, the external input signal generation unit 213 identifies “external input factor” based on the identification symbol of “external input factor” as the external input factor selection processing (S110), and identifies “external input timing” as the external input timing selection processing. Based on the symbol, “external input timing” is selected from the test library 214 (S111).

  Subsequently, the external input signal generation unit 213 generates an external input signal parameter based on the “verification instruction address”, “external input factor”, and “external input timing” (S112). The external input signal generation unit 213 describes the generated external input signal parameter in the external input signal generation module 11 (S113).

  FIG. 16 is a diagram illustrating an example of the external input signal generation module 11 whose “external input factor” is an interrupt. The external input signal generation module 11 shown in the figure is described in Verilog HDL. However, the external input signal generation module 11 is not limited to the description in FIG.

  In the description 161 of FIG. 16, the variables “int_addr” and “int_stage” are defined, and the value indicating the “verification instruction address” of the “verification instruction” that generates an interrupt in “int_addr” is “external input timing” in “int_stage”. A value indicating is input. In the description 162 of FIG. 16, the process of generating an interrupt signal when the instruction address of the “int_stage (external input timing)” stage of the CPU 10 is “int_addr (verification instruction address)” during the simulation is executed. It has been described. Accordingly, the external input signal generation module 11 generates an interrupt signal when the “verification instruction address” indicated by “int_addr” is in the “int_stage” stage during the logic verification simulation.

  Specifically, the external input signal generation unit 213 sets the value “verification instruction address” in the variable “int_addr” corresponding to “external input factor” as the external input signal parameter, and “external input timing” in “int_stage”. Is generated (S112). Then, the generated external input signal parameter is described in the module corresponding to the “external input factor” to generate the external input signal generation module 11 (S113).

  As described above, the logic verification scenario generation unit 21 generates the external input signal parameters based on the “external input factor”, “verification instruction address”, and “external input timing”, and describes them in the corresponding module. A generation module 11 is generated. As a result, the external input signal generation module 11 can generate an “external input factor” at the “external input timing” of the “verification instruction” when executing the logic verification simulation.

FIG. 17 is an example of the memory module 12 that stores a test program generated based on the verification scenario condition. In FIG. 6, “verification instruction” “1 (ADD R1, R2)”, “verification instruction address” “1 (0x00000100)”, “preceding instruction combination” “4 ((previous instruction) branch processing B / ( Tests generated based on verification scenario conditions of “post instruction) arithmetic processing A)”, “external input factor” “1 (interrupt signal)”, “external input timing” “3 (verification instruction execution timing)” in FIG. The memory module 12 stores a program. Specifically, the branch process B is the next instruction.
“LDI: 32 (branch destination address), R5”
"JMP @ R5"
The arithmetic processing A is the next instruction.
“LDI: 32 0x00000300, R1”
In the memory module 12 storing the test program of FIG. 17, the branch processing B is in the “previous instruction space” 71, the arithmetic processing A is in the “following instruction space” 72, and the verification instruction “ADD R1, R1” is in the verification instruction address “0x00000100”. R2 ”is described so that the verification instruction address“ 0x00000100 ”is stored in the (branch destination address) 171 of the branch process B. According to the test program of FIG. 6, when executing the logic verification simulation, the CPU 10 first executes the previous instructions “LDI: 32 0x00000100, R5” and “JMP @ R5”. Since “JMP @ R5” is a branch instruction, the CPU 10 branches to the branch destination address “0x00000100” indicated by “@ R5”, and then executes the verification instruction “ADD R1, R2”.

  However, an interrupt signal is input from the external input signal generation module 11 to the verification instruction “ADD R1, R2” at “verification instruction execution timing”. When the interrupt signal is input, the CPU 10 obtains the start address “0x00001000” 172 of the interrupt signal routine in the “EIT routine space” 77 from the “vector table” 78 and the instruction “ADD R3,” stored in advance at the address. R4 "and" RETI "are executed. Since “RETI” is a return instruction from the branch destination, the CPU 10 returns to the branch source and executes the next instruction “LDI: 32 0x00000300, R1”.

  As described above, the logic verification scenario generation unit 21 stores, for each “external input factor” in the memory space, an “EIT routine space” 77 in which an instruction (EIT routine) executed when the “external input factor” occurs is stored. The head address is stored in advance in the “vector table” 78. As a result, the test program generation unit 212 also automatically generates a test program when an “external input factor” occurs in the “external input timing” of the “verification instruction”, as in the first embodiment. can do.

  The expected value generation process will be described based on the flowchart of FIG. The expected value generation unit 22 reads instructions sequentially from the start address of the test program (S121), and performs element decomposition processing of the read instructions (S122).

  As the verification scenario element decomposition process (S122, FIG. 10), the expected value generation unit 22 decodes the instruction to generate decode information, and passes it to the instruction type determination process (FIG. 10). 10 S141). Then, the expected value generation unit 22 extracts the EIT factor of the external input signal based on the external input signal parameter, passes it to the EIT factor determination process (S142 in FIG. 10), and based on the decode information and the presence / absence of the EIT factor. Thus, the presence / absence information of the instruction branch is generated and passed to the branch determination process (S143 in FIG. 10). Since a branch occurs due to an EIT factor, the branch is present when the EIT factor is present. Then, the expected value generation unit 22 delivers the decode information and the address information of the instruction to the data extraction process as in the first embodiment (S144 in FIG. 10).

  Returning to FIG. 9, subsequently, the expected value generation unit 22 sets the format number corresponding to the instruction type as the instruction type determination process (S123) and branches as the branch determination process, as in the first embodiment. In this case, the branch format number is passed to the expected value format selection process (S127) (S125). Then, as the EIT factor determination process, the expected value generation unit 22 selects a format number corresponding to the EIT factor and passes it to the expected value format selection process (S127) (S124).

  The expected value format “9 to 11” in FIG. 12 is an expected value format corresponding to the EIT factor. Expected value formats corresponding to EIT factors include, for example, “(9) Asynchronous EIT”, “(10) Synchronous EIT”, and “(11) Break”, which are selected according to the EIT factor. For example, when the EIT factor is “interrupt”, since “interrupt” is an asynchronous EIT, an expected value format of “(9) Asynchronous EIT” is selected.

  When the interrupt signal is generated, the CPU 10 reads the address of the interrupt routine in the “EIT routine space” 77 from the “vector table” 78 and also returns the return information (program status, address of the next instruction) from the branch caused by the generation of the interrupt signal. Write to the “stack space” 75. For this reason, the expected value format for “(9) Asynchronous EIT” external input factor is “Instruction address”, “Branch information (fixed value)” in the process of reading the storage address of the interrupt routine from “Vector table” 78 on the first line. ) ”,“ Branch factor (fixed value) ”,“ EIT factor ”,“ CPU state ”,“ access address ”,“ RW information (fixed value) ”,“ access size (fixed value) ”,“ read data ” Has an output signal item.

  Then, “(9) Asynchronous EIT” expected value format for external input factor, the second to third lines are “CPU state”, “access address”, “RW information (fixed value)” in the process of writing the return information to the stack space. , “Access size (fixed value)”, and “write data” output signal items.

  Subsequently, in FIG. 11 (S127), the expected value generation unit 22 selects a format based on the format number selected in the instruction type determination process and the format number selected in the EIT factor determination process (S151). Specifically, when there is a format number corresponding to the EIT factor, the expected value generation unit 22 acquires the expected value format of the format number corresponding to the EIT factor instead of the instruction type. Then, when there is a branch (YES in S152), the expected value generation unit 22 adds the expected value format for branching to the expected value format based on the instruction type and EIT factor determination (S153), and determines the expected value format. (S154).

  Returning to FIG. 9, the expected value generation unit 22 generates an expected value corresponding to the output signal item in the expected value format, based on the extracted data based on the data extraction process (S126), as in the first embodiment. (S128, 129).

  A specific example of expected value generation based on the test program of FIG. 17 will be described below. In the test program of FIG. 8, the expected value generation processing for an instruction in which “external input factor” does not occur is the same as that in the first embodiment. Therefore, an expected value generation process of the verification instruction “ADD R1, R2” in which the “external input factor” is generated will be described below.

  The expected value generation unit 22 reads the instruction “ADD R1, R2” (S121), performs verification scenario element decomposition processing (S122), decodes the instruction, and determines that the instruction is “ADD” as an instruction type In addition to the process (S141 in FIG. 10), the EIT factor “interrupt” is extracted based on the “external input factor” and passed to the EIT factor determination process (S142 in FIG. 10). Then, the expected value generation unit 22 passes information indicating that the branch is present to the branch determination process based on the EIT factor “interrupt” although the “ADD” instruction is not branched (S143 in FIG. 10). Further, the expected value generation unit 22 passes the decode information and instruction address information “0x00000100” to the data extraction process (S144 in FIG. 10).

  Subsequently, the expected value generation unit 22 determines that the “ADD” instruction is an arithmetic instruction, sets the format number “1” corresponding to the arithmetic instruction (S123), and based on the EIT factor “interrupt”. Then, the format number “9” of the expected value format “(9) Asynchronous” (S124), and the expected value format “12” for branching is passed to the format selection process based on the branching presence information (S125).

  The expected value generation unit 22 responds to the EIT factor based on the format number “9” corresponding to the EIT factor instead of the format number “1” corresponding to the instruction type based on the flowchart of FIG. The expected value format “9” is selected (S151). If the branch is present (YES in S152), the expected value generation unit 22 selects the expected value formats “9” and “12” from the expected value format storage unit 221 to determine the format (S154). In this way, the expected value format corresponding to the instruction “ADD R1, R2” that generates the interrupt signal is selected.

  FIG. 18 is a diagram showing an expected value format corresponding to each instruction of the test program of FIG. As described above, the expected value formats corresponding to the verification instruction “ADD R1, R2” in which the “external input factor” is generated are “9” and “12” (l-1 to 3, m).

  Next, FIG. 19 is a diagram showing expected values corresponding to the test program of FIG. Hereinafter, a process for generating an expected value for the verification instruction “ADD R1, R2” will be described.

  The expected value generation unit 22 performs, as data extraction processing for the instruction “ADD R1, R2”, based on the decode information, the initial CPU state “state A” due to the fact that the instruction “ADD” is not an instruction for controlling the state of the CPU. The EIT factor “interrupt” and the instruction address “0x00000100” are extracted (S126). Further, the expected value generation unit 22 uses the vector table address “0xFFFF1000”, “read data” as the “access address” in the read processing of the storage address of the interrupt routine from the “vector table” 78 based on the EIT factor “interrupt”. ", The vector table memory information" 0x0001000 "is extracted. Further, the expected value generation unit 22 writes “0x000007F8 / 0x000007FC” as the write address to the stack space for two information as the “access address” in the write processing of the return information to the stack space, and “PS (program) as the“ write data ”. (Status) / next instruction address (0x00000102) ”is extracted.

  As a result, for the expected value format (k, l-1 in FIG. 19) of the instruction “ADD R1, R2” synthesized with the expected value format (k) for branching, “RW information / R” “access size / 4” ”,“ Instruction address / 0x00000100 ”,“ EIT factor / interrupt ”,“ CPU state / state A ”,“ access address / 0xFFFF1000 ”, and“ read data / 0x00001000 ”are generated as expected values. Further, by combining the expected value format (k) for branching, “branch information / branch destination” and “branch factor / instruction branch / asynchronous EIT” are generated as expected values.

  Further, regarding the expected value format (l-2, 3 in FIG. 19) of the instruction “ADD R1, R2”, in addition to the fixed values “RW information / W” and “access size / 4”, “CPU state / state A” “ Access address / 0x000007FC, 0x000007F8 "" Write data / PS, 0x00000102 "are generated as expected values. Further, the expected value format (m) for the branch of the verification instruction “ADD R1, R2” is synthesized into the expected value format (n) corresponding to the next instruction “ADD R3, R4”.

  In this way, when an “external input factor” is generated for an instruction, the expected value generation unit 22 acquires an expected value format having an output signal item corresponding to the “external input factor”. The expected value corresponding to the output signal item is generated based on the EIT factor. In addition, the expected value generation unit 22 further generates an expected value based on the address of the memory space previously classified according to the use based on the EIT factor, and the memory information stored in advance at the address. Accordingly, the expected value generation unit 22 can generate an expected value in which a signal output by the CPU 10 executing each instruction of the test program is predicted even when an “external input factor” occurs.

  In addition, the logic verification scenario generation device according to the present exemplary embodiment selects a logic that specifies the timing at which the “external input factor” is generated in the “verification instruction” by selecting “external input timing” as the verification scenario condition. Verification can be performed. However, the logic verification scenario generation device may not include “external input timing” in the verification scenario condition.

  Further, the logic verification scenario generation device according to the present embodiment may cause the “verification instruction address” to select the address of the “EIT routine space” 77. However, when the address of the “EIT routine space” 77 is selected as the “verification instruction address”, processing (interrupt processing or the like) that causes an external input factor needs to be selected as the previous instruction.

  Furthermore, the expected value format in the present embodiment is prepared for each instruction type that outputs the same output signal item, so that the data capacity of the expected value format storage unit can be suppressed. However, the expected value format may be prepared for each command and each external input signal.

  In the present embodiment, the output signal items as illustrated in FIG. 12 are illustrated. However, the output signal items differ depending on the CPU 10 and are not limited to the example in FIG. The output signal item in the present embodiment is an item output when the instruction cycle of the CPU 10 is completed. However, the output signal item may be, for example, an item acquired every clock cycle of the CPU 10 or an item acquired in a specific cycle in which acquisition is effective.

  The above embodiment is summarized as follows.

(Appendix 1)
A logic verification scenario generation device for generating a test program for CPU logic verification described in RTL,
A test library for storing a verification instruction list having a plurality of verification instructions, a front instruction executed before the verification instruction, and a front and rear instruction combination list having a plurality of front and rear instruction combinations of subsequent instructions executed after the verification instruction;
An expected value format storage unit that stores an expected value format having one or a plurality of output signal items that the CPU executes and outputs the instructions;
A verification instruction address for storing the verification instruction, a previous instruction space for storing the previous instruction, a subsequent instruction space for storing the subsequent instruction, and a data space to be accessed when the instruction is a data access instruction A memory module having a branch instruction space for storing a branch destination instruction when the instruction is a branch instruction, and a stack space for storing return information when the instruction is a return instruction after branching, Based on the verification instruction sequentially selected from the test library and the combination of the preceding and following instructions, the verification instruction is stored in the verification instruction address, the previous instruction is stored in the previous instruction space, and the subsequent instruction is stored in the subsequent instruction space. In addition, when the previous instruction is the branch instruction, a memory module storing the verification instruction address in the branch destination address of the previous instruction is stored in the test module. And test program generation unit for generating as a program,
For each instruction of the generated test program, the expected value format corresponding to the instruction is acquired from the expected value format storage unit, and an expected value corresponding to the output signal item is obtained based on decoding information obtained by decoding the instruction. An expected value generator to generate;
A logic verification scenario generation device characterized by comprising:

(Appendix 2)
In Appendix 1,
The test library further stores a verification instruction address list having a plurality of verification instruction addresses,
The test program generation unit further selects the verification instruction address sequentially from the test library.

(Appendix 3)
In Appendix 1 or 2,
The test library further stores an external input signal list having a plurality of external input signals to be generated for the verification instruction,
The test program generation unit further includes an external input command space for storing an external input command corresponding to each external input signal in the external input signal list, and the external input of each external input signal in the external input command space Generating the memory module having a vector table for storing an instruction address as a test program;
The logic verification scenario generation device further includes:
An external input signal generation unit that generates an external input signal generation module that generates the external input signal in response to the verification instruction based on the external input signal sequentially selected from the test library and the verification instruction address. And
The expected value generation unit selects the expected value format corresponding to the external input signal for the verification instruction, and generates the expected value based on the external input signal. .

(Appendix 4)
In Appendix 3,
The test library further stores a generation timing list having a plurality of generation timings for generating the external input signal,
The external input signal generation unit further generates the external input signal generation module based on the generation timing sequentially selected from the test library.

(Appendix 5)
In any one of supplementary notes 1 to 4,
The expected value generated by the expected value generation unit is further one or both of address information of the memory module based on the decode information and memory information stored in the address information. Logic verification scenario generator.

(Appendix 6)
In Appendix 3 or 4,
The expected value generated by the expected value generating unit is further one or both of address information of the memory module based on the external input signal and memory information stored in the address information. A logic verification scenario generation device.

(Appendix 7)
In any one of supplementary notes 1 to 6,
In the case where the instruction is a branch instruction, the expected value generation unit, in addition to the expected value format corresponding to the instruction, adds a branch destination expected value format having the output signal item indicating a branch destination to the expected value format storage unit. And generating the combined expected value format by combining the branch destination expected value format with the expected value format of the next instruction, and regarding the next instruction, the expected value corresponding to the output signal item of the combined expected value format A logic verification scenario generation device characterized by generating.

(Appendix 8)
In any one of appendices 1 to 7,
The logic verification scenario generation device according to claim 1, wherein the pre-instruction and the post-instruction stored in the test library include one or a plurality of the instructions.

(Appendix 9)
In any one of appendices 1 to 8,
The logic verification scenario generation device, wherein the expected value formats corresponding to the same type of instruction or the external input signal are the same.

(Appendix 10)
In Appendix 9,
The output signal item of the expected value has a fixed value in which an expected value is predicted in advance based on the type, and a non-fixed value in which an expected value is generated based on the decoding information or the external input signal. And
The expected value generation unit generates an expected value corresponding to the output signal item of the non-fixed value.

(Appendix 11)
In Appendix 1,
A logic verification scenario generation device, wherein the memory module is described in RTL.

(Appendix 12)
In Appendix 3,
A logic verification scenario generation device, wherein the external input signal generation module is described in RTL.

(Appendix 13)
In a computer-readable logic verification scenario generation program for causing a computer to execute a logic verification scenario generation process for generating a test program for logic verification of a CPU described in RTL,
The logic verification scenario generation process includes:
A test library for storing a verification instruction list having a plurality of verification instructions, a front instruction executed before the verification instruction, and a front and rear instruction combination list having a plurality of front and rear instruction combinations of subsequent instructions executed after the verification instruction;
An expected value format storage unit that stores an expected value format having one or a plurality of output signal items that the CPU executes and outputs the instructions;
A verification instruction address for storing the verification instruction, a previous instruction space for storing the previous instruction, a subsequent instruction space for storing the subsequent instruction, and a data space to be accessed when the instruction is a data access instruction A memory module having a branch instruction space for storing a branch destination instruction when the instruction is a branch instruction, and a stack space for storing return information when the instruction is a return instruction after branching, Based on the verification instruction sequentially selected from the test library and the combination of the preceding and following instructions, the verification instruction is stored in the verification instruction address, the previous instruction is stored in the previous instruction space, and the subsequent instruction is stored in the subsequent instruction space. In addition, when the previous instruction is the branch instruction, a memory module storing the verification instruction address in the branch destination address of the previous instruction is stored in the test module. And test program generation step of generating as a program,
For each instruction of the generated test program, the expected value format corresponding to the instruction is acquired from the expected value format storage unit, and an expected value corresponding to the output signal item is obtained based on decoding information obtained by decoding the instruction. An expected value generation process to generate;
A logic verification scenario generation program characterized by comprising:

10: CPU (RTL), 11: External input signal generation module (RTL), 12: Memory module (RTL), 13: Output signal trace module (RTL),
21: Logic verification scenario generation unit, 210: Verification scenario condition input unit, 211: Program condition determination unit, 212: Test program generation unit, 213: External input signal generation unit, 214: Test library,
22: Expected value generation unit, 2211: Expected value format storage unit

Claims (5)

A logic verification scenario generation device for generating a test program for CPU logic verification described in RTL,
A test library for storing a verification instruction list having a plurality of verification instructions, a front instruction executed before the verification instruction, and a front and rear instruction combination list having a plurality of front and rear instruction combinations of subsequent instructions executed after the verification instruction;
An expected value format storage unit that stores an expected value format having one or a plurality of output signal items that the CPU executes and outputs the instructions;
A verification instruction address for storing the verification instruction, a previous instruction space for storing the previous instruction, a subsequent instruction space for storing the subsequent instruction, and a data space to be accessed when the instruction is a data access instruction A memory module having a branch instruction space for storing a branch destination instruction when the instruction is a branch instruction, and a stack space for storing return information when the instruction is a return instruction after branching, Based on the verification instruction sequentially selected from the test library and the combination of the preceding and following instructions, the verification instruction is stored in the verification instruction address, the previous instruction is stored in the previous instruction space, and the subsequent instruction is stored in the subsequent instruction space. In addition, when the previous instruction is the branch instruction, a memory module storing the verification instruction address in the branch destination address of the previous instruction is stored in the test module. And test program generation unit for generating as a program,
For each instruction of the generated test program, the expected value format corresponding to the instruction is acquired from the expected value format storage unit, and an expected value corresponding to the output signal item is obtained based on decoding information obtained by decoding the instruction. An expected value generator to generate;
A logic verification scenario generation device characterized by comprising: In claim 1,
The test library further stores a verification instruction address list having a plurality of verification instruction addresses,
The test program generation unit further selects the verification instruction address sequentially from the test library. In claim 1 or 2,
The test library further stores an external input signal list having a plurality of external input signals to be generated for the verification instruction,
The test program generation unit further includes an external input command space for storing an external input command corresponding to each external input signal in the external input signal list, and the external input of each external input signal in the external input command space Generating the memory module having a vector table for storing an instruction address as a test program;
The logic verification scenario generation device further includes:
An external input signal generation unit that generates an external input signal generation module that generates the external input signal in response to the verification instruction based on the external input signal sequentially selected from the test library and the verification instruction address. And
The expected value generation unit selects the expected value format corresponding to the external input signal for the verification instruction, and generates the expected value based on the external input signal. . In claim 3,
The test library further stores a generation timing list having a plurality of generation timings for generating the external input signal,
The external input signal generation unit further generates the external input signal generation module based on the generation timing sequentially selected from the test library. In a computer-readable logic verification scenario generation program for causing a computer to execute a logic verification scenario generation process for generating a test program for logic verification of a CPU described in RTL,
The logic verification scenario generation process includes:
A test library for storing a verification instruction list having a plurality of verification instructions, a front instruction executed before the verification instruction, and a front and rear instruction combination list having a plurality of front and rear instruction combinations of subsequent instructions executed after the verification instruction;
An expected value format storage unit that stores an expected value format having one or a plurality of output signal items that the CPU executes and outputs the instructions;
A verification instruction address for storing the verification instruction, a previous instruction space for storing the previous instruction, a subsequent instruction space for storing the subsequent instruction, and a data space to be accessed when the instruction is a data access instruction A memory module having a branch instruction space for storing a branch destination instruction when the instruction is a branch instruction, and a stack space for storing return information when the instruction is a return instruction after branching, Based on the verification instruction sequentially selected from the test library and the combination of the preceding and following instructions, the verification instruction is stored in the verification instruction address, the previous instruction is stored in the previous instruction space, and the subsequent instruction is stored in the subsequent instruction space. In addition, when the previous instruction is the branch instruction, a memory module storing the verification instruction address in the branch destination address of the previous instruction is stored in the test module. And test program generation step of generating as a program,
For each instruction of the generated test program, the expected value format corresponding to the instruction is acquired from the expected value format storage unit, and an expected value corresponding to the output signal item is obtained based on decoding information obtained by decoding the instruction. An expected value generation process to generate;
A logic verification scenario generation program characterized by comprising:

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