JP6473023B2 - Performance evaluation module and semiconductor integrated circuit incorporating the same - Google Patents

Description

  The present invention relates to a performance evaluation module and a semiconductor integrated circuit, and more particularly to a performance evaluation module for evaluating a processing time of a processor and a semiconductor integrated circuit incorporating the performance evaluation module.

  In a semiconductor integrated circuit including a processor and a peripheral circuit such as a memory, the processor sequentially reads program codes (instructions) from the memory and executes processing according to the instructions. In general, in order to improve the processing speed performance of a processor, a pipeline system is adopted in which individual instructions are divided into a plurality of stages and the divided stages are executed in parallel.

  In order to further increase the performance of the processor, it is necessary to optimize the program according to the hardware. The program is optimized by, for example, simulating program execution and analyzing how long each instruction takes.

  For example, the following Patent Document 1 discloses a program analysis support apparatus that enables a user to know a part that is a bottleneck for program execution in a parallel computer. This program analysis support device collects and manages event trace data while assigning an identifier to each event of a program executed on a parallel computer, and edits the relationship between events in a visually easy-to-read manner. Show on the display.

JP-A-6-083608

  However, the program analysis support apparatus disclosed in Patent Document 1 as described above analyzes a program based on an event based on a certain interval that accompanies the execution of the program. The instruction could not be analyzed on a clock cycle basis. Depending on the program structure and instruction type, the execution cycle of one instruction may affect the execution cycle of other instructions, resulting in a decrease in the overall processing speed of the program. However, there is a problem that sufficient analysis accuracy for improving performance cannot be obtained.

  Therefore, an object of the present invention is to make it possible to analyze the execution progress of a program executed by a processor on the basis of a clock cycle of an instruction having a smaller granularity than an event base.

  More specifically, an object of the present invention is to provide a performance evaluation module capable of counting the number of executions of individual instructions for a program executed in a pipeline manner by a processor.

  Further, the present invention provides a performance evaluation module capable of correctly counting the number of executions of individual instructions even when a control hazard occurs due to execution of a branch instruction for such a program. For the purpose.

  Furthermore, the present invention provides a performance evaluation module capable of correctly counting the number of executions of individual instructions even when a data hazard caused by a memory access instruction occurs in such a program. Objective.

  Still another object of the present invention is to provide a performance evaluation module as described above having a configuration that can be easily incorporated into a semiconductor integrated circuit including a processor.

  The present invention for solving the above problems includes the following technical features or invention specific matters.

  That is, the present invention according to a certain aspect is a performance evaluation module that evaluates the processing performance of a processor module that executes an instruction group of a program by pipeline processing according to a predetermined operation clock, and includes at least one instruction of the instruction group The program counter table for storing the execution address value for the processor, the value of the program counter sent from the processor module in accordance with the instruction processing by the processor module, and the value of the execution address stored in the program counter table And, when it is determined by the program counter comparison unit and the program counter comparison unit that determines whether or not they match, the number of instructions executed corresponding to the value of the program counter that has been compared and determined is counted, Count to output A control unit, a performance evaluation module comprising a.

  Thereby, the performance evaluation module determines whether or not the value of the program counter sent from the processor module matches the value of the execution address stored in the program counter table, and performs counting according to the result of the determination. The performance evaluation module can count the number of executions of individual instructions corresponding to a predetermined execution address among the instructions executed by the processor module.

  Here, the count control unit includes a plurality of sequential circuits connected in stages, and sequentially latches the value of the program counter for a predetermined clock cycle of the predetermined operation clock by the plurality of sequential circuits, The number of executions of the instruction may be counted.

  As a result, the performance evaluation module can latch the value of the program counter for a predetermined clock cycle by a plurality of sequential circuits connected in stages.

  Further, the predetermined clock cycle may be the number of clock cycles required to execute the one instruction after the processor module fetches the one instruction.

  As a result, the performance evaluation module can latch the value of the program counter for one instruction until the processor module fetches one instruction and then executes the one instruction.

  The count control unit is configured to latch the predetermined clock cycle when the instruction executed by the processor module is a branch instruction and a branch condition of the branch instruction is satisfied. The output of one sequential circuit that holds the value of the program counter may be input to each of the plurality of sequential circuits.

  Thus, the performance evaluation module updates the content latched by the sequential circuit to the output of the one sequential circuit when the one instruction is a branch instruction and the branch condition of the branch instruction is satisfied. As a result, the number of executions of individual instructions can be correctly counted against a hazard caused by a branch instruction.

  Further, the count control unit may input the value of the program / counter that has been compared and determined to the sequential circuit in the forefront stage when the branch condition of the predetermined branch instruction is not satisfied.

  In addition, the count control unit stores a value read from the predetermined memory module after the execution of the calculation, in which one instruction calculated and executed by the processor module is a read command for the predetermined memory module. If the value of the address indicating the area to be executed matches the value of the address indicating the area storing the value according to the other instruction before the execution of the operation of the other instruction, until the execution of the operation of the one instruction A selection unit that sends the latched value of the program counter to the program counter comparison unit may be further included.

  Thus, the performance evaluation module sends the value of the program counter for the one instruction to the program counter comparison unit when the one instruction is a read instruction for the memory module and the condition for generating the hazard is satisfied. The number of executions of individual instructions can be counted correctly even in the case of a hazard generated by a read instruction.

  The performance evaluation module may count the number of executions for each identifier assigned to one or more of the instructions.

  As a result, the performance evaluation module can count the number of executed instructions for each instruction corresponding to the identifier.

  Further, according to another aspect of the present invention, there is provided a processor module that executes an instruction group of a program by pipeline processing according to a predetermined operation clock, at least one performance evaluation module connected to the processor module, and the instruction group. A program counter table for storing an execution address value for at least one instruction of the program, wherein the at least one performance evaluation module includes a value of the program counter associated with the processing of the instruction by the processor module and the program counter table. A program counter comparison unit that compares the execution address value stored in the program counter and determines whether or not they match, and a counter control unit that counts the number of executions of instructions corresponding to the value of the program counter. The program counter The comparison unit determines whether or not they match based on the value of the program counter sent from the processor module when an instruction is fetched by the processor module, and the count control unit compares the program counter comparison In the semiconductor integrated circuit, the number of instructions executed corresponding to the value of the program counter that has been compared and determined is counted and output when it is determined that they match.

  Thereby, the semiconductor integrated circuit determines whether or not the value of the program counter sent from the processor module matches the value of the execution address stored in the program counter table, and performs counting according to the result of the determination. The performance evaluation module can count the number of executions of individual instructions corresponding to a predetermined execution address among the instructions executed by the processor module.

  Here, the semiconductor integrated circuit may include a plurality of the performance evaluation modules for counting the number of executions for each identifier assigned to one or more of the instructions.

  As a result, the semiconductor integrated circuit can count the number of executed instructions for each instruction corresponding to the identifier.

  Furthermore, the present invention according to another aspect is a performance evaluation method for evaluating the processing performance of a processor module that executes a group of instructions of a program by pipeline processing according to a predetermined operation clock, and the processing of instructions by the processor module Receiving a value of a program counter sent from the processor module, receiving an execution address value for at least one instruction of the instruction group stored in the program counter table, and a value of the program counter The execution address value is compared to determine whether they match, and when it is determined that the value of the program counter matches the value of the execution address, Count the number of executions of the instruction corresponding to the value. Including the door, it is the performance evaluation method.

  Thereby, the performance evaluation module determines whether or not the value of the program counter sent from the processor module matches the value of the execution address stored in the program counter table, and performs counting according to the result of the determination. The performance evaluation module can count the number of executions of individual instructions corresponding to a predetermined execution address among the instructions executed by the processor module.

  According to the present invention, the performance evaluation module can analyze the execution of a program executed on the processor on the basis of the clock cycle of the instruction having a smaller granularity than the event base.

  That is, according to the present invention, the performance evaluation module can count the number of executions of individual instructions for a program executed on the processor.

  In addition, according to the present invention, the performance evaluation module can execute the number of individual instructions for a program executed by a processor in a pipeline manner even when a control hazard occurs due to execution of a branch instruction. Can be counted correctly.

  Further, according to the present invention, the performance evaluation module correctly sets the execution number of each instruction even when a data hazard caused by a memory access instruction occurs in a program executed by a processor in a pipeline manner. Will be able to count.

  In addition, according to the present invention, the performance evaluation module can have a configuration that can be easily incorporated into a semiconductor integrated circuit including a processor while realizing the above-described effects.

  Other technical features, objects, effects, and advantages of the present invention will become apparent from the following embodiments described with reference to the accompanying drawings.

It is a figure which shows an example of schematic structure of the semiconductor integrated circuit which concerns on one Embodiment of this invention. It is a figure which shows an example of a structure of the processor module of the semiconductor integrated circuit which concerns on one Embodiment of this invention. It is a figure which shows an example of a structure of each component in the processor module which concerns on one Embodiment of this invention. It is a figure which shows an example of a structure of each component in the processor module which concerns on one Embodiment of this invention. It is a figure which shows an example of a structure of the performance evaluation module which concerns on one Embodiment of this invention. It is a flowchart which shows an example of operation | movement of the performance evaluation module which concerns on one Embodiment of this invention. It is a flowchart which shows an example of operation | movement of the performance evaluation module which concerns on one Embodiment of this invention. It is a conceptual diagram for demonstrating the count operation | movement of the performance evaluation module in the pipeline process by the processor module of the semiconductor integrated circuit which concerns on one Embodiment of this invention. It is a conceptual diagram for demonstrating the count operation | movement of the performance evaluation module in the pipeline process by the processor module of the semiconductor integrated circuit which concerns on one Embodiment of this invention. It is a conceptual diagram for demonstrating the count operation | movement of the performance evaluation module in the pipeline process by the processor module of the semiconductor integrated circuit which concerns on one Embodiment of this invention. It is a figure which shows the other example of schematic structure of the semiconductor integrated circuit which concerns on one Embodiment of this invention.

  Next, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a diagram showing an example of a schematic configuration of a semiconductor integrated circuit according to an embodiment of the present invention. As shown in the figure, the semiconductor integrated circuit 1 according to the present embodiment includes, for example, a processor module 10, a memory module 20, a chip set 30, and a performance evaluation module 40. The semiconductor integrated circuit 1 typically connects a storage device 50, an input / output device 60, and the like via a predetermined I / O interface (not shown) to constitute a computer system. The semiconductor integrated circuit 1 may be configured only by the performance evaluation module 40 and may operate integrally with another semiconductor integrated circuit configured by a processor module or the like.

  The processor module 10 includes, for example, a processor core, a microcontroller, a digital signal processor, and / or combinations thereof. The processor module 10 of this embodiment is configured to be able to execute instructions in a pipeline manner. Accordingly, the processor module 10 causes the computer system to realize a predetermined function by performing pipeline processing on a group of instructions constituting the program stored in the memory module 20. In the present embodiment, the processor module 10 outputs the value of the program counter to the performance evaluation module 40 during execution of the program.

The memory module 20 is typically a primary storage device composed of volatile memory (for example, RAM), nonvolatile memory (for example, ROM, flash memory, etc.), and / or a combination thereof. In this example, the memory module 20 stores a program used for performance evaluation, various programs necessary for the execution, and the like.
Further, the memory module 20 stores the count value output from the performance evaluation module 40.

  The chipset 30 includes a bridge with a bus connecting the processor module 10, the memory module 20, the performance evaluation module 40, the storage device 50 and the input / output device 60, and other components necessary for configuring a computing device. Consists of integrated circuits.

  The performance evaluation module 40 counts how many cycles a predetermined instruction in the program executed by the processor module 10 has been executed (that is, the number of instructions executed). Specifically, the performance evaluation module 40 determines that the value of the program counter (PC) sequentially output from the processor module 10 in accordance with the execution of the program is a predetermined value stored in the PC table (see FIG. 2). It is determined whether or not they match, and counts each time they match. The count result is stored in, for example, the memory module 20 or the storage device 50 via the chipset 30 and is used for program analysis.

  The storage device 50 typically comprises a hard disk drive (HDD), an optical disk drive, a solid state device (SSD), or the like. The storage device 50 functions as a secondary storage device of the processor module 10. The input / output device 60 is various peripheral interfaces such as a keyboard, a mouse, a display, a printing device, and a communication device.

  In the semiconductor integrated circuit 1 configured as described above, the processor module 10 executes instructions in the program stored in the memory module 20, and during the execution, the performance evaluation module 40 determines what predetermined instructions are. It counts whether it was executed for the number of cycles, and stores the count value in the memory module 20 or the like. As a result, the semiconductor integrated circuit 1 can count the number of instructions executed on the basis of the clock cycle of instructions having a smaller granularity than the event base, so that the program developer can analyze the execution progress. become.

  FIG. 2 is a diagram illustrating an example of a configuration of a processor module of a semiconductor integrated circuit according to an embodiment of the present invention. As shown in the figure, the processor module 10 according to the present embodiment includes, for example, an instruction fetch unit 11, a register read unit 12, an execution unit 13, a memory access unit 14, and a write back unit 15. Composed. In the present embodiment, the processor module 10 is configured to process instructions by these five components in five stages of pipeline processing, but is not limited to this.

  The instruction fetch unit 11 fetches and outputs an instruction from the instruction cache (see FIG. 3) according to the execution address stored in the program counter (see FIG. 3). Accordingly, the value of the program counter is updated according to a control signal CNT output from the execution unit 13 described later. The instruction fetch unit 11 generates read register signals RREG1 and RREG2 indicating a read register address for the register read unit 12, a write register signal WREG indicating a write register address, and a control signal CNT indicating a control content according to the instruction. A program counter signal PC indicating the value of the program counter is output to the register read unit 12. Further, the instruction fetch unit 11 outputs a program counter signal PC to the performance evaluation module 40.

  The register read unit 12 has a register file (see FIG. 3) that stores various values to be used for program execution, and executes reading to the register file in accordance with the instruction fetched by the instruction fetch unit 11. At the same time, writing to the register file is executed in accordance with a signal output from a write back unit 15 described later. Specifically, the register read unit 12 latches the program counter signal PC output from the instruction fetch unit 11, the control signal CNT, the read register signals RREG1 and RREG2, and the write register signal WREG, and the read register signal RREG1 and RREG2 are output to the performance evaluation module 40. The register read unit 12 outputs the program counter signal PC, the control signal CNT, and the write register signal WREG to the execution unit 13. The register read unit 12 reads a value from the address of the register file according to the latched read register signals RREG1 and RREG2, and outputs the read values to the execution unit 13 as read data signals RDATA1 and RDATA2. Further, the register read unit 12 writes the value indicated by the write data signal WDATA output from the write back unit 15 to the address of the register file according to the write back register signal WBREG output from the write back unit 15 described later.

  The execution unit 13 interprets the instruction fetched by the instruction fetch unit 11 using various values read by the register read unit 12, and executes an operation according to the interpretation. Specifically, the execution unit 13 latches the program counter signal PC output from the register read unit 12, the write register signal WREG, the read data signals RDATA1 and RDATA2, and the control signal CNT, and latches the program counter. The signal PC is output to the performance evaluation module 40 as a program counter signal PC2. In addition, the execution unit 13 outputs the latched control signal CNT to the performance evaluation module 40, the instruction fetch unit 11, and the memory access unit 14. The execution unit 13 outputs the latched write register signal WREG to the memory access unit 14 and the performance evaluation module 40, and outputs the latched read data signal RDATA2 to the memory access unit 14 as the write signal WRITE. Furthermore, the execution unit 13 uses the values of the read data signals RDATA1 and RDATA2 output from the register read unit 12 to execute an operation according to the latched control signal CNT. Furthermore, the execution unit 13 outputs the result of the calculation to the memory access unit 14 and the performance evaluation module 40 as a result signal RESULT.

  The memory access unit 14 has a data cache (see FIG. 4) that serves as a primary cache for the memory module 20, and is read by the register read unit 12 according to the instruction fetched by the instruction fetch unit 11. The value of is used to write to and / or read from the data cache. Specifically, the memory access unit 14 latches the control signal CNT, the result signal RESLUT, and the write register WREG output from the execution unit 13, and outputs the latched three signals to the write back unit 15. . In accordance with the latched control signal CNT, the memory access unit 14 writes the value indicated by the latched write signal WRITE to the address of the data cache indicated by the latched result signal RESULT or starts from the address of the data cache indicated by the result signal RESULT. The value is read, and the read value is output to the write back unit 15 as a read signal READ. In addition, the memory access unit 14 transmits the contents of the data cache to the memory module 20 and updates the memory module 20.

  The write-back unit 15 stores the execution result of the instruction fetched by the instruction fetch unit 11 (that is, the result of operation execution by the execution unit 13 and the value read by the memory access unit 14) in the register file of the register read unit 12. Write to. Specifically, the write back unit 15 latches the write register signal WREG output from the memory access unit 14 and outputs the latched signal to the register read unit 12 as the write back register signal WBREG. The write back unit 15 selects either the result signal RESULT or the read signal READ according to the control signal CNT output from the memory access unit 14, and outputs the selection result to the register read unit 12 as the write data signal WDATA. To do.

  In the processor module 10 configured as described above, the instruction fetch unit 11 fetches an instruction according to the execution address of the program output from the memory module 20, and then the register read unit 12 executes the instruction from the register file. The necessary value is read out and passed to the execution unit 13, and the execution unit 13 executes an operation according to the instruction. Further, according to the instruction fetched by the instruction fetch unit 11, the memory access unit 14 executes writing or reading with respect to the data cache. Further, the write back unit 15 writes the calculation result by the execution unit 13 or the data cache read result by the memory access unit 14 in the register file of the register read unit 12. In this way, the processor module 10 can execute the program output from the memory module 20.

  FIG. 3 is a diagram showing an example of the configuration of each component in the processor module surrounded by the line III-III shown in FIG. 2. Specifically, the instruction fetch unit 11 and the register read unit in the processor module 10 are shown. 12 shows the details of the configuration of the execution unit 13 and the execution unit 13. As shown in the figure, the instruction fetch unit 11 includes a program counter 111 and an instruction cache 112.

  The program counter 111 holds the value of the execution address of the instruction, and outputs the value of the held execution address based on a predetermined clock. The execution address value of the program counter 111 is simply updated according to the control signal CNT when the control signal CNT output from the execution unit 13 indicates the execution address value, and when the control signal CNT does not indicate the execution address value. Count up. The program counter 111 outputs the value of the execution address as the program counter signal PC to the instruction cache 112 and the register read unit 12.

  The instruction cache 112 has a role of a primary cache for the memory module 20 and stores an instruction of a program executed by the processor module 10 output from the memory module 20 and an execution address corresponding to the instruction. The instruction cache 112 reads an instruction according to the signal based on the program counter signal PC output from the program counter 111, a write register signal WREG according to the read instruction, read register signals RREG1 and RREG2, and a control signal. CNT is generated, and the generated signal is output to the register read unit 12. The write register signal WREG indicates the address of the register file that stores the execution result of the instruction, the read register signals RREG1 and RREG2 indicate the value of the register file from which the value is read when the instruction is executed, and the control signal CNT indicates the content of the instruction Show.

  The register read unit 12 includes a plurality of registers 121 (in this example, registers 121 (1) to 121 (5)) and a register file 122. Each of the registers 121 (1) to 121 (5) latches the write register signal WREG output from the instruction fetch unit 11, the read register signals RREG1 and RREG2, the control signal CNT, and the program counter signal PC. The registers 121 (2) and 121 (3) output the latched read register signals RREG1 and RREG2 to the register file 122 and the performance evaluation module 40, respectively.

  As described above, the register file 122 stores various values used for execution by the execution unit 13. The register file 122 reads values from the addresses indicated by the read register signals RREG1 and RREG2 output from the registers 121 (2) and 121 (3), and uses the read values as read data signals RDATA1 and RDATA2 to the execution unit 13, respectively. Output. In addition, the register file 122 writes a value indicated by the write data signal WDATA output from the write back unit 15 at an address according to the write back register signal WBREG output from the write back unit 15.

  The execution unit 13 includes registers 131 (1) to 131 (5) and a calculation unit 132. Each of the registers 131 (1) to 131 (5) latches the write register signal WREG output from the register read unit 12, the read data signals RDATA1 and RDATA2, the control signal CNT, and the program counter PC. The registers 131 (2) to 131 (4) output the latched read data signals RDATA1 and RDATA2 and the control signal CNT to the arithmetic unit 132. The register 131 (3) outputs the latched read data signal RDATA2 to the memory access unit 14 as the write signal WRITE. Further, the register 131 (4) outputs the latched control signal CNT to the instruction fetch unit 11, the performance evaluation module 40, and the memory access unit 14.

  The arithmetic unit 132 is, for example, an ALU (Arithmetic Logic Unit), interprets an instruction, and performs arithmetic processing according to the interpretation. The arithmetic unit 132 uses the values indicated by the read data signals RDATA1 and RDATA2 output from the registers 131 (2) and 131 (3) to execute an operation according to the instruction indicated by the control signal CNT output from the register 131 (4). To do. The calculation unit 132 outputs the signal as a result signal RESULT to the performance evaluation module 40 and the memory access unit 14.

  FIG. 4 is a diagram illustrating an example of the configuration of each component of the processor module surrounded by the IV-IV line illustrated in FIG. 2. Specifically, the memory access unit 14 and the write back unit in the processor module 10 are illustrated. 15 shows details of the configuration. As shown in the figure, the memory access unit 14 according to the present embodiment includes, for example, registers 141 (1) to 141 (4) and a data cache 142.

  Each of the registers 141 (1) to 141 (4) latches the write register signal WREG, the result signal RESULT, the write signal WRITE, and the control signal CNT output from the execution unit 13. The registers 141 (2) and 141 (3) output the latched result signal RESULT and the write signal WRITE to the data cache 142. The registers 141 (1), 141 (2), and 141 (4) output the latched write register signal WREG, result signal RESULT, and control signal CNT to the write back unit 15, respectively.

  As described above, the data cache 142 serves as a primary cache for the memory module 20. When a data write or read command is issued to the memory module 20, the data cache 142 replaces the memory module 20 and stores data. It is used for writing or reading. When the control signal CNT output from the register 141 (4) indicates a read process with respect to the memory module 20, the data cache 142 reads a value from an address according to the result signal RESULT output from the register 141 (2), and performs the read The read data is output to the write back unit 15 as a read signal READ. In addition, when the control signal CNT output from the register 141 (4) indicates a process of writing to the memory module 20, the data cache 142 registers the register 141 at the address indicated by the result signal RESULT output from the register 141 (2). The value indicated by the write signal WRITE output from (3) is written. Further, the data cache 142 transmits the stored contents as the memory signal MEM to the memory module 20 according to a predetermined algorithm.

  The write back unit 15 includes, for example, registers 151 (1) to 151 (4) and a selection circuit 152. Each of the registers 151 (1) to 151 (4) latches the write register signal WREG output from the memory access unit 14, the result signal RESULT, the read signal READ, and the control signal CNT. In addition, the register 151 (1) outputs the latched write register signal WREG to the register read unit 12 as the write back register signal WBREG. Further, the registers 151 (2) and 151 (3) output the latched result signal RESULT and the read signal READ to the selection circuit 152.

  The selection circuit 152 is, for example, a multiplexer, but is not limited thereto, and may be a data selector, a signal switch, or the like. The selection circuit 152 selects either the result signal RESULT output from the register 151 (2) or the read signal READ output from the register 151 (3) in accordance with the control signal CNT output from the register 151 (4). Then, the selection result is output as a write data signal WDATA. Specifically, when the control signal CNT indicates a process of writing and reading data with respect to the memory module 20, the read signal READ is selected while the control signal CNT performs a process other than writing and reading of data with respect to the memory module 20. In the case shown, the result signal RESULT is selected, and the result of the selection is output to the register read unit 12 as the write data signal WDATA.

  FIG. 5 is a diagram showing an example of the configuration of a performance evaluation module according to an embodiment of the present invention. The performance evaluation module 40 according to the present embodiment includes, for example, a program counter selection unit (hereinafter referred to as “PC selection unit”) 21, a program counter comparison unit (hereinafter referred to as “PC comparison unit”) 22, and a count control unit. 23 and a program counter table (hereinafter referred to as “PC table”) 24.

  The PC selection unit 21 is a program counter signal PC output from the instruction fetch unit 11 of the processor module 10 or a program counter signal output from the execution unit 13 of the processor module 10 in accordance with various signals output from the processor module 10. One of the PCs 2 is selected, and the selection result is output to the PC comparison unit 22. The PC selection unit 21 includes, for example, comparators 211 (1) and 211 (2), an OR circuit 212, a signal determination unit 213, an AND circuit 214, and a selection circuit 215.

  The comparator 211 compares two input signals and outputs the comparison result to the OR circuit 212. Specifically, the comparator 211 (1) compares the read register signal RREG1 output from the register read unit 12 of the processor module 10 with the write register signal WREG output from the execution unit 13 of the processor module 10, When the values indicated by the two signals match, for example, “1” is output, and when the values indicated by the two signals do not match, for example, “0” is output. The comparator 211 (2) compares the read register signal RREG2 output from the register read unit 12 of the processor module 10 with the write register signal WREG output from the execution unit 13 of the processor module 10, and compares the comparison result. Is output to the OR circuit 212.

  The logical sum circuit 212 performs a logical sum on the comparison results of the comparators 211 (1) and 211 (2), and outputs the logical sum result to the logical product circuit 214.

  The signal determination unit 213 determines whether or not the content of the command indicated by the control signal CNT output from the execution unit 13 of the processor module 10 is read from the memory module 20. When the signal determination unit 213 determines that the content of the command indicated by the control signal CNT is read from the memory module 20, the signal determination unit 213 outputs a signal indicating the state of “1” to the AND circuit 214, while the control signal CNT is When it is determined that the content of the command to be indicated is not read from the memory module 20, a signal indicating a state of “0” is output to the AND circuit 214.

  The logical product circuit 214 performs a logical product on the result of the determination output from the signal determination unit 213 and the result of the logical sum output from the logical sum circuit 212, and selects the result of the logical product by the selection circuit 215. Output to terminal SL.

  The selection circuit 215 is a multiplexer, for example, but is not limited thereto, and may be a data selector or a signal switch. The selection circuit 215 receives the program counter signal PC output from the instruction fetch unit 11 of the processor module 10 or the program counter signal output from the execution unit 13 of the processor module 10 according to the result of the logical product output from the logical product circuit 214. One of the PCs 2 is selected, and the selection result is output to the PC comparison unit 22. The selection circuit 215 selects the program counter signal PC2 when the logical product result of the logical product circuit 214 is “1”, while selecting the program counter signal PC2 when the logical product result of the logical product circuit 214 is “0”. The counter signal PC is selected.

  The PC selection unit 21 configured as described above indicates that the control signal CNT output from the execution unit 13 indicates reading from the memory module 20 and the read register signal RREG1 output from the register read unit 12 of the processor module 10. Alternatively, when RREG2 and the write register signal WREG output from the execution unit 13 of the processor module 10 match, the program counter signal PC2 output from the execution unit 13 is selected and output. On the other hand, when the control signal CNT does not indicate reading from the memory module 20 or the read register signal RREG1 or RREG2 does not match the write register signal WREG, the PC selection unit 21 outputs a program output from the instruction fetch unit 11 The counter signal PC is selected and output.

  Thus, the PC selection unit 21 is held in the program counter 111 of the instruction fetch unit 11 when an instruction that refers to the result of the read is issued immediately after the read instruction to the memory module 20 is issued. Instead of the value, the value held in the register 131 (5) of the execution unit 13 is selected. Therefore, the PC selection unit 21 executes each instruction correctly even for a data hazard that may occur immediately after issuing a read instruction to the memory module 20 when an instruction that refers to the result of the read is issued. The program counter signal can be selected so that the number can be counted.

  The PC table 24 stores a specific execution address in the program. The specific execution address is determined, for example, by a developer or the like based on the type and characteristics of the instruction. The predetermined execution address stored in the PC table 24 is output to the PC comparison unit 22. The PC table 24 typically stores a plurality of predetermined execution address values, and the comparators 221 (1) to 221 (n) of the PC comparison unit 22 each have a signal indicating a different execution address value. Output. In this example, the PC table 24 is provided as a part of the performance evaluation module 40. However, the present invention is not limited to this, and the PC table 24 is stored in the memory module 20. Also good.

  The PC comparison unit 22 compares the value indicated by the program counter signal selected by the PC selection unit 21 with the value of the specific execution address stored in the PC table 24, and counts the result of the comparison as the coincidence signal ACCODE. Output to the control unit 23. The PC comparison unit 22 includes, for example, comparators 221 (1) to 221 (n) and an OR circuit 222.

  The comparators 221 (1) to 221 (n) compare the value of the program counter signal output from the PC selection unit 21 with the value of the execution address output from the PC table 24, and OR the results of the comparison. Output to the circuit 222. When the comparators 221 (1) to 221 (n) determine that the value of the program counter signal matches the value of the execution address, the comparator 221 (1) to 221 (n) outputs a signal indicating the state of “1”, while the value of the program counter signal When it is determined that the value of the execution address does not match, a signal indicating the state of “0” is output.

  The logical sum circuit 222 performs a logical sum on the comparison results output from the comparators 221 (1) to 221 (n), and outputs the logical sum result to the count control unit 23 as the coincidence signal ACCODE.

  The count control unit 23 latches the coincidence signal ACCODED output from the PC comparison unit 22 and outputs it to the counter 235. Further, the count control unit 23 controls the state of the signal output to the counter 235 according to the state of the result signal RESULT output from the execution unit 13 of the processor module 10. The count control unit 23 includes, for example, a signal determination unit 231, selection circuits 232 (1) and 232 (2), sequential circuits 233 (1) and 233 (2), and an AND circuit 234. .

  The signal determination unit 231 determines whether or not the content indicated by the result signal RESULT output from the execution unit 13 of the processor module 10 is “branch condition satisfied”. When the content indicated by the result signal RESULT is “branch condition satisfied”, the signal determination unit 231 performs, for example, a signal indicating the state of “1” with the selection terminals SL of the selection circuits 232 (1) and 232 (2). Output to the circuit 234. On the other hand, when the content indicated by the result signal RESULT is “branch condition not satisfied”, the signal determination unit 231 selects, for example, a signal indicating a state of “0” by the selection circuits 232 (1) and 232 (2). The data is output to the terminal SL and the logical product circuit 234.

  The selection circuit 232 is a multiplexer, for example, but is not limited thereto, and may be a data selector or a signal switch. The selection circuit 232 selects either of the signals input to the input terminal A0 or A1 according to the signal input to the selection terminal SL and outputs the selected signal from the output terminal Y. Specifically, the selection circuit 232 (1) selects the coincidence signal ACCODED output from the PC comparison unit 22 when the signal output from the signal determination unit 231 indicates “0”, for example. When the signal output from the signal determination unit 231 indicates “1”, for example, the selection circuit 232 (1) selects the signal output from the AND circuit 234, and the result of the selection is displayed as the sequential circuit 233 ( 1) to the data input terminal D. The selection circuit 232 (2) selects the signal output from the sequential circuit 233 (1) when the signal output from the signal determination unit 231 indicates, for example, “0”. When the signal output from the signal determination unit 231 indicates, for example, “1”, the selection circuit 232 (2) selects the signal output from the AND circuit 234, and the result of the selection is displayed as the sequential circuit 233 ( 2) to the data input terminal D.

  The sequential circuit 233 is, for example, a D-type flip-flop, but is not limited thereto. The sequential circuit 233 outputs a signal input to the data input terminal D from the data output terminal Q based on the clock input to the clock terminal CK. Specifically, the sequential circuit 233 (1) outputs a signal output from the selection circuit 232 (1) to the input terminal A1 of the selection circuit 232 (2) based on a predetermined clock CLK. The sequential circuit 233 (2) outputs a signal output from the selection circuit 232 (2) to the logical product circuit 234 and the counter 235 based on a predetermined clock CLK.

  The logical product circuit 234 performs a logical product on the signal output from the signal determination unit 231 and the signal output from the sequential circuit 233 (2), and the result of the logical product is input to the selection circuit 232 (1). The data is output to the terminal A0 and the input terminal A0 of the selection circuit 232 (2).

  The counter 235 receives a signal output from the sequential circuit 233 (2). When the signal output from the sequential circuit 233 (2) indicates, for example, “1”, the counter 235 performs counting and updates the count value. The counter 235 outputs the count result to the memory module 20 via the chipset 30 as the count signal COUNT.

  When the result signal RESULT output from the execution unit 13 indicates “branch condition not satisfied”, the count control unit 23 configured as described above uses the sequential circuit 233 (1 ) And 233 (2), and the latched result is output to the counter 235. On the other hand, the count control unit 23 sets the states of the sequential circuits 233 (1) and 233 (2) to the output state of the sequential circuit 233 (2) when the result signal RESULT indicates “branch condition satisfied”. The counter 235 counts based on the state of the sequential circuit.

  Accordingly, the count control unit 23 sets the inputs of the sequential circuits 233 (1) and 233 (2) to the output of the sequential circuit 233 (2) when the result signal RESULT indicates “branch instruction is established”. The count value of the instruction for two times after the instruction is issued is not the count value of each instruction when the branch condition is not satisfied, but the count value of the branch instruction. Therefore, the count control unit 23 can control the count value so that the number of executions of individual instructions can be correctly counted even for a control hazard that occurs when a branch condition is satisfied.

  The performance evaluation module 40 configured as described above determines whether or not the program counter signal selected by the PC selection unit 21 matches a predetermined execution address by the PC comparison unit 22, and the determination is made. The result is latched by the count control unit 23, and the control is performed when the branch condition is satisfied for the latched signal, and then the counter 235 performs counting. Thereby, the performance evaluation module 40 can count the number of executions of individual instructions corresponding to a predetermined execution address among the instructions executed in the processor module 10.

  In this example, the performance evaluation module 40 includes one PC table 24, but is not limited thereto. The performance evaluation module 40 includes a plurality of PC tables 24, and each time the performance evaluation module 40 is executed, one PC table 24 is selected from the plurality of PC tables 24, and the selected PC table 24 is selected. The stored predetermined address may be compared with the value indicated by the program counter selected by the PC selection unit 21.

  In this example, the performance evaluation module 40 includes one PC selection unit 21, one PC comparison unit 22, and one count control unit 23. However, the present invention is not limited to this. The performance evaluation module 40 may include a plurality of PC selection units 21, PC comparison units 22, and count control units 23, respectively. The performance evaluation module 40 can individually count the number of executions of different instructions in a single process by storing the execution addresses of different instructions in the PC table 24 of each PC comparison unit 22.

  FIG. 6 is a flowchart showing an example of the operation of the performance evaluation module according to the embodiment of the present invention. In the figure, the performance evaluation module 40 first receives various signals from the processor module 10. Specifically, the performance evaluation module 40 includes the program counter signal PC from the instruction fetch unit 11 of the processor module 10, the read register signals RREG1 and RREG2 from the register read unit 12, and the program counter signal PC2 and the write register from the execution unit 13. The signal WREG and the control signal CNT are received (S601). The performance evaluation module 40 compares the received read register signals RREG1 and RREG2 with the write register signal WREG (S602).

  Next, the performance evaluation module 40 determines whether or not the control signal CNT indicates a read command for the memory module 20 and the read register signal RREG1 or RREG2 matches the write register signal WREG (S603). When the control signal CNT indicates a read command for the memory module 20 and the performance evaluation module 40 determines that the read register signal RREG1 or RREG2 and the write register signal WREG match (Yes in S603), the performance evaluation module 40 outputs from the execution unit 13 The program counter signal PC2 to be executed is selected (S604). On the other hand, the performance evaluation module 40 determines that the control signal CNT does not indicate a read command for the memory module 20 or that the read register signal RREG1 or RREG2 and the write register signal WREG do not match (S603). No), the program counter signal PC output from the instruction fetch unit 11 is selected (S605).

  Subsequently, the performance evaluation module 40 counts the number of instructions executed according to the selected program counter signal (S606). Details of the process in step S606 will be described with reference to FIG.

  FIG. 7 is a flowchart showing an example of the operation of the performance evaluation module according to the embodiment of the present invention, and shows details of the processing in step S606 in FIG. As shown in the figure, first, the performance evaluation module 40 compares the value of the program counter signal selected in the process of step S604 or S605 of FIG. 6 with the value stored in the PC table 24 (S701).

  Next, the performance evaluation module 40 determines whether or not the result signal RESULT output from the execution unit 13 of the processor module 10 indicates “branch condition instruction established” (S702). When the result signal RESULT indicates “branch condition satisfied” (Yes in S702), the performance evaluation module 40 sets the inputs of the sequential circuits 233 (1) and 233 (2) to the output of the sequential circuit 233 (2) ( S703). On the other hand, when the result signal RESULT does not indicate “satisfaction of branch condition” (No in S702), the performance evaluation module 40 converts the input of the sequential circuit 233 (1) into the comparison result in the process of Step S701, and the sequential circuit 233 (2 ) Is set to the output of the sequential circuit 233 (1) (S704).

  Next, the performance evaluation module 40 determines whether or not the output of the sequential circuit 233 (2) is “1” (S705). When the output of the sequential circuit 233 (2) is “1” (Yes in S705), the performance evaluation module 40 increments the counter 235 (S706), and proceeds to the process of step S707. On the other hand, when the output of the sequential circuit 233 (2) is not “1” (No in S705), the performance evaluation module 40 proceeds to the process of step S707.

  The performance evaluation module 40 updates the outputs of the sequential circuits 233 (1) and 233 (2) to their own inputs (S707), and ends the process.

  As described above, the performance evaluation module 40 compares the value of the program counter output from the instruction fetch unit 11 with the value stored in the PC table 24 and counts according to the result of the comparison. It is possible to count the number of executions of instructions corresponding to the execution addresses stored in. Further, when it is determined that the branch condition is satisfied, the performance evaluation module 40 inputs the inputs of the sequential circuits 233 (1) and 233 (2) to the output of the sequential circuit 233 (2) (that is, the value of the program counter of the branch instruction) Therefore, even when a control hazard occurs due to a branch instruction, the number of instructions executed can be counted correctly. The performance evaluation module 40 uses the value of the program counter output from the execution unit 13 when an instruction that refers to the result of the read instruction is issued immediately after the read instruction to the memory module 20. Even for a data hazard that occurs by referring to the result of an instruction immediately, the number of instructions executed can be counted correctly.

  Next, an example in which the performance evaluation module 40 counts the number of executions for each different instruction will be described with reference to FIGS. Here, the performance evaluation module 40 counts the number of executions for each instruction group identified according to an identifier (ID) assigned to each specific one or more instructions. Therefore, a PC table 24 for storing the value of the execution address of the instruction is prepared for each different ID, and the performance evaluation module 40 includes a PC selection unit 21, a PC comparison unit 22 corresponding to each of the plurality of PC tables 24, A plurality of configurations including the count control unit 23 are included.

  FIG. 8 is a conceptual diagram for explaining the counting operation of the performance evaluation module in the pipeline processing by the processor module of the semiconductor integrated circuit according to one embodiment of the present invention. In the figure, timings at which the processor module 10 operates in accordance with a predetermined operation clock are indicated as t801 to t809. That is, the figure shows which component of the processor module 10 each of a certain series of instructions (instruction 1 to instruction 5) is processed at a certain time t. Here, “IF”, “RR”, “EX”, “MA”, and “WB” are an instruction fetch unit 11, a register read unit 12, an execution unit 13, a memory access unit 14, and a write back unit 15, respectively. Point to. In addition, ID # 0 is assigned to Instruction 1, Instruction 3 and Instruction 5, and ID # 1 is assigned to Instruction 2 and Instruction 4. In this example, the execution address of the instruction assigned ID # 0 is stored in the first PC table 24a, and the execution address of the instruction assigned ID # 1 is stored in the second PC table 24b. It is assumed that the third PC table 24c stores the execution address of the instruction assigned ID # 0 and ID # 1.

  At time t801, the instruction fetch unit 11 of the processor module 10 fetches the instruction 1 from the memory module 20 and outputs the value of the program counter for the instruction 1 to the performance evaluation module 40. As described above, the performance evaluation module 40 compares the value of the program counter latched for two clocks with the value of the predetermined execution address stored in the PC table 24, and determines that they match. In this case, the number of executions of the corresponding instruction is counted up. However, since the value of the program counter for instruction 1 is not yet latched for two clocks, the performance evaluation module 40 does not count up. Therefore, the number of executions of instructions corresponding to ID # 0 and ID # 1 remains 0.

  At time t <b> 802, the instruction fetch unit 11 fetches the instruction 2 and outputs the value of the program counter for the instruction 2 to the performance evaluation module 40. Further, the processor module 10 processes the instruction 1 by the register read unit 12. Since the value of the program counter for instruction 1 and instruction 2 has not yet been latched for two clocks, the performance evaluation module 40 does not count up the number of executions of instructions corresponding to ID # 0 and ID # 1. The execution number and the total instruction execution number remain zero.

  At time t803, the instruction fetch unit 11 fetches the instruction 3 and outputs the value of the program counter for the instruction 3 to the performance evaluation module 40. Further, the register read unit 12 processes the instruction 2 while the execution unit 13 processes the instruction 1. Since the value of the program counter for instruction 1 is latched for two clocks at time t803, the performance evaluation module 40 increments the execution number of the instruction corresponding to ID # 0 by one and sets it to 1. On the other hand, since the value of the program counter for instruction 2 is not yet latched for two clocks, the number of executions of the instruction corresponding to ID # 1 remains zero. At time t803, the total number of executed instructions is 1 because it is the total number of executed instructions corresponding to ID # 0 and ID # 1.

  At time t804, the instruction fetch unit 11 fetches the instruction 4 and outputs the value of the program counter for the instruction 4 to the performance evaluation module 40. The register read unit 12 processes the instruction 3, the execution unit 13 processes the instruction 2, and the memory access unit 14 processes the instruction 1. At time t804, since the value of the program counter for instruction 2 is latched for two clocks, the performance evaluation module 40 increments the execution number of the instruction corresponding to ID # 1 by one and sets it to 1. At time t804, the total number of instructions executed becomes 2.

  At time t805, the instruction fetch unit 11 fetches the instruction 5, and outputs the value of the program counter indicating the instruction 5 to the performance evaluation module 40. The register read unit 12, the execution unit 13, the memory access unit 14, and the write back unit 15 process the instruction 4, the instruction 3, the instruction 2, and the instruction 1, respectively. Since the value of the program counter for the instruction 3 is latched for two clocks at time t804, the performance evaluation module 40 increments the number of executions of the instruction corresponding to ID # 0 by one and sets it to 2. At time t805, the total number of instructions executed is 3.

  Even after time t806, each component of the processor module 10 pipelines a series of instructions as described above. For the value of the program counter obtained by latching the value of the program counter received from the processor module 10 by two clocks, the performance evaluation module 40 matches the value of the predetermined execution address stored in the PC table 24. In this case, the program counter is incremented by one.

  As described above, each component of the processor module 10 sequentially pipelines a series of instructions, while the performance evaluation module 40 latches the value of the program counter sent from the instruction fetch unit 11 for two clocks. When the value of the program counter matches the value of the predetermined execution address stored in the PC table 24, the count is performed. Thereby, the performance evaluation module 40 can count the number of executions of a specific instruction on a clock cycle basis.

  Next, the execution count by the performance evaluation module 40 when a branch instruction is included in a series of instructions will be described. FIG. 9 is a conceptual diagram for explaining the count operation of the performance evaluation module in the pipeline processing by the processor module of the semiconductor integrated circuit according to one embodiment of the present invention. In the figure, timings at which the processor module 10 operates according to a predetermined operation clock are indicated as t901 to t909. In this example, instruction # 1 and instruction # 4 are assigned ID # 0, and instruction # 2, instruction # 3 and instruction # 5 are assigned ID # 1. The first PC table 24a stores the execution address of the instruction assigned ID # 0, and the second PC table 24b stores the execution address of the instruction assigned ID # 1. It is assumed that the third PC table 24c stores execution addresses of instructions assigned to ID # 0 and ID # 1. In addition, it is assumed that the instruction 1 is an instruction that branches to the instruction 4 when the branch condition is satisfied, and that follows the instruction 2 when the branch condition is not satisfied.

  At time t901, the instruction fetch unit 11 similarly fetches the instruction 1 and outputs the value of the program counter for the instruction 1 to the performance evaluation module 40. Since the value of the program counter for instruction 1 is not yet latched for two clocks, the performance evaluation module 40 does not count up. Therefore, the number of executions of the instructions corresponding to ID # 0 and ID # 1 and the total number of instructions remains 0. Note that it is unknown whether the branch condition is satisfied until the instruction 1 is processed by the execution unit 13. Each component of the processor module 10 performs a given process on the instruction as described above until it is determined whether the branch condition of the instruction 1 is satisfied.

  At time t <b> 902, the instruction fetch unit 11 fetches the instruction 2 and outputs the value of the program counter for the instruction 2 to the performance evaluation module 40. Further, the register read unit 12 processes the instruction 1. At time t902, the value of the program counter for instruction 1 is not yet latched for two clocks, so the number of executions of instructions corresponding to ID # 0 and ID # 1 and the execution number of all instructions remain 0. is there.

  At time t903, the instruction fetch unit 11 fetches the instruction 3, and outputs the value of the program counter for the instruction 3 to the performance evaluation module 40. Further, the execution unit 13 processes the instruction 1. In this example, the execution unit 13 determines that the branch condition is satisfied as a result of the processing, and outputs a control signal CNT indicating “branch condition satisfied” to the performance evaluation module 40. The performance evaluation module 40 changes all of the latched program counter values for two clocks (that is, for the instruction 1 and the instruction 2) to the program counter value for the instruction 1 in accordance with the control signal CNT. Since the performance evaluation module 40 counts the value of the program counter for the instruction 1, the execution number of the instruction corresponding to the ID # 0 is set to 1. On the other hand, the value of the program counter for instruction 2 is not counted because it has been changed to the value of the program counter for instruction 1, and the number of executions of the instruction corresponding to ID # 1 remains zero. At time t903, the total number of executed instructions is 1.

  At time t904, the instruction fetch unit 11 fetches the instruction 4 and outputs the value of the program counter for the instruction 4 to the performance evaluation module 40. Further, the memory access unit 14 processes the instruction 1, but since the branch condition is satisfied in the execution unit 13, the processing for the instruction 3 by the register read unit 12 and the processing for the instruction 2 by the execution unit 13 are stopped. Since the value of the program counter for instruction 1 is latched twice at time t904, the performance evaluation module 40 counts up the number of executions of the instruction corresponding to ID # 0 and sets it to 2. At time t904, the total number of executed instructions is 2.

  At time t905, the instruction fetch unit 11 fetches the instruction 5, and outputs the value of the program counter for the instruction 5 to the performance evaluation module 40. The register read unit 12 processes the instruction 4, and the write back unit 15 processes the instruction 1. Since the value of the program counter for instruction 1 is latched twice, the performance evaluation module 40 counts up the number of executions of the instruction corresponding to ID # 0 to 3. On the other hand, since the value of the program counter for instruction 5 is not latched twice at time t905, the number of executions of the instruction corresponding to ID # 1 remains zero. At time t905, the total number of instructions executed is 3.

  At time t906, the register read unit 12 processes the instruction 5, and the execution unit 13 processes the instruction 4. Since the value of the program counter for the instruction 4 is latched twice, the performance evaluation module 40 counts up the number of executions of the instruction corresponding to ID # 0 to 4. On the other hand, since the value of the program counter for instruction 5 is not latched twice at time t906, the number of executions of the instruction corresponding to ID # 1 remains zero. At time t905, the total number of instructions executed is 4.

  At time t907, the execution unit 13 processes the instruction 5, and the memory access unit 14 processes the instruction 4. Since the value of the program counter for instruction 5 is latched twice at time t907, the performance evaluation module 40 counts up the number of executions of the instruction corresponding to ID # 1 and sets it to 1. At time t907, the total number of executed instructions is 5.

  As described above, when each component of the processor module 10 includes a branch instruction in a series of instructions, it proceeds with a given process for the instruction until it is determined whether the branch condition is satisfied. If it is determined that is satisfied, the processing so far is stopped, and a control signal CNT indicating that the branch condition is satisfied is output to the performance evaluation module 40. The performance evaluation module 40 changes the value of the program counter latched for two clocks to the value of the program counter corresponding to the branch instruction in accordance with the control signal CNT. As a result, the performance evaluation module 40 counts the delay due to the control hazard caused by the execution of the branch instruction as the delay due to the branch instruction, so that the execution number of each instruction can be correctly counted on a clock cycle basis.

  FIG. 10 is a conceptual diagram for explaining the count operation of the performance evaluation module in the pipeline processing by the processor module of the semiconductor integrated circuit according to one embodiment of the present invention. In the figure, the time when each component of the processor module 10 processes each instruction is defined as time t1001 to t1008. Also, in the figure, ID # 0 is assigned to instruction 1 to instruction 3, and ID # 1 is assigned to instruction 4. The first PC table 24a stores an execution address of an instruction assigned ID # 0, and the second PC table 24b stores an execution address of an instruction assigned ID # 1. The PC table 24c stores the execution addresses of instructions assigned ID # 0 and ID # 1.

  At time t1001, the processor module 10 receives the instruction 1 from the memory module 20, and the instruction fetch unit 11 processes the instruction 1. The instruction fetch unit 11 outputs the value of the program counter indicating the instruction 1 to the performance evaluation module 40. Since the value of the program counter for instruction 1 is not yet latched for two clocks, the performance evaluation module 40 does not count up. Therefore, the number of executions of the instructions corresponding to ID # 0 and ID # 1 and the total number of instructions remains 0.

  At time t1002, the processor module 10 receives the instruction 2 indicating reading from the memory module 20 to the memory module 20, and the instruction fetch unit 11 processes the instruction 2. Further, the instruction fetch unit 11 outputs the value of the program counter indicating the instruction 2 to the performance evaluation module 40. Further, the processor module 10 processes the instruction 1 by the register read unit 12. Since the value of the program counter for instruction 1 is not latched twice at time t1002, the number of executions of the instruction corresponding to ID # 0 is still 0. At time t1002, the total number of instructions executed remains zero.

  At time t1003, the processor module 10 receives the instruction 3 referring to the result of the instruction 2 from the memory module 20, and processes the instruction 3 by the instruction fetch unit 11. Further, the instruction fetch unit 11 outputs the value of the program counter indicating the instruction 3 to the performance evaluation module 40. The processor module 10 processes the instruction 2 by the register read unit 12 and processes the instruction 1 by the execution unit 13. Since the value of the program counter of instruction 1 is latched twice at time t1003, the performance evaluation module 40 counts up the number of executions of the instruction corresponding to ID # 0 and sets it to 1. At time t1003, the total number of executed instructions is 1.

  At time t1004, the processor module 10 receives the instruction 4 from the memory module 20, and the instruction fetch unit 11 processes the instruction 4. The processor module 10 processes the instruction 2 by the execution unit 13 and processes the instruction 1 by the memory access unit 14. Further, the processor module 10 indicates that the instruction 3 is an instruction for referring to the result of the instruction 2, the instruction 2 is a read instruction for the memory module 20, and the instruction 2 has not reached the processing stage by the memory access 14. Then, the register read unit 12 waits without processing the instruction 3.

  At time t1004, the performance evaluation module 40 matches the read register signal RREG1 or RREG2 of the register read unit 12 with the write register signal WREG of the execution unit 13, and the control signal CNT of the execution unit 13 is sent to the memory module 20. Judged as a read command. The performance evaluation module 40 latches the value of the program counter of the instruction 2 of the execution unit 13 according to the determination result. Since the value of the program counter of instruction 2 is latched twice at time t1004, the performance evaluation module 40 counts up the number of executions of the instruction corresponding to ID # 0 and sets it to 2. At time t1004, the total number of executed instructions is 2.

  At time t1005, the processor module 10 processes the instruction 4 by the instruction fetch unit 11 again because the processing of the instruction 3 by the register read unit 12 is not completed. Further, the instruction fetch unit 11 outputs the value of the program counter indicating the instruction 4 to the performance evaluation module 40. The processor module 10 processes the instruction 3 by the register read unit 12, processes the instruction 2 by the memory access unit 14, and processes the instruction 1 by the write-back unit 15. Since the value of the program counter of instruction 3 is latched twice at time t1005, the performance evaluation module 40 counts up the number of executions of the instruction corresponding to ID # 0 and sets it to 3. At time t1005, the total number of executed instructions is 3.

  At time t <b> 1006, the processor module 10 processes the instruction 4 by the register read unit 12, processes the instruction 3 by the execution unit 13, and processes the instruction 2 by the write-back unit 15. Since the value of the program counter of instruction 3 is latched twice at time t1006, the performance evaluation module 40 counts up the execution number of the instruction corresponding to ID # 0 to 4. At time t1006, the total number of instructions executed is 4.

  At time t1007, the processor module 10 processes the instruction 4 by the execution unit 13 and processes the instruction 3 by the memory access unit 14. Since the value of the program counter of the instruction 4 is latched twice at time t1007, the performance evaluation module 40 counts up the number of executions of the instruction corresponding to ID # 1 to 1. At time t1007, the total number of executed instructions becomes 5.

  As described above, when the processor module 10 receives an instruction that refers to the result of the instruction immediately after issuing a read instruction to the memory module 20, the processor module 10 transmits the instruction that refers to the result of the instruction at the stage of the register read unit 12. Wait for one stage. Further, the performance evaluation module 40 latches the value of the program counter of the execution unit 13 when an instruction that refers to the result of the instruction is issued immediately after issuing a read instruction to the memory module 20, and therefore a delay due to standby The time is counted as the value of the program counter of the read command for the memory module 20.

  As a result, the performance evaluation module 40 correctly executes each instruction even for a data hazard that occurs when an instruction that refers to the result of the read is issued immediately after issuing the read instruction to the memory module 20. The number can be counted. In the present embodiment, the read command has been described as an example. However, for example, the same can be applied to a write command.

  FIG. 11 is a diagram showing another example of a schematic configuration of a semiconductor integrated circuit according to an embodiment of the present invention. As shown in the figure, the semiconductor integrated circuit 1 ′ according to this embodiment includes a plurality of performance evaluation modules 40 (1) to 40 (m).

  The circuit configuration itself of the performance evaluation modules 40 (1) to 40 (m) is the same, but the contents (that is, the values of the execution addresses) stored in the respective PC tables 24 are different. That is, each PC table 24 stores the value of the execution address of an instruction assigned with a different ID. The performance evaluation modules 40 (1) to 40 (m) output the respective count results as count signals COUNT (1) to COUNT (m) to the memory module 20 via the chipset 30. Thereby, the semiconductor integrated circuit 1 ′ can count the number of executions of different instructions according to the number of the performance evaluation modules 40 by executing the program once.

  Each of the above embodiments is an example for explaining the present invention, and is not intended to limit the present invention only to these embodiments. The present invention can be implemented in various forms without departing from the gist thereof.

  For example, in the method disclosed herein, steps, operations, or functions may be performed in parallel or in a different order, as long as the results do not conflict. The steps, operations, and functions described are provided as examples only, and some of the steps, operations, and functions may be omitted and combined with each other without departing from the spirit of the invention. There may be one, and other steps, operations or functions may be added.

  Further, although various embodiments are disclosed in this specification, a specific feature (technical matter) in one embodiment is appropriately improved and added to another embodiment or the other implementation. Specific features in the form can be substituted, and such form is also included in the gist of the present invention.

  The present invention can be widely used in the field of semiconductor integrated circuits including a processor.

DESCRIPTION OF SYMBOLS 1 ... Semiconductor integrated circuit 10 ... Processor module 11 ... Instruction fetch part 111 ... Program counter 112 ... Instruction cache 12 ... Register read part 121 ... Register 122 ... Register file 13 ... Execution part 131 ... Register 132 ... Operation part 14 ... Memory access part 141 ... Register 142 ... Data cache 15 ... Write-back unit 151 ... Register 152 ... Selection circuit 20 ... Memory module 30 ... Chipset 40 ... Performance evaluation module 21 ... PC selection unit 211 ... Comparator 212 ... OR circuit 213 ... Signal judgment Unit 214 ... logical product circuit 215 ... selection circuit 22 ... PC comparison unit 221 ... comparator 222 ... logical sum circuit 23 ... count value control unit 231 ... signal judgment unit 232 ... selection circuit 233 ... sequential circuit 234 ... logical product circuit 235 ... Cow 24 ... PC table 50 ... Storage device 60 ... I / O device

Claims (10)

A performance evaluation module that evaluates the processing performance of a processor module that executes an instruction group of a program by pipeline processing according to a predetermined operation clock,
A program counter table for storing an execution address value for at least one instruction of the instruction group;
A program counter comparison unit that compares a value of a program counter sent from the processor module with processing of an instruction by the processor module and a value of an execution address stored in the program counter table, and determines whether or not they match ,
A count control unit that counts and outputs the execution number of an instruction corresponding to the value of the program counter that has been compared and determined when the program counter comparison unit determines that the values match;
A performance evaluation module comprising:   The count control unit includes a plurality of sequential circuits connected in stages, and sequentially latches the value of the program counter for a predetermined clock cycle of the predetermined operation clock by the plurality of sequential circuits. The performance evaluation module according to claim 1, wherein the execution number is counted.   The performance evaluation module according to claim 2, wherein the predetermined clock cycle is the number of clock cycles required for the processor module to execute the one instruction after fetching the one instruction. The count control unit
When one instruction to be executed by the processor module is a branch instruction and the branch condition of the branch instruction is satisfied, the value of the program counter latched for the predetermined clock cycle is held. The performance evaluation module according to claim 2, wherein an output of the sequential circuit is input to each of the plurality of sequential circuits. The count control unit
5. The performance evaluation module according to claim 4, wherein when the branch condition of the predetermined branch instruction is not satisfied, the value of the program / program counter determined by comparison is input to the sequential circuit in the forefront stage. The count control unit
One instruction to be executed by the processor module is a read instruction for a predetermined memory module, and an address indicating an area for storing a value read from the predetermined memory module after the execution of the operation The value of the program counter latched until the execution of the operation of the one instruction when the value matches the value of the address indicating the area for storing the value according to the other instruction before the execution of the operation of the other instruction The performance evaluation module according to claim 1, further comprising: a selection unit that sends a message to the program counter comparison unit.   The performance evaluation module according to claim 1, wherein the performance evaluation module counts the number of executions for each identifier assigned to one or more of the instructions. A processor module that executes a group of program instructions by pipeline processing according to a predetermined operation clock;
At least one performance evaluation module connected to the processor module;
A program counter table for storing an execution address value for at least one instruction of the instruction group;
With
The at least one performance evaluation module includes:
A program counter comparison unit that compares a value of a program counter associated with processing of an instruction by the processor module and a value of an execution address stored in the program counter table, and determines whether or not they match.
A counter control unit that counts the number of instructions executed corresponding to the value of the program counter,
The program counter comparison unit determines whether or not they match based on the value of the program counter sent from the processor module by fetching an instruction by the processor module;
The count control unit
When it is determined by the program counter comparison unit that they match, the execution count of the instruction corresponding to the value of the program counter determined to be compared is counted and output.
Semiconductor integrated circuit. The semiconductor integrated circuit includes a plurality of the performance evaluation modules for counting the number of executions for each identifier assigned to one or more of the instructions.
The semiconductor integrated circuit according to claim 8. A performance evaluation method for evaluating the processing performance of a processor module that executes an instruction group of a program by pipeline processing according to a predetermined operation clock,
Receiving a value of a program counter sent from the processor module in accordance with processing of an instruction by the processor module;
Receiving an execution address value for at least one instruction of the group of instructions stored in a program counter table;
Comparing the value of the program counter with the value of the execution address to determine whether they match,
When it is determined that the value of the program counter matches the value of the execution address, counting the number of executions of the instruction corresponding to the value of the program counter determined to be compared;
A method for evaluating performance.