JP2001209556A - Verification supporting system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a verification supporting system in which a coordinative verification between a hardware and a software is made possible while effectively using a high speed property of an FPGA(Field Programmable Gate Array) emulator. SOLUTION: In the verification supporting system carrying out, on the FPGA emulator, a verification of an object logic circuit including a processor, a verifying logic depending on the processor is mapped to an FPGA existing in the FPGA emulator by a circuit description.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an FPGA (Field
The present invention relates to a verification support system using a device that emulates hardware based on a programmable gate array (hereinafter referred to as an FPGA emulator). More specifically, the present invention relates to a verification support system improved to enable hardware verification, software verification, or hardware / software verification using an FPGA emulator.

[0002]

2. Description of the Related Art An FPGA emulator is a device that applies a feature that an FPGA is a programmable element, maps a logic circuit to an FPGA arranged in an array, and emulates the logic circuit at high speed. Compared to a logic circuit simulator that operates on a personal computer or a workstation, an FPGA emulator performs emulation with an FPGA, so it is said that verification can be performed 1000 times or more. Further, the FPGA emulator has an advantage that the verification speed does not decrease even if the hardware increases, and is an indispensable device for prototype verification of a large-scale IC such as a system LSI. The FPGA emulator is mainly used for hardware verification.

In recent years, with the miniaturization of semiconductor processes,
The logic incorporated in C is enormous. System L
In SI, the circuit of the entire system including the processor is incorporated in one IC, and verification of hardware as in the past is not sufficient, and co-verification of hardware and software including software is required. I have.

The FPGA emulator has the disadvantage that it can perform high-speed hardware prototype verification, but lacks a verification function such as a debugger. FPGA
In order to perform not only hardware verification but also software verification using an emulator, the following verification support system was conventionally constructed.

(Conventional Example 1) FIG. 5 is a diagram showing a configuration example of a conventional verification support system. In the conventional example shown in FIG. 5, a logic circuit other than the processor is mounted on the FPGA in the FPGA emulator 1 and the ICE 2 (Incircuit-Emulato) is provided outside the FPGA emulator 1.
Emulate the processor part by connecting r). For verification of software, a debugger 3 connected to the ICE 2 is used. The FPGA of the FPGA emulator 1 has a logic circuit 4 as a logic circuit other than the processor and a memory 5 mounted thereon.

(Conventional Example 2) FIG. 6 is a diagram showing another configuration example of a conventional verification support system. In the conventional example of FIG. 6, the host computer system 6 and the FPGA
Emulator 1 is connected. An instruction execution part unique to the processor is replaced with an instruction set simulator 7 (Instruction Se
tSimulator). In the FPGA emulator 1, a logic circuit of a processor other than the instruction set simulator 7 and an external bus control circuit of the processor are mounted. These circuits are logic circuits 8. And FP
A co-simulation by the GA emulator 1 and the instruction set simulator 7 is executed. The software verification environment is implemented in the instruction set simulator 7.

However, the first conventional example has the following problems. Since the ICE 2 is connected to the outside of the FPGA emulator 1, the processor to be verified is limited to an IC-based processor. Generally, a processor core for a system LSI is arranged as a component in an IC.
Even if it has the same function as an integrated processor used as CE, there are differences in timing, clock control, and bus control. Therefore, it is different from the actual use state.

Although the FPGA emulator is fast,
Still, the operating frequency is about 1 MHz. However, most ICEs do not guarantee operation at such frequencies.

[0009] Since the FPGA emulator and the ICE are connected by a cable, the operation may become unstable due to signal distortion, signal timing deviation, noise, or the like at the connector or the soldered portion.

In the actual software verification, ICE
Causes an interrupt when the address of the processor reaches the breakpoint, and starts the debugger in the interrupt processing. When the breakpoint is reached, the clock supplied to the processor does not stop. Therefore, the clocks of circuits other than the processor do not stop. For example, in communication and other verifications, even if a break occurs to verify software, the hardware operates regardless of the processor break, resulting in a communication error or the like. Cannot be verified.

The conventional example 2 has the following problems. FPG
Since the co-simulation is performed by the A emulator and the simulator, it is necessary to synchronize between the FPGA emulator and the simulator, and the emulator verification speed of about 1 MHz is reduced to about 1 KHz.
It was not practical.

[0012]

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-mentioned problems, and a processor-dependent verification logic is mapped to an FPGA in an FPGA emulator by a circuit description. FP
The GA emulator has a software verification function.
An object of the present invention is to realize a verification support system that enables cooperative verification of hardware and software while utilizing the high speed of a PGA emulator.

[0013]

SUMMARY OF THE INVENTION The present invention is a verification support system having the following configuration.

(1) In a verification support system for executing a verification of a target logic circuit including a processor on an FPGA emulator, an FPGA included in the FPGA emulator
A verification support system characterized in that processor-dependent verification logic is mapped by a circuit description.

(2) In a verification support system for executing verification of a target logic circuit including a processor on an FPGA emulator, a processor circuit that can be mapped to an FPGA of the FPGA emulator, and a logic circuit included in the target logic circuit. From a logic circuit that is a logic circuit other than the processor circuit and a logic circuit of the processor circuit,
Execution address generating means for generating one or more internal signals and generating an address to be executed by the processor;
A break condition storage unit that is specified by the host computer system and holds one or more break conditions for verifying software; and an execution address generated by the execution address generation unit and a condition held by the break condition storage unit. A first comparator group to be compared, a break signal generation means for generating a break signal when the execution address matches at least one break condition as a result of the comparison by the first comparator group, and a break signal generation means Receiving the break signal from the host computer system and notifying the host computer system, and supplying clocks to the processor circuit and the logic circuit, and interface means for notifying the FPGA emulator of the information sent from the host computer system. break And clock generation means for stopping the clock supply to the processor circuit and the logic circuit when the signal is generated, and for re-supplying the clock in response to a restart instruction from the host computer system, by mapping the circuit description to the FPGA. Verification support system.

(3) The clock generating means is mounted on an in-circuit board as a clock generating circuit,
The verification support system according to (2), wherein the in-circuit board and the FPGA emulator are connected via an in-circuit interface of the A emulator.

(4) The verification support system according to (2) or (3), wherein the internal state of the processor is notified to the host computer system via the interface means.

(5) It has a general-purpose memory defined in the FPGA emulator and a counter indicating the address of the general-purpose memory. The execution address information from the execution address generating means and the instruction information executed by the processor are stored in the general-purpose memory. The verification support system according to (2) or (3), wherein at least one of them is stored, and at the time of a break, trace information as an operation history of the processor is extracted from a general-purpose memory and transferred to a host computer system.

(6) The verification support system according to (2) or (3), wherein a bus access condition from the processor circuit is added as a break condition to the break condition storage means.

(7) Two pieces of address information are added to the break condition storing means, and a second comparator for detecting a case where the address is out of the range determined by the two pieces of address information as a break condition is provided by the first comparator group and the first comparator group. The verification support system according to (2) or (3), which is mounted in parallel.

(8) A second condition in which two pieces of address information are added to the break condition storage means, and a case where the information falls within a range determined by these two pieces of address information is detected as a break condition.
The verification support system according to (2) or (3), wherein the comparator is mounted in parallel with the first comparator group.

(9) In a verification support system for executing verification of a target logic circuit including a processor on an FPGA emulator, a processor circuit that can be mapped to an FPGA in the FPGA emulator and executes a plurality of instructions simultaneously, and the target logic circuit By combining one or more internal signals from a logic circuit which is a logic circuit other than the processor circuit among the logic circuits in the above and a logic circuit of the processor circuit, execution addresses are respectively given to instructions simultaneously executed by the processor. An execution address generating means for generating a program, a break condition storing means designated by the host computer system and holding one or more conditions for performing software verification, and a plurality of break condition storing means provided in accordance with the number of simultaneously executed instructions. Execution address generated by the address generation means And a plurality of comparator groups for comparing the conditions held by the break condition storing means with the plurality of comparator groups, and a break signal generation circuit for generating a break signal when an execution address matches at least one break condition as a result of comparison by the plurality of comparator groups. Means, an interface means for receiving a break signal from the break signal generating means, notifying the host computer system system, and notifying the FPGA emulator of information sent from the host computer system, and providing a clock to the processor circuit and its peripheral circuits. Clock generation means for stopping the clock to the processor circuit and its peripheral circuits when the break signal generation means generates a break signal, and re-supplying the clock in response to a restart instruction from the host computer system. Description Verification support system, characterized in that was mapped to the FPGA.

(10) The clock generation means is mounted as a clock generation circuit on an in-circuit board, and
(9) The verification support system according to (9), wherein the in-circuit board and the FPGA emulator are connected via an in-circuit interface of the GA emulator.

(11) Software verification means mounted on a host computer system, which calculates execution address and data conditions from software code, and performs verification including source code verification, processor register display, and inverse conversion to assembler code. The verification support system according to (2) or (3), further comprising an interface between the software verification unit and the verification logic mapped to the FPGA via the interface unit.

(12) The verification support system according to (2) or (3), wherein a stop condition in one or more instruction execution units is added to the break condition of the break signal generation means.

(13) A break condition for stopping the clock generation each time the clock generation means or the clock generation circuit generates one or a plurality of clocks is added to the break signal generation means (2) or (3) The verification support system described above.

(14) The internal information of the processor is stored in the first
FP is the first copy means for copying to the memory of the
The verification support system according to (2) or (3), wherein the verification support system is mounted on a GA emulator and collectively transfers internal information of the first memory to a host computer system at a predetermined timing.

(15) The second memory for storing break information sent from the interface means as needed, and the break information stored in the second memory at a predetermined timing are collectively copied to the break condition storage means. The verification support system according to (2) or (3), wherein the second copy means is mapped to an FPGA emulator.

(16) The verification support system according to (14) or (15), wherein the first memory and the second memory are replaced by one memory.

(17) A logic circuit including a plurality of processors is to be verified, and the processor circuit, the execution address generation means, the break condition storage means, and the first comparator group are mounted on each processor, and are commonly used for each processor. The verification support system according to (2) or (3), wherein the clock generation means or the clock generation circuit, the break signal generation means, and the interface means are mounted.

(18) The processor circuit is connected to an actual IC
Replaced with a processor chip that has been integrated, using the debug support circuit built into this processor chip,
The verification support system according to (2) or (3), wherein the processor circuit and an execution address generation means mapped to the FPGA are connected.

(19) The processor circuit, the logic circuit,
An execution address generation unit, a break condition storage unit, a first comparator group, a break signal generation unit, an interface unit, and a clock generation unit or a clock generation circuit are mounted on an emulator configured by one or more emulation dedicated processors. The verification support system according to (2) or (3), wherein:

(20) The processor circuit, the logic circuit, the execution address generation means, the break condition storage means, the first comparator group, the break signal generation means, the interface means, and the clock generation means or the clock generation circuit are replaced by a logic circuit. The verification support system according to (2) or (3), wherein the verification support system is mounted on a simulator for use.

[0034]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings. FIG. 1 is a configuration diagram showing one embodiment of the present invention. In FIG. 1, the FPGA in the FPGA emulator 20
Is mapped by the processor model 21 in the circuit description. The processor model 21 includes a processor circuit 22 as an original processor, a processor interface (hereinafter referred to as a processor I / F) 23, and a logic circuit 24 as a verification target. The logic circuit 24 is a logic circuit other than the processor circuit 22 among the logic circuits in the processor to be verified. The logic circuit 24 includes, for example, user logic. The logic circuit 24 may be an application specific IC.

The FPGA emulator 20 has a memory 2
5 and an interface means (I / F means) 26 are mounted. The memory 25 stores programs executed by the processor and data. Generally, the memory 25 stores
Tightly connected to PGA, but rarely mapped to FPGA. The I / F means 26 is an FPGA
The emulator 20 and the host computer system 30 are connected.

The host computer system 30 is provided with a hardware and software verification environment.
The host computer system 30 can be activated by the I / F means 26 to activate the emulator, check the internal state of the processor, verify software such as setting of break conditions, and execute an internal signal of the logic circuit 24 and an interrupt signal to the processor. Hardware verification for breaking at the same time becomes possible.

FIG. 2 is a block diagram of a main part of the system shown in FIG. In FIG. 2, the same components as those in FIG. FIG.
The information necessary for generating an address in the processor circuit 22 enters the execution address generation means 231 and generates an address to be executed by the processor and a timing signal thereof. The execution address information is stored in the first comparator group 232
, And the instruction execution timing signal D is input to the break signal generation means 233.

On the other hand, the break condition is stored in the second memory 234 via the interface means 26,
Of the break condition storing means 2 by the copying means 235 of
33. The held break condition is compared with the execution address by the first comparator group 232. Each comparator in the first comparator group 232 generates a match signal E when the conditions match, and is input to the break signal generation means 233. The break condition storage means 233 holds one or more break conditions. The break signal generation means 236 is connected to the first comparator group 23
As a result of the comparison in 2, a break signal is generated when the execution address matches at least one break condition.

A step function is instructed to the break signal generating means 236 by a step instruction signal B from the host computer system 30. When the step function is instructed, the instruction execution timing signal D from the execution address generation means 231 realizes a so-called step verification in which the processor breaks every time an instruction is executed.

The timer 237 is specified by the host computer system 30 in advance, and realizes a function of interrupting the computer from the emulator at regular intervals.
With this function, even when the processor cannot reach the break condition due to a break condition setting error or a program or logic circuit design error, the function of forcibly stopping the emulation from the host computer system 30 can be realized.

The break condition generating means 233 outputs a break signal A when at least one of the following conditions is satisfied: an instruction of a step function, a periodic interruption by the timer 237, and a match detection in the first comparator group 232.
At the same time as interrupting the host computer system 30 via the I / F means 26,
38, requesting that the clock be stopped.

The clock generation means 238 stops and restarts the clock in response to a stop instruction from the break signal generation means 236 and a restart instruction (restart signal C) from the host computer system 30 via the I / F means 26. Repeat startup. The clock generation means 238 includes the processor circuit 2
2 as well as a clock to the logic circuit 24 around the processor. So not only the processor,
It is possible to control the stop and start of the clock of the peripheral circuit.
When the clock is active, the emulation speed of the FPGA emulator 20 is not reduced because the emulation is performed at the original operation speed.

Information such as registers in the processor is stored in the first
Is stored in the first memory 240 via the copying means 239, and is notified to the host computer system 30 via the I / F means 26.

The verification logic dependent on the processor, which is composed of the execution address generation means 231, the break condition storage means 233, the first comparator group 232, and the clock control means 238, is represented by a circuit description and mapped to the FPGA. .

The standard operating procedure from the hardware and software verification environment is as follows. (1) Initialize the timer 237 and the like, and download the program to the memory 25. (2) Set a breakpoint. (3) Set hardware break conditions. (4) Start emulation. (Equivalent to restart) (5) When the break condition is satisfied, the break signal A
Occurs. At this time, the emulation is stopped. (6) Verify the logic circuit and the software in the verification environment. (7) Set new break conditions as required. (8) Restart the emulation. (9) A break signal is generated again. (10) The operations of (7) to (9) are repeated. If a hardware bug or a software bug is found, the circuit or program is changed, the data is remapped to the FPGA, or the program is downloaded to the memory 25, and the operation is repeated from (1).

FIG. 3 is a block diagram showing another embodiment of the present invention. In this embodiment, the software can be verified for each processor in any multiprocessor including a plurality of processors. The example in the figure shows a case where two processors are provided. Processor circuits 22A and 22B are provided for each processor. Processor interface to processor-specific I
/ F means 23A, 23B and common I / F means 27, and map to FPGA.

Processor-specific I / F means 23A, 23B
, An execution address generation unit 231, a break condition storage unit 233, and a first comparator group 232 are respectively mounted. In the common I / F unit 27, a clock generation unit 238, a break signal generation unit 236, and a timer 237 are mounted.

The present invention is not limited to the above-described embodiment, but may have various configurations. Another configuration example will be described.

A general-purpose memory may be defined in the FPGA emulator 20, and a counter indicating the address of the general-purpose memory may be provided. At least one of the execution address information from the execution address generation means 231 and the instruction information executed by the processor is stored in the general-purpose memory, and at the time of a break, trace information, which is the operation history of the processor, is extracted from the general-purpose memory and transferred to the host computer system.

Further, a bus access condition from the processor circuit 22 may be added to the break condition storage means 233 to set a break condition other than the execution address.

Further, two address information is added to the break condition storage means 233, and a case where the address deviates from the range determined by these two address information or enters a range determined by the two address information is detected as a break condition. May be provided, and the second comparator may be mounted in parallel with the first comparator group.

A processor that executes a plurality of instructions at the same time may be targeted for verification. In this case, the mapped processor circuit, comparator group and break signal generating means are different from the embodiment of FIG. 1 in the following points. The processor circuit executes a plurality of instructions simultaneously. A plurality of comparator groups are provided according to the number of instructions to be executed simultaneously. The break signal generation means generates a break signal when the execution address matches at least one break condition as a result of the comparison performed by the plurality of comparator groups.

Software verification means mounted on the host computer system 30 for calculating execution address and data conditions from software code and performing verification including source code verification, processor register display, and inverse conversion to assembler code. May be provided, and the software verification means may be interfaced with the verification logic mapped to the FPGA via the interface means.

Further, to the break condition of the break signal generating means 233, a stop condition in one or a plurality of instruction execution units may be added.

Further, a break condition for stopping clock generation each time the clock generation means 238 generates one or more clocks may be added to the break signal generation means 236.

Further, the first copying means 239 copies the internal information of the processor to the first memory 240 as needed, and collects the internal information of the first memory 240 at a predetermined timing and sends it to the host computer system 30. It may be transferred. The function of the I / F unit 260 is changed to the first copy unit 2
39. Thereby, the first memory 24
Instead of transferring the information via the I / F means 260 each time the information is stored in the "0", the information is transferred collectively when a predetermined amount of information is stored in the first memory 240. Thereby, transfer efficiency is improved. The transfer command is issued by the host computer system 30.

The second memory 234 stores break information sent from the interface means 26 as needed, and the second copy means 235 stores the break information stored in the second memory 234 at a predetermined timing. The information may be copied to the break condition storage means 233 in a lump. Similarly to the first copy unit 239, the function of the I / F unit 260 is replaced with the second copy unit 235 to improve the transfer efficiency.

The first memory 240 and the second memory 234 may be replaced by one memory.

A logic circuit including a plurality of processors is targeted for verification, and a processor circuit 2 is provided for each processor.
2, execution address generation means 231, first copy means 2
39, first memory 240, second memory 234, second memory
235, a break condition storage means 233, a first comparator group 232, and a second comparator are mounted, and the clock generation means 23 is shared by each processor.
8. The break signal generating means 236 and the interface means 26 may be mounted.

Further, the processor circuit 22 is replaced with an actual IC-based processor chip, and an execution address generating means mapped to the processor circuit and the FPGA by using a debug support circuit built in the processor chip. 231 may be connected.

The processor circuit 22, the logic circuit 24, the execution address generation means 231, the break condition storage means 233, the first comparator group 232, the break signal generation means 236, the interface means 26, and the clock generation means 238 are provided as one. Alternatively, it may be implemented in an emulator composed of a plurality of emulation dedicated processors.

The processor circuit 22, the logic circuit 24, the execution address generation means 231, the break condition storage means 233, the first comparator group 232, the break signal generation means 236, the interface means 26 and the clock generation means 238 May be implemented on a simulator for use.

FIG. 4 is a block diagram showing another embodiment of the present invention. In this embodiment, the clock generation means is mounted on the in-circuit board 40 as the clock generation circuit 41. Via the in-circuit interface 28 of the FPGA emulator 20, the in-circuit board 4
0 and the FPGA emulator 20 are connected. The logic circuit 42 is an IC component that cannot be mapped to the FPGA and its control circuit.

The clock generation circuit 41 is connected to the FPGA emulator 2 via the in-circuit interface 28.
The stop and restart of the clock are repeated by a stop instruction from 0 and a restart instruction (stop / restart control signal). The clock generation circuit 41 supplies a clock to the processor model 21 on the FPGA emulator 20 and the logic circuit 24 around the processor via an in-circuit interface (in-circuit I / F) 28. Also,
At the same time, the logic circuit 42 on the in-circuit board 40
Also supply the clock. Therefore, not only the circuit on the FPGA emulator 20 but also the in-circuit board 40
It is possible to control the stop and start of the clock to the logic circuit 42 above.

In the embodiment shown in FIG. 4, a processor that executes a plurality of instructions at the same time may be targeted for verification. Also in this case, the following configuration is adopted. The processor circuit executes a plurality of instructions simultaneously. A plurality of comparator groups are provided according to the number of instructions to be executed simultaneously. The break signal generation means generates a break signal when the execution address matches at least one break condition as a result of the comparison performed by the plurality of comparator groups.

[0066]

According to the present invention, the following effects can be obtained.

According to the first aspect of the present invention, the following effects can be obtained. The verification logic that depends on the processor is mapped to the FPGA in the FPGA emulator by a circuit description. As a result, it becomes possible to perform verification including software without lowering the emulation speed in the FPGA emulator which has conventionally been able to verify only the function of hardware. Further, since a part for performing hardware verification and a part for performing software verification are included in the FPGA emulator and the host computer system, the number of cable connection parts is reduced as compared with the conventional example. As a result, the occurrence of signal distortion, signal timing deviation, and the like at the connector and the soldered portion is reduced, and stable operation can be guaranteed. Further, since the hardware and software can be co-verified in one host computer system, the operability is improved.

According to the second aspect of the invention, the following effect can be obtained in addition to the effect obtained in the first aspect. When the FPGA emulator has a hardware verification function, the hardware and software can be cooperatively verified by combining the software verification according to the present invention with a break caused by an internal signal of a logic circuit or an interrupt signal to a processor.

According to the third and tenth aspects of the present invention, since the clock generation means is mounted on the in-circuit board as a clock generation circuit, verification including a logic circuit having only IC components can be performed. Further, when a break occurs, not only the supply of the clock to the circuit on the FPGA emulator but also the supply of the clock to the logic circuit on the in-circuit board is stopped. Therefore, even if the circuit is restarted after the break, the operation of all the circuits can be continued.

According to the fourth aspect of the present invention, the processor-dependent verification can be made more efficient by notifying the internal state of the processor to the host computer system via the interface means.

According to the fifth aspect of the present invention, the execution address information from the execution address generation means or the instruction information executed by the processor is stored in the general-purpose memory, and the trace information as the operation history of the processor is extracted from the general-purpose memory at the time of a break. The transfer to the host computer system enables verification based on the trace information in a verification environment on the host computer system.

According to the invention of claim 6, since the bus access condition from the processor circuit is added as a break condition to the break condition storage means, the break function can be improved.

According to the seventh aspect of the present invention, two address information are added to the break condition storing means, and a second comparator for detecting a break condition as a break condition when the address deviates from a range determined by the two address information is used as the first comparator. Implemented in parallel with groups.

According to the eighth aspect of the present invention, two address information are added to the break condition storage means, and a second comparator for detecting a case where the address falls within a range determined by the two address information as a break condition is a first comparator group. And implemented in parallel. As a result, a break function can be realized when execution shifts from a software function being executed by the processor to another function.

According to the ninth aspect of the present invention, since the processor circuit, the comparator group, and the break signal generating means are provided according to the processor which executes a plurality of instructions at the same time, the processor which executes the plurality of instructions at the same time is provided. Even the break function can be operated correctly.

According to the eleventh aspect of the present invention, since the software verification means and the verification logic mapped to the FPGA are interfaced through the interface means, both high-speed emulation and software verification can be achieved.

According to the twelfth aspect of the present invention, a stop condition in one or more instruction execution units is added to the break condition of the break signal generation means. This allows sequential verification of software each time a predetermined number of instructions are executed. In this state, it is also possible to verify the state of the hardware.

According to the thirteenth aspect, a break condition for stopping the clock generation each time the clock generation means generates one or more clocks is added to the break signal generation means. As a result, an interrupt is issued from the host computer system at regular intervals, and even if the processor does not reach the break condition due to a mistake in setting the break condition, a design error in the program or logic circuit, etc.
Emulation can be forcibly stopped from the host computer system.

According to the fourteenth aspect of the present invention, the first copy means for copying the internal information of the processor to the first memory at any time is mounted on the FPGA, and the first copy means is provided at a predetermined timing.
The internal information of the memory is collectively transferred to the host computer system. As a result, the transfer efficiency when transferring data to the host computer system can be improved.

According to the fifteenth aspect, the break information sent from the interface means as needed is stored in the second memory, and the stored break information is collectively copied to the break condition storage means. Thereby, the transfer efficiency when transferring from the host computer system can be improved.

According to the sixteenth aspect of the present invention, the first memory and the second memory are replaced by one memory, so that effective use of memory resources can be realized.

According to the seventeenth aspect of the present invention, since the verification logic of the multiprocessor is mapped to the FPGA, the verification depending on a plurality of processors can be realized at the same time.

According to the eighteenth to twentieth aspects of the present invention, the software verification can be executed not only by the FPGA but also by the processor chip, the emulation processor and the logic circuit simulator.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing one embodiment of the present invention.

FIG. 2 is a main part configuration diagram of the system of FIG. 1;

FIG. 3 is a configuration diagram showing another embodiment of the present invention.

FIG. 4 is a configuration diagram showing another embodiment of the present invention.

FIG. 5 is a diagram showing a configuration example of a conventional verification support system.

FIG. 6 is a diagram showing another configuration example of a conventional verification support system.

[Explanation of symbols]

 20 FPGA emulator 22, 22A, 22B Processor circuit 23A, 23B Processor specific I / F means 26 I / F means 27 Common I / F means 28 In-circuit I / F 30 Host computer system 40 In-circuit board 41 Clock generation circuit 231 Execution Address generation means 232 First comparator group 233 Break condition storage means 234 Second memory 235 Second copy means 236 Break signal generation means 237 Timer 238 Clock generation means 239 First copy means 240 First memory

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G06F 17/50 664 G01R 31/28 F G06F 11/26 310

Claims (20)

[Claims] 1. A verification support system for performing verification of a target logic circuit including a processor on an FPGA emulator, wherein verification logic dependent on the processor is mapped to an FPGA in the FPGA emulator by a circuit description. Verification support system. 2. A verification support system for executing verification of a target logic circuit including a processor on an FPGA emulator, comprising: a processor circuit that can be mapped to an FPGA of the FPGA emulator; and a processor included in the logic circuit in the target logic circuit. An execution address generation means for generating an address to be executed by the processor by combining one or a plurality of internal signals from a logic circuit which is a logic circuit other than the circuit, and a logic circuit of the processor circuit; A break condition storing means for holding one or more break conditions for verifying the condition, a first comparator group for comparing an execution address generated by the execution address generating means with the condition held by the break condition storing means, This first comparator As a result of the group comparison, a break signal generating means for generating a break signal when the execution address matches at least one break condition; and receiving a break signal from the break signal generating means;
Interface means for notifying the host computer system and notifying the information sent from the host computer system to the FPGA emulator, and supplying a clock to the processor circuit and the logic circuit;
A clock generation means for stopping the clock supply to the processor circuit and the logic circuit when the break signal generation means generates the break signal, and for re-supplying the clock in response to a restart instruction from the host computer system. A verification support system characterized by mapping to 3. The circuit according to claim 2, wherein said clock generation means is mounted on an in-circuit board as a clock generation circuit, and the in-circuit board and the FPGA emulator are connected via an in-circuit interface of the FPGA emulator. Verification support system described. 4. The verification support system according to claim 2, wherein an internal state of the processor is notified to the host computer system via the interface means. 5. A general-purpose memory defined in an FPGA emulator, and a counter indicating an address of the general-purpose memory,
At least one of the execution address information from the execution address generation means and the instruction information executed by the processor is stored in the general-purpose memory, and at the time of a break, trace information, which is the operation history of the processor, is extracted from the general-purpose memory and transferred to the host computer system The verification support system according to claim 2 or 3, wherein: 6. The verification support system according to claim 2, wherein a bus access condition from said processor circuit is added as a break condition to said break condition storage means. 7. A method according to claim 2, wherein two pieces of address information are added to said break condition storing means, and a case where the address information is out of a range determined by these two pieces of address information is detected as a break condition.
4. The verification support system according to claim 2, wherein said comparator is mounted in parallel with said first comparator group. 8. A second comparator which adds two pieces of address information to the break condition storage means and detects a case where the address falls within a range determined by the two pieces of address information as a break condition in parallel with the first comparator group. The verification support system according to claim 2 or 3, wherein the verification support system is implemented. 9. A verification support system for executing verification of a target logic circuit including a processor on an FPGA emulator, comprising: a processor circuit that can be mapped to an FPGA in the FPGA emulator and executes a plurality of instructions simultaneously; By combining one or more internal signals from a logic circuit, which is a logic circuit other than the processor circuit in a certain logic circuit, and a logic circuit of the processor circuit, the execution addresses are respectively assigned to instructions simultaneously executed by the processor. Execution address generation means for generating, break condition storage means specified by the host computer system and holding one or more conditions for performing software verification, a plurality of break address storage means provided in accordance with the number of instructions to be executed simultaneously, Execution address generated by generation means A plurality of comparator groups for comparing the conditions held by the break condition storage means; and a break signal generating means for generating a break signal when an execution address matches at least one break condition as a result of the comparison by the plurality of comparator groups. Receiving a break signal from the break signal generating means,
Notify the host computer system and send the information sent from the host computer system to the FP
Interface means for notifying the GA emulator, and a clock supplied to the processor circuit and its peripheral circuits;
Clock generation means for stopping the clock to the processor circuit and its peripheral circuits when the break signal generation means generates the break signal, and re-supplying the clock in response to a restart instruction from the host computer system; A verification support system characterized by mapping. 10. An FPGA, wherein the clock generation means is mounted on an in-circuit board as a clock generation circuit.
10. The verification support system according to claim 9, wherein the in-circuit board and the FPGA emulator are connected via an in-circuit interface of the emulator. 11. A software verification unit mounted on a host computer system, which calculates execution address and data conditions from software code and performs verification including source code verification, processor register display, and inverse conversion to assembler code. 4. The device according to claim 2, wherein the interface unit interfaces the software verification unit and the verification logic mapped to the FPGA via the interface unit.
Verification support system described. 12. The verification support system according to claim 2, wherein a stop condition in one or a plurality of instruction execution units is added to a break condition of said break signal generation means. 13. The break signal generating means according to claim 2, wherein a break condition for stopping clock generation every time the clock generating means or the clock generating circuit generates one or more clocks is added to said break signal generating means. Item 3. The verification support system according to Item 3. 14. A first copy unit for copying internal information of the processor to a first memory as needed by an FPGA
4. The verification support system according to claim 2, wherein the verification support system is mounted on an emulator and collectively transfers internal information of the first memory to a host computer system at a predetermined timing. 15. A second memory for storing break information sent from the interface means as needed, and a second memory for collecting the break information stored in the second memory at a predetermined timing and copying the break information to the break condition storage means. 2
4. The verification support system according to claim 2, wherein the copying means is mapped to an FPGA emulator. 16. The memory according to claim 1, wherein the first memory and the second memory are 1
16. The verification support system according to claim 14, wherein one memory is substituted. 17. A logic circuit including a plurality of processors is to be verified, and the processor circuit, the execution address generation unit, the break condition storage unit, and the first comparator group are mounted on each processor, and are commonly used for each processor. 4. The verification support system according to claim 2, wherein said clock generation means or clock generation circuit, break signal generation means, and interface means are mounted. 18. An execution address generating means mapped to the processor circuit and the FPGA by using the debug support circuit built in the processor chip by replacing the processor circuit with an actual IC processor chip. The verification support system according to claim 2, wherein the verification support system is connected. 19. One or more of the processor circuit, logic circuit, execution address generation means, break condition storage means, first comparator group, break signal generation means, interface means, and clock generation means or clock generation circuit. 4. The verification support system according to claim 2, wherein the verification support system is mounted on an emulator configured by a plurality of emulation-dedicated processors. 20. The processor circuit, the logic circuit,
An execution address generation unit, a break condition storage unit, a first comparator group, a break signal generation unit, an interface unit, and a clock generation unit or a clock generation circuit are mounted on a logic circuit simulator. The verification support system according to claim 2 or 3.