CN111028878B

CN111028878B - Flash memory writing method, flash memory chip and nonvolatile storage device

Info

Publication number: CN111028878B
Application number: CN201911149761.2A
Authority: CN
Inventors: 张吉兴; 武艺; 李东起; 杨亚飞; 李卫军
Original assignee: Shenzhen Dapu Microelectronics Co Ltd
Current assignee: Shenzhen Dapu Microelectronics Co Ltd
Priority date: 2019-11-21
Filing date: 2019-11-21
Publication date: 2021-07-30
Anticipated expiration: 2039-11-21
Also published as: CN111028878A

Abstract

The embodiment of the invention relates to the field of storage equipment application, and discloses a flash memory writing method, a flash memory chip and non-volatile storage equipment, wherein the flash memory writing method comprises the steps of setting a corresponding state flag bit for each bit line, and acquiring target bit values of all storage units in at least one word line; performing voltage pulse, and reading the current bit values of all the memory cells in at least one word line; determining a storage unit with the current bit value identical to the target bit value, and setting a state flag bit corresponding to the storage unit with the current bit value identical to the target bit value as a disconnection flag; and repeating the voltage pulse on all the memory cells in the at least one word line until the current bit value of each memory cell in the at least one word line is the same as the target bit value, and setting the state flag bits of all the memory cells in the at least one word line as the conducting flags. Through the mode, the embodiment of the invention can reduce the power consumption of the flash memory chip during writing.

Description

Flash memory writing method, flash memory chip and nonvolatile storage device

Technical Field

The present invention relates to the field of storage device applications, and in particular, to a flash memory writing method, a flash memory chip, and a nonvolatile storage device.

Background

Solid State Drives (SSD), which are hard disks made of Solid State electronic memory chip arrays, include control units and memory units (FLASH memory chips and DRAM memory chips), while the Solid State disks using NAND FLASH memory media to store data occupy higher and higher positions in the services of servers and data centers, the interface speed of the interaction between the Solid State disks and the host is faster and faster, the theoretical speed of the SATA interface is gradually upgraded to 4GB/s of the current mainstream PCIe third-generation interface, however, the single channel performance of the FLASH memory chips is not substantially improved, in order to match the speed of the FLASH memory and the interface, the general main control design of the Solid State disks is a multi-channel design, i.e. a plurality of FLASH memory chips are made to work in parallel, the number advantage makes up the disadvantage of the single channel performance, the parallel work of N channels can improve the performance to N times of the single channel, only the number of channels need to be superimposed to solve the flash performance problem theoretically.

However, in practical situations, when multiple channels work together, the power consumption of the channels inevitably increases linearly, and when the number N of the channels increases, the working power consumption of the entire SSD also increases linearly.

Based on this, there is a need for improvement in the art.

Disclosure of Invention

Embodiments of the present invention are directed to a flash memory writing method, a flash memory chip, and a non-volatile memory device, which can reduce power consumption of flash memory writing.

In order to solve the above technical problems, embodiments of the present invention provide the following technical solutions:

in a first aspect, an embodiment of the present invention provides a flash memory writing method applied to a nonvolatile memory device, where the nonvolatile memory device includes a plurality of word lines and a plurality of bit lines, each word line is composed of a plurality of memory cells, and each bit line corresponds to a unique memory cell in the word line, the method includes:

setting a corresponding state flag bit for each bit line, wherein the state flag bit comprises a conducting flag and a disconnecting flag;

acquiring target bit values of all memory cells in the at least one word line;

performing voltage pulse on the memory cell of which the state flag bit in the at least one word line is a conducting flag, and reading the current bit value of the memory cell of which the state flag bit in the at least one word line is the conducting flag;

determining a storage unit with the current bit value identical to the target bit value, and setting a state flag bit corresponding to the storage unit with the current bit value identical to the target bit value as a disconnection flag;

repeatedly carrying out voltage pulse on the memory cells of which the status flag bits are the conducting flags in the at least one word line until the current bit value of each memory cell in the at least one word line is the same as the target bit value;

and setting the state flag bits of all the memory cells in the at least one word line as a conducting flag.

In some embodiments, the setting a corresponding status flag bit for each bit line includes:

and arranging a corresponding state marking component for each bit line, wherein the state marking component comprises a conducting state and a disconnecting state, the conducting state corresponds to the conducting mark of the state marking bit, and the disconnecting state corresponds to the disconnecting mark of the state marking bit.

In some embodiments, the voltage pulsing all of the memory cells in the at least one word line to read the current bit values of all of the memory cells in the at least one word line includes:

acquiring the current voltage value of any memory cell in the at least one word line;

determining the voltage state of the storage unit according to the current voltage value;

and determining the current bit value of the memory cell according to the voltage state of the memory cell.

In some embodiments, before the step of performing a voltage pulse on the memory cell whose status flag bit is a turn-on flag in the at least one word line, and reading the current bit value of the memory cell whose status flag bit is a turn-on flag in the at least one word line, the method further comprises:

all memory cells in the at least one word line are set to an initial state in advance.

In some embodiments, the method further comprises:

caching target bit values of all memory cells in at least one wordline of the non-volatile memory device.

In a second aspect, an embodiment of the present invention provides a flash memory writing apparatus applied to a nonvolatile memory device, where the nonvolatile memory device includes a plurality of word lines and a plurality of bit lines, each word line is composed of a plurality of memory cells, and each bit line corresponds to a unique memory cell in the word line, the apparatus includes:

the state flag setting unit is used for setting a corresponding state flag for each bit line, and the state flag comprises a conducting flag and a disconnecting flag;

a target bit value acquisition unit configured to acquire target bit values of all memory cells in the at least one word line;

a current bit value obtaining unit, configured to perform voltage pulse on the memory cell whose state flag bit in the at least one word line is the conducting flag, and read a current bit value of the memory cell whose state flag bit in the at least one word line is the conducting flag;

a state flag bit changing unit, configured to determine a memory cell with a current bit value that is the same as the target bit value, and set a state flag bit corresponding to the memory cell with the current bit value that is the same as the target bit value as a disconnection flag;

a bit value judging unit, configured to repeatedly perform voltage pulse on the memory cell whose status flag bit is a conducting flag in the at least one word line until a current bit value of each memory cell in the at least one word line is the same as the target bit value;

and the state flag bit resetting unit is used for setting the state flag bits of all the memory cells in the at least one word line to be the conducting flags.

In some embodiments, the status flag setting unit is specifically configured to:

In some embodiments, the current bit value obtaining unit is specifically configured to:

In some embodiments, the apparatus further comprises:

and the preset unit is used for setting the current bit values of all the memory cells in the at least one word line as high-level signals in advance.

In some embodiments, the apparatus further comprises:

a buffer unit for buffering target bit values of all memory cells in at least one word line of the non-volatile memory device.

In a third aspect, an embodiment of the present invention provides a flash memory chip, including:

a plurality of wafers, each wafer comprising a plurality of groupings, each grouping comprising a plurality of physical blocks, each physical block comprising a plurality of physical pages;

the physical page comprises a plurality of storage units, control gates of the storage units are connected to form word lines, sources and drains of the storage units are connected to form bit lines, and each bit line is provided with a state flag component.

In some embodiments, the flash memory chip further comprises:

and the buffer is used for buffering the target bit values of all the memory cells in at least one word line.

In some embodiments, the status flag component may be: semiconductor diode and/or semiconductor triode and/or MOS tube and/or transistor.

In some embodiments, the flash memory chip may be an SLC flash memory chip or an MLC flash memory chip or a TLC flash memory chip or a QLC flash memory chip.

In a fourth aspect, an embodiment of the present invention provides a nonvolatile memory device, including:

the flash memory chip described above;

a flash memory controller, the flash memory controller comprising:

at least one processor; and the number of the first and second groups,

a memory communicatively coupled to the at least one processor; wherein the content of the first and second substances,

the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the flash memory writing method described above.

In a fifth aspect, the present invention also provides a non-volatile computer-readable storage medium, where the computer-readable storage medium stores computer-executable instructions for enabling a non-volatile storage device to execute the flash memory writing method described above.

The embodiment of the invention has the beneficial effects that: in contrast to the prior art, an embodiment of the present invention provides a flash memory writing method applied to a nonvolatile memory device, where the nonvolatile memory device includes a plurality of word lines and a plurality of bit lines, each word line is composed of a plurality of memory cells, and each bit line corresponds to a unique memory cell in the word line, the method includes: setting a corresponding state flag bit for each bit line, wherein the state flag bit comprises a conducting flag and a disconnecting flag; acquiring target bit values of all memory cells in the at least one word line; performing voltage pulse on the memory cell of which the state flag bit in the at least one word line is a conducting flag, and reading the current bit value of the memory cell of which the state flag bit in the at least one word line is the conducting flag; determining a storage unit with the current bit value identical to the target bit value, and setting a state flag bit corresponding to the storage unit with the current bit value identical to the target bit value as a disconnection flag; repeatedly carrying out voltage pulse on the memory cells of which the status flag bits are the conducting flags in the at least one word line until the current bit value of each memory cell in the at least one word line is the same as the target bit value; and setting the state flag bits of all the memory cells in the at least one word line as a conducting flag. By adding a status flag bit to the word line, the write operation and the read operation of the memory cell are reduced, and the power consumption of the flash memory chip during writing can be reduced.

Drawings

One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the figures in which like reference numerals refer to similar elements and which are not to scale unless otherwise specified.

Fig. 1 is a schematic structural diagram of a solid state disk according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a flash memory multichannel according to an embodiment of the present invention;

FIG. 3 is a schematic structural diagram of a memory cell according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of voltage distributions of memory cells of an MLC flash memory chip according to an embodiment of the invention;

FIG. 5 is a diagram illustrating a writing method of a memory cell according to an embodiment of the present invention;

FIG. 6 is a diagram illustrating a writing scheme of a plurality of memory cells according to the prior art;

FIG. 7 is a diagram illustrating a writing method for a plurality of memory cells according to an embodiment of the present invention;

FIG. 8 is a flowchart illustrating a flash memory writing method according to an embodiment of the present invention;

FIG. 9 is a detailed flowchart of step S30 in FIG. 8;

fig. 10 is a schematic structural diagram of a flash memory writing device according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.

In embodiments of the present invention, the Non-Volatile Memory device is comprised as a Non-Volatile Memory device with a write mechanism, and Non-Volatile Memory (NVM) is a general term for all forms of solid-state (no moving parts) Memory, which does not have to refresh Memory contents periodically. This includes all forms of Read-Only Memory (ROM), such as: programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Flash Memory (Flash Memory), and battery-powered Random Access Memory (RAM).

Specifically, the embodiment of the present invention is explained by using a nonvolatile storage device as a Solid State Drive (SSD), and the method is further explained with reference to the drawings.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a solid state disk according to an embodiment of the present invention;

as shown in fig. 1, the solid state disk 10 includes: the flash memory controller 11 is connected with the flash memory chip 12;

specifically, the flash memory controller 11 includes: one or more processors 111, and memory 112. In fig. 1, one processor 111 is taken as an example.

The processor 111 and the memory 112 may be connected by a bus or other means, such as the bus connection shown in fig. 1.

The memory 112, which is a non-volatile computer-readable storage medium, may be used to store non-volatile software programs, non-volatile computer-executable programs, and modules. The processor 111 executes various functional applications and data processing of the flash memory writing method of the embodiment of the present invention by executing nonvolatile software programs, instructions, and modules stored in the memory 112.

The memory 112 may include high speed random access memory and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some embodiments, the memory 112 may optionally include memory located remotely from the processor 111, which may be connected to the processor 111 via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof. The modules are stored in the memory 112 and, when executed by the one or more processors 111, perform a garbage collection method based on block classification in an embodiment of the present invention.

Specifically, the flash memory chip 12 includes a plurality of wafers (die), each wafer is composed of a plurality of groups (planes), each group is composed of a plurality of blocks (blocks), that is, a physical block (block), wherein a block is a basic unit for erasing the flash memory chip 12, each block has a plurality of pages (pages), that is, a physical page, and a physical page (page) is a basic unit for reading and writing the flash memory chip 12, wherein the flash memory operation of the solid state disk uses a flash memory page (page) as a reading and writing unit, and a flash memory block (block) as an erasing unit, and a plurality of levels of parallelism such as a channel (channel), a particle package (package), a particle (die), and a flash memory chip (plane) are provided for medium access inside the device. The device comprises a plurality of flash memory grain packages, wherein each grain package comprises two or more flash memory grains, each grain can be independently selected to execute the instruction. Flash memory devices take full advantage of the access capabilities of the media by executing multiple levels of instructions in parallel.

The size of a Solid State Drive (SSD) capacity depends on the number of NAND flash memory granules in the SSD and the storage capacity of each granule. Among them, the solid state disk mostly adopts a Multi-Channel (Multi-Channel) architecture, an 8-bit (8-bit) bus is called a Channel (Channel), and operations on a Channel can be Interleaved (Interleaved). When one NAND flash memory is in an occupied state Busy, the first NAND flash memory can be Busy, the master can access a second NAND flash memory on the same channel, for example, the master needs to continuously Write (Write) all the NAND flash memories on one channel, with the help of an Interleave function, the NAND flash memories on the same channel form a Pipeline (Pipeline) with the maximum channel utilization rate, and when the Write operation is executed in the NAND flash memories, the channel is in an idle state, so that the other NAND flash memories can be continuously operated. At a certain flash write time (programtime), the data throughput (throughput) of the SSD rises greatly as the number of NAND flash memories increases.

The physical page is composed of a plurality of memory cells (cells), each memory cell stores data with a fixed number of bits, and the flash memory chip 12 may be an SLC flash memory chip, an MLC flash memory chip, a TLC flash memory chip, or a QLC flash memory chip, for example:

if the flash memory chip 12 is a Single-Level Cell (SLC) flash memory chip, each memory Cell stores 1bit of information, that is, only two voltage changes, i.e., 0 and 1;

if the flash memory chip 12 is an MLC flash memory chip (MLC), each memory Cell stores 2-bit information, and there are four voltage changes of 00,01,10, and 11, and at this time, more complicated voltage control is required compared with the SLC flash memory chip;

if the flash memory chip 12 is a TLC flash memory chip (TLC), each memory Cell stores 3-bit information, and there are eight voltage changes of 000, 001,010,011,100,101,110, 111;

if the flash memory chip 12 is a QLC flash memory chip (Quad-Level Cell, QLC), each memory Cell stores 4bit information, and there are sixteen voltage variations 0000, 0001,0010,0011,0100,0101,0110,0111, 1000,1001,1010,1011,1100,1101,1110, 1111.

In the embodiment of the present invention, the flash memory chip 12 is an MLC flash memory chip (MLC) for example.

Referring to fig. 2 again, fig. 2 is a schematic diagram of a flash memory multichannel according to an embodiment of the present invention;

as shown in fig. 2, when the flash controller sends a command to the flash memory chip, since one flash memory chip may encapsulate a plurality of channels, since the plurality of channels operate in parallel, when the number of channels operating in parallel is large, each channel may generate extremely high power consumption within the first tens of nanoseconds, and the instantaneous power consumption of each channel can be added, as the number N of channels increases, the sum of the instantaneous power consumptions of the plurality of channels is large, which may easily result in the instantaneous power consumption of the entire flash memory chip being high, and the high instantaneous power consumption may cause the ambient temperature to exceed the normal operating temperature range of the flash memory chip.

Since various components of the SSD are integrated on the circuit board in a high-density manner, and each component has a strict normal operating temperature range, for example, the operating temperature range of a consumer-grade flash memory chip is generally 0 to 70 degrees celsius, and if the operating temperature range exceeds this range, the normal function of the flash memory chip cannot be guaranteed, so that when the number N of channels is larger and larger, the sum of instantaneous power consumption always exceeds 70 degrees celsius.

Referring to fig. 3, fig. 3 is a schematic structural diagram of a memory cell according to an embodiment of the invention;

as shown in fig. 3, the memory cell includes a control gate, a floating gate and a substrate, wherein an oxide is filled between the control gate and the floating gate, and a tunnel oxide is filled between the floating gate and the substrate, wherein the bottom layer of the memory cell for storing data is based on the principle that applying a relatively high voltage to the control gate can make electrons pass through the tunnel oxide from the substrate to the floating gate, and then the electrons are stored in the floating gate.

Referring to fig. 4 again, fig. 4 is a schematic diagram illustrating voltage distributions of memory cells of an MLC flash memory chip according to an embodiment of the present invention;

as shown in fig. 4, each memory Cell of the MLC flash memory chip stores 2-bit data, and the 2-bit permutation has four states, so that the stored data is represented by four voltage state distributions, the larger the amount of electrons injected into the floating gate, the larger the voltage of the Cell, and vice versa, the erase state in fig. 3 represents storing '11' data (initial state), state a represents storing '01' data, state B represents storing '00' data, and state C represents storing '10' data.

Referring to fig. 5 again, fig. 5 is a schematic diagram illustrating a writing method of a memory cell according to an embodiment of the invention;

as shown in fig. 5, the MLC flash memory chip in the present invention adopts a 2-shot write mode, that is, writing twice, the first write operation raises the voltage of the memory cell from the erased state to the state a through multiple voltage pulses (during which the voltages on all the memory cells need to be read after each voltage pulse to determine whether the voltage reaches the threshold voltage V _ a), the second write operation raises the voltage of the memory cell from the state a to the state B or C through multiple voltage pulses (during which the voltages on all the memory cells need to be read after each voltage pulse to determine whether the voltage reaches the threshold voltage V _ B or V _ C), and the internal logic of the flash memory chip automatically implements the above-mentioned write process according to the target threshold voltage of the memory cell (determined by the target bit value of the data written into the memory cell by the user).

Referring to FIG. 6, FIG. 6 is a diagram illustrating a writing method of a plurality of memory cells according to the prior art;

as shown in fig. 6, control gates of a plurality of memory cells are connected to form a Word line (Word line), sources and drains of the memory cells are connected to form a Bit line (Bit line), and in the write operation, a high voltage (about 20V) is applied to the control gate of the Word line (Word line), and a memory cell to be written (the voltage needs to be shifted to the right) is selected by the Bit line (Bit line), and the write operation, that is, a voltage pulse is performed to inject electrons. It should be noted that, in order not to cause the overshoot phenomenon (the actually injected electrons of the Cell exceed the expected number), only a little electrons are injected in each voltage pulse, then the actual voltages of all the memory cells on the whole Word line (each Bit line is added with about 1V), and compared with the expected threshold voltage, those memory cells whose actual voltages have reached the expected threshold voltage do not need to perform the next voltage pulse, and then perform the next voltage pulse on the memory cells which have not reached the expected threshold voltage.

For example, assuming that a Word line of the MLC flash memory is composed of 10 cells, a user needs to write 20 target bit values '10010011101001001111' into the flash memory, and the flash memory chip first temporarily stores these target bit values into an internal Buffer Page Buffer (which may be a cache memory inside the flash memory chip), it can be understood that the Buffer is essentially a Random Access Memory (RAM) with a physical Page size, and data written by the user is firstly buffered into the Buffer and then programmed into a certain physical Page of the flash memory, and by setting the Buffer, the speed and performance of data writing can be improved. As shown in fig. 6, assuming that they are written into Word line0 (the initial state of each Cell in Word line0 is an erased state, i.e. data '11' is stored), the writing process is as follows:

step1, reading the actual initial voltage states of all cells in the Word line0 by the flash memory chip, wherein the actual initial voltage states are '1111111111111111111111';

step2, comparing the read actual value with the expected value, and finding that the actual voltage on

Cell

3,8,9 is equal to the expected value voltage, then the next write operation does not select

Cell

3,8, 9;

and Step3, performing voltage pulse on cells except

cells

3,8 and 9 on Word line0 according to the result of Step2, comparing the actual voltage reading of all the cells on Word line0 with the expected value after each voltage pulse, and if the actual voltage of a certain Cell is equal to the expected value voltage, not selecting the Cell (similar to Step 2) by the next voltage pulse until the actual voltage of all the cells is equal to the expected value voltage.

As can be seen from the above-mentioned writing process, the writing of one Word line (Word line) is divided into multiple voltage pulses and multiple read voltages, wherein the subsequent voltage pulses are not performed on the memory cells that have reached the desired voltage value, but the subsequent read voltage operation needs to be performed on all the memory cells, and although the voltage for reading the memory cells only needs to add a small amount of voltage to the Bit line (Bit line), the voltage is more than a few, and when the number of read operations is larger, the power consumption is wasted.

Based on the above problems, embodiments of the present invention provide a new flash memory writing method to reduce the waste of power consumption.

Referring to fig. 7, fig. 7 is a schematic diagram illustrating a writing method of a plurality of memory cells according to an embodiment of the present invention;

for the write process in the prior art, the embodiment of the present invention reduces the power consumption by reducing the number of read operations, and specifically, as shown in fig. 7, adds a status flag component to each Bit line (Bit line), and identifies whether the memory cell of the Bit line (Bit line) corresponding to the status flag component reaches an expected voltage value, so as to determine whether to perform a read operation on the memory cell. In the embodiment of the present invention, the status flag component can implement on and off functions, including but not limited to: the circuit device has an on state and an off state, such as a semiconductor diode and/or a semiconductor triode and/or a MOS transistor and/or a field effect transistor.

Specifically, referring to fig. 8 again, fig. 8 is a schematic flow chart of a flash memory writing method according to an embodiment of the present invention;

as shown in fig. 8, the flash memory writing method is applied to a nonvolatile memory device, where the nonvolatile memory device includes a plurality of word lines and a plurality of bit lines, each word line includes a plurality of memory cells, and each bit line corresponds to a unique memory cell in the word line, and includes:

step S10: setting a corresponding state flag bit for each bit line, wherein the state flag bit comprises a conducting flag and a disconnecting flag;

specifically, a status flag Bit corresponding to each Bit line (Bit) is set, where the status flag Bit is used to indicate whether the Bit line (Bit line) needs to be turned on, and if a memory cell (cell) on the Bit line (Bit line) does not reach an expected voltage in a writing process of a Word line (Word line), the status flag Bit is set as a turn-on flag, and if a memory cell (cell) on the Bit line (Bit line) reaches an expected voltage in a writing process of a Word line (Word line), the status flag Bit is set as a turn-off flag, for example: the method comprises the steps that a state mark component corresponding to each Bit line (Bitline) is arranged for each Bit line (Bitline), the state mark component comprises a conducting state and a disconnecting state, the conducting state corresponds to a conducting mark of the state mark Bit, the disconnecting state corresponds to a disconnecting mark of the state mark Bit, if a storage unit (cell) on the Bit line (Bit line) does not reach an expected voltage in the writing process of a certain Word line (Word line), the state of the state mark component is the conducting state, the state is equivalent to the conducting mark, if the storage unit (cell) on the Bit line (Bit line) reaches the expected voltage in the writing process of the certain Word line (Word line), the state of the state mark component is the disconnecting state, and the state mark Bit is equivalent to the disconnecting mark.

Step S20: acquiring target bit values of all memory cells in the at least one word line;

specifically, the flash memory controller receives storage data sent by a host, and the flash memory controller obtains target bit values of all storage units in the at least one word line according to the storage data sent by the host, for example: taking an example where one word line includes ten memory cells, the target bit value is '10010011101001001111'.

Step S30: performing voltage pulse on the memory cell of which the state flag bit in the at least one word line is a conducting flag, and reading the current bit value of the memory cell of which the state flag bit in the at least one word line is the conducting flag;

specifically, before the step of performing a voltage pulse on the memory cell with the status flag bit of the at least one word line as the conducting flag and reading the current bit value of the memory cell with the status flag bit of the at least one word line as the conducting flag, the method further includes: all the memory cells in the at least one word line are set to an initial state in advance, which is equivalent to that all the memory cells in the at least one word line are in the initial state, and the initial state is an erased state, that is, all the memory cells store data of '11', that is, all the memory cells store high-level signals.

It can be understood that after the memory cell is written with data, the state of the memory cell changes, taking an MLC flash memory chip as an example, the state of the memory cell includes: the memory cell comprises an initial state, a state A, a state B and a state C, wherein data corresponding to the initial state is '11', data corresponding to the state A is '01', and data corresponding to the state B is '10', and at this time, the state of the memory cell needs to be read, namely, the data stored in the memory cell needs to be read.

Reading the current voltage value of each memory cell in each word line is equivalent to reading the data currently stored in each memory cell in each word line, such as: the data stored in a certain memory cell is '01'.

Referring to fig. 9, fig. 9 is a detailed flowchart of step S30 in fig. 8;

as shown in fig. 9, the performing a voltage pulse on the memory cell whose status flag bit in the at least one word line is a turn-on flag to read the current bit value of the memory cell whose status flag bit in the at least one word line is a turn-on flag includes:

step S31: acquiring the current voltage value of any memory cell in the at least one word line;

specifically, reading the current voltage values of all the memory cells in the at least one word line, that is, reading the actual voltages of all the memory cells in the at least one word line, it can be understood that reading the voltage values of the memory cells requires applying a certain voltage to each bit line, for example: reading the voltage value of a memory cell requires applying a voltage of around 1V to each bit line.

Step S32: determining the voltage state of the storage unit according to the current voltage value;

specifically, referring to fig. 5 again, fig. 5 is a schematic diagram of voltage states of an MLC flash memory chip, which has four voltage states, and determines whether the current voltage value is greater than or equal to a preset voltage threshold according to the current voltage value of the memory cell, that is, an actual voltage, and if the current voltage value is greater than or equal to the preset voltage threshold, the memory cell is determined to be in a voltage state corresponding to the preset voltage threshold, for example: the preset voltage threshold includes a first voltage threshold, a second voltage threshold and a third voltage threshold, the first voltage threshold corresponding to the state a is V _ a, the second voltage threshold corresponding to the state B is V _ B, and the third voltage threshold corresponding to the state C is V _ C, where the first voltage threshold V _ a < the second voltage threshold V _ B < the third voltage threshold V _ C, it can be understood that, since the voltage of the memory cell is increased by a certain voltage every time a voltage pulse is applied, the increased voltage is not too large, and therefore, a situation that an actual voltage of the memory cell is greater than the third voltage threshold V _ C due to one voltage pulse does not occur, and therefore, the voltage state of the memory cell can be determined by determining the actual voltage of the memory cell in a stepwise manner, for example: if the current voltage value of the memory cell is greater than or equal to the first voltage threshold value V _ a, the memory cell is determined to be in a state A, if the current voltage value of the memory cell is greater than or equal to the second voltage threshold value V _ B, the memory cell is determined to be in a state B, and if the current voltage value of the memory cell is greater than or equal to the third voltage threshold value V _ C, the memory cell is determined to be in a state C.

It can be understood that when the flash memory chip is an SLC flash memory chip, there are two voltage states, when the flash memory chip is a TLC flash memory chip, there are eight voltage states, and when the flash memory chip is a QLC flash memory chip, there are sixteen voltage states, which have a similar principle to that of an MLC flash memory chip and are not described herein again.

Step S33: and determining the current bit value of the memory cell according to the voltage state of the memory cell.

Specifically, each voltage state corresponds to a unique bit value, for example: the bit value corresponding to the erase state (initial state) is '11', the bit value corresponding to the state a is '01', the bit value corresponding to the state B is '00', and the bit value corresponding to the state C is '10', and the current bit value of the memory cell can be determined by determining the voltage state of the memory cell.

Because each bit line corresponds to a status flag bit, and the status of the memory cell corresponding to the bit line with the status flag bit in the off state is set to be unchangeable and unreadable, only the current bit value of the memory cell with the status flag bit in the at least one word line as the on flag needs to be read, and by only reading the current bit value of the memory cell with the status flag bit as the on flag, unnecessary power consumption caused by reading the memory cell with the status flag bit as the off flag can be avoided, thereby reducing the power consumption of the flash memory chip.

Step S40: determining a storage unit with the current bit value identical to the target bit value, and setting a state flag bit corresponding to the storage unit with the current bit value identical to the target bit value as a disconnection flag;

specifically, comparing the current bit value of all the memory cells of the word line with the corresponding target bit value, if the current bit value of a certain memory cell of the word line is the same as the corresponding target bit value, setting the status flag bit of the bit line corresponding to the memory cell to be in an off state, which is equivalent to setting the memory cell to be in the off state, and the bit line in the off state will not be written with data or read data, so as to achieve the purpose of reducing power consumption; it can be understood that if the current bit value of a certain memory cell of the word line is different from the corresponding target bit value, the status flag bit of the bit line corresponding to the memory cell is kept in the on state to write data or read its stored data, for example: referring to fig. 7, assuming that the target Bit values of all the memory cells of the word line are '10, 01,00,11,10,10,01,00,11, 11', and the current Bit values of all the memory cells of the word line are '11, 01,00,11,10,10,01,00,11, 10', the current Bit values of the memory cells corresponding to Bit line0 and Bit line9, that is, the memory data thereof is different from the target Bit values, are determined by comparison, and at this time, the states of the state flag elements corresponding to Bit line0 and Bit line9 need to be set to an on state, and the current Bit values of the memory cells corresponding to Bit line1 to Bit line8 are the same as the target Bit values, and at this time, the states of the state flag elements corresponding to Bit line1 to Bit line8 are set to an off state.

Step S50: judging whether the current bit value of each storage unit in at least one word line is the same as the target bit value;

specifically, by determining whether the current bit value of each memory cell in at least one word line is the same as the target bit value, if yes, it is determined that the data writing is completed, and the current bit values of all the memory cells are set as the target bit values, at this time, the process proceeds to step S60: setting the state flag bits of all the memory cells in the at least one word line to a conducting state; if not, the process returns to step S30: and performing voltage pulse on all the storage units in the at least one word line, reading the current bit values of all the storage units in the at least one word line, repeating the voltage pulse on the storage units of which the state flag bits are the conducting flags in the at least one word line until the current bit value of each storage unit in the at least one word line is the same as the target bit value, and repeating the voltage pulse on the storage units which do not reach the preset voltage threshold value until all the storage units in the at least one word line reach the preset voltage threshold value.

Step S60: and setting the state flag bits of all the memory cells in the at least one word line as a conducting flag.

Specifically, after data writing to all memory cells of the at least one word line is completed, setting status flag bits of all memory cells in the at least one word line as a conducting flag, wherein if the status flag element is in a conducting state, after a subsequent voltage pulse, when a memory cell (cell) voltage is read, the flash memory chip can add a voltage to the Bit line (Bit line), that is, can read a voltage value of the memory cell (cell); when the voltage value of the memory cell (cell) on the Bit line (Bit line) does not reach the expected voltage in the writing process of a Word line (Word line), the flash memory chip does not perform subsequent voltage pulse on the memory cell (cell) any more after the voltage value of the memory cell (cell) is equal to the expected voltage, namely the voltage value of the memory cell (cell) is not changed, the state flag component is set to be in an off state, and the Bit line (Bit line) cannot be conducted due to the off state in the subsequent reading operation, namely power consumption cannot be generated, so that the purpose of saving energy is achieved. After all the memory cells (cells) on the Word line (Word line) are written, the status flag devices on all the Bit lines (Bit line) are set to be in a conducting state, so that the subsequent read command can be executed.

The flash memory write process of the present invention is illustrated below with reference to fig. 7:

writing the target bit value '10010011101001001111' into Word line0 of the flash memory (the initial state of each Cell is an erase state, that is, data '11' is stored), and the writing process is as follows:

step0, the state flag components of all Bit lines are in a conducting state (initial state);

step1, reading the actual voltage states of all cells in the Word line0 by the flash memory chip, wherein the actual voltage states are '1111111111111111111111';

step2, comparing the read current Bit value (actual value) with the target Bit value (expected value), finding that the actual voltage on the

Cell

3,8 and 9 is equal to a preset voltage threshold (expected value voltage), setting the state flag element on the

Cell

3,8 and 9 corresponding to the Bit line to be in an off state, and then selecting neither

Cell

3,8 or 9 in the next writing operation nor reading voltage operation;

and Step3, performing voltage pulse on other cells except

cells

3,8 and 9 on the Word line0 according to the result of Step2, reading the cells which do not reach the expected voltage on the Word line0 (the state flag elements corresponding to the Bit line are in an on state, the off state Bit line is not connected, and no power consumption is generated) after each voltage pulse, setting the state flag elements of the Bit line which reaches the expected voltage after the voltage pulse to be in an off state, and then not conducting the Bit line (and the Bit line) in the subsequent voltage reading operation, so that the power consumption is further reduced.

Step4, repeating Step3 until all cells on the Word line reach a preset voltage threshold (expected value voltage), and finishing data writing;

and Step5, setting the state flag components on all Bit lines to be in a conducting state.

In an embodiment of the present invention, the method further comprises: caching target bit values of all memory cells in at least one wordline of the non-volatile memory device.

Specifically, each of the bit lines is provided with a corresponding high speed register (Page buffer), and the caching target bit values of all memory cells in at least one word line of the nonvolatile memory device includes:

saving the target bit values of all the word lines to a buffer corresponding to each bit line of the nonvolatile storage device, such as: high speed registers, in embodiments of the present invention, the buffer includes, but is not limited to: high-speed registers, such as a high-speed Random Access Memory (Flash Random-Access Memory), a Programmable Read-Only Memory (PROM), an Erasable Programmable Read-Only Memory (EPROM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), a Flash Memory (Flash Memory), and a battery-powered Random Access Memory (RAM).

In an embodiment of the present invention, a flash memory writing method is provided, which is applied to a nonvolatile memory device, where the nonvolatile memory device includes a plurality of word lines and a plurality of bit lines, each word line is composed of a plurality of memory cells, and each bit line corresponds to a unique memory cell in the word line, and the method includes: setting a corresponding state flag bit for each bit line, wherein the state flag bit comprises a conducting flag and a disconnecting flag; acquiring target bit values of all memory cells in the at least one word line; performing voltage pulse on the memory cell of which the state flag bit in the at least one word line is a conducting flag, and reading the current bit value of the memory cell of which the state flag bit in the at least one word line is the conducting flag; determining a storage unit with the current bit value identical to the target bit value, and setting a state flag bit corresponding to the storage unit with the current bit value identical to the target bit value as a disconnection flag; repeatedly carrying out voltage pulse on the memory cells of which the status flag bits are the conducting flags in the at least one word line until the current bit value of each memory cell in the at least one word line is the same as the target bit value; and setting the state flag bits of all the memory cells in the at least one word line as a conducting flag. By adding a state zone bit to the sub-line, the write-in operation and the read-out operation of the memory unit are reduced, and the power consumption of the flash memory chip during writing can be reduced.

Referring to fig. 10, fig. 10 is a schematic structural diagram of a flash memory writing device according to an embodiment of the present invention;

as shown in fig. 10, the flash memory writing apparatus 100 is applied to a nonvolatile memory device, where the nonvolatile memory device includes a plurality of word lines and a plurality of bit lines, each word line includes a plurality of memory cells, and each bit line corresponds to a unique memory cell in the word line, and the apparatus includes:

a status flag setting unit 110, configured to set a corresponding status flag for each bit line, where the status flag includes a conducting flag and a disconnecting flag;

a target bit value obtaining unit 120 configured to obtain target bit values of all memory cells in the at least one word line;

a current bit value obtaining unit 130, configured to perform voltage pulse on the memory cell whose state flag bit in the at least one word line is the conducting flag, and read a current bit value of the memory cell whose state flag bit in the at least one word line is the conducting flag;

a status flag bit changing unit 140, configured to determine a memory cell with the current bit value being the same as the target bit value, and set a status flag bit corresponding to the memory cell with the current bit value being the same as the target bit value as a disconnection flag;

a bit value determining unit 150, configured to repeatedly perform voltage pulse on the memory cell whose status flag bit is a conducting flag in the at least one word line until a current bit value of each memory cell in the at least one word line is the same as the target bit value;

a status flag bit resetting unit 160, configured to set the status flag bits of all the memory cells in the at least one word line to the on flag.

In this embodiment of the present invention, the status flag setting unit 110 is specifically configured to:

In this embodiment of the present invention, the current bit value obtaining unit 130 is specifically configured to:

In an embodiment of the present invention, the apparatus further includes:

the presetting unit 170 is configured to set current bit values of all memory cells in the at least one word line to high level signals in advance.

In an embodiment of the present invention, the apparatus further includes:

a buffer unit 180 for buffering target bit values of all memory cells in at least one word line of the non-volatile memory device.

Since the apparatus embodiment and the method embodiment are based on the same concept, the contents of the apparatus embodiment may refer to the method embodiment on the premise that the contents do not conflict with each other, and are not described herein again.

In an embodiment of the present invention, a flash memory writing apparatus is provided, which is applied to a nonvolatile memory device, where the nonvolatile memory device includes a plurality of word lines and a plurality of bit lines, each word line is composed of a plurality of memory cells, and each bit line corresponds to a unique memory cell in the word line, the apparatus includes: the state flag setting unit is used for setting a corresponding state flag for each bit line, and the state flag comprises a conducting flag and a disconnecting flag; a target bit value acquisition unit configured to acquire target bit values of all memory cells in the at least one word line; a current bit value obtaining unit, configured to perform voltage pulse on the memory cell whose state flag bit in the at least one word line is the conducting flag, and read a current bit value of the memory cell whose state flag bit in the at least one word line is the conducting flag; a state flag bit changing unit, configured to determine a memory cell with a current bit value that is the same as the target bit value, and set a state flag bit corresponding to the memory cell with the current bit value that is the same as the target bit value as a disconnection flag; a bit value judging unit, configured to repeatedly perform voltage pulse on the memory cell whose status flag bit is a conducting flag in the at least one word line until a current bit value of each memory cell in the at least one word line is the same as the target bit value; and the state flag bit resetting unit is used for setting the state flag bits of all the memory cells in the at least one word line to be the conducting flags. By adding a status flag bit to the word line, the write operation and the read operation of the memory cell are reduced, and the power consumption of the flash memory chip during writing can be reduced.

Embodiments of the present invention further provide a non-volatile computer storage medium, where the computer storage medium stores computer-executable instructions, which are executed by one or more processors, such as one processor 111 in fig. 1, and enable the one or more processors to perform the flash memory writing method in any of the above method embodiments, for example, perform the above-described steps shown in fig. 8 to 9; the functions of the respective units shown in fig. 10 can also be realized.

The above-described embodiments of the apparatus or device are merely illustrative, wherein the unit modules described as separate parts may or may not be physically separate, and the parts displayed as module units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network module units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment.

Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented by software plus a general hardware platform, and certainly can also be implemented by hardware. Based on such understanding, the technical solutions mentioned above may be embodied in the form of a software product, which may be stored in a computer-readable storage medium, such as ROM/RAM, magnetic disk, optical disk, etc., and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute the method according to each embodiment or some parts of the embodiments.

Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; within the idea of the invention, also technical features in the above embodiments or in different embodiments may be combined, steps may be implemented in any order, and there are many other variations of the different aspects of the invention as described above, which are not provided in detail for the sake of brevity; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A flash memory writing method is applied to a nonvolatile memory device, the nonvolatile memory device comprises a plurality of word lines and a plurality of bit lines, each word line comprises a plurality of memory cells, and each bit line corresponds to a unique memory cell in the word line, and the method comprises the following steps:

acquiring target bit values of all memory cells in at least one word line;

performing voltage pulse on the memory cell of which the state flag bit in at least one word line is a conducting flag, and reading the current bit value of the memory cell of which the state flag bit in at least one word line is the conducting flag;

repeatedly carrying out voltage pulse on the memory cell of which the status flag bit is a conducting flag in at least one word line until the current bit value of each memory cell in at least one word line is the same as the target bit value;

and setting the state flag bits of all the memory cells in at least one word line as a conducting flag.

2. The method of claim 1, wherein setting a corresponding status flag bit for each bit line comprises:

3. The method of claim 1, wherein the step of voltage pulsing the memory cell with the status-flag bit of the at least one of the word lines as a conducting flag to read the current bit value of the memory cell with the status-flag bit of the at least one of the word lines as a conducting flag comprises:

obtaining a current voltage value of any memory cell in at least one word line;

4. The method of claim 1, wherein before the step of performing a voltage pulse on the memory cell with the status-flag bit of the at least one of the word lines being a conducting flag to read the current bit value of the memory cell with the status-flag bit of the at least one of the word lines being a conducting flag, the method further comprises:

all memory cells in at least one of the word lines are set to an initial state in advance.

5. The method according to any one of claims 1-4, further comprising:

6. A flash memory chip, comprising:

the physical page comprises a plurality of memory cells, control gates of the memory cells are connected to form word lines, sources and drains of the memory cells are connected to form bit lines, each bit line is provided with a state flag component, and the state flag component is used for identifying whether the memory cells of the corresponding bit line reach an expected voltage value or not.

7. The flash memory chip of claim 6, further comprising:

8. The flash memory chip of claim 6, wherein the status flag component is one of: semiconductor diode and/or semiconductor triode and/or MOS tube.

9. The flash memory chip according to any of claims 6-8, wherein the flash memory chip can be an SLC flash memory chip or an MLC flash memory chip or a TLC flash memory chip or a QLC flash memory chip.

10. A non-volatile storage device, comprising:

the flash memory chip of any one of claims 6-9;

a flash memory controller, the flash memory controller comprising:

at least one processor; and the number of the first and second groups,

the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-5.