KR101913331B1 - Nonvolatile memory device, novolatile memory system, program method thereof, and operation method of controller controlling the same - Google Patents

Nonvolatile memory device, novolatile memory system, program method thereof, and operation method of controller controlling the same Download PDF

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KR101913331B1
KR101913331B1 KR1020120006098A KR20120006098A KR101913331B1 KR 101913331 B1 KR101913331 B1 KR 101913331B1 KR 1020120006098 A KR1020120006098 A KR 1020120006098A KR 20120006098 A KR20120006098 A KR 20120006098A KR 101913331 B1 KR101913331 B1 KR 101913331B1
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South Korea
Prior art keywords
memory cell
word line
program
voltage
memory
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KR1020120006098A
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Korean (ko)
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KR20130085154A (en
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박일한
조용성
박상수
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삼성전자주식회사
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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/10Programming or data input circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/24Bit-line control circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G11C16/3427Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written

Abstract

The present invention relates to a flash memory device including a coupling program control unit. A flash memory device according to an embodiment of the present invention includes a first memory cell for programming a first data pattern, a program using a program voltage, a second memory cell; And verifying whether or not the first data pattern of the first memory cell is programmed by using a verify voltage corresponding to the first data pattern, and when the verify result of the first memory cell is a pass, Lt; / RTI >

Description

 TECHNICAL FIELD [0001] The present invention relates to a nonvolatile memory device, a nonvolatile memory system including the nonvolatile memory device, a programming method thereof, and a controller operation method for controlling the nonvolatile memory device,
The present invention relates to a semiconductor memory device, and more particularly, to a nonvolatile memory device including a coupling program control unit and a method of operating the same.
Semiconductor memory devices are generally classified into volatile memories such as DRAMs and SRAMs and nonvolatile memories such as EEPROMs, FRAMs, PRAMs, MRAMs, and Flash memories. The volatile memory loses the stored data when the power is turned off, but the nonvolatile memory preserves the stored data even when the power is turned off. In particular, flash memory devices are widely used as storage media in computer systems and the like because they have the advantages of high programming speed, low power consumption, and large data storage.
A flash memory device may store single bit data in one memory cell or multi bit data in two or more bits. A flash memory device (hereinafter referred to as SLC flash memory device) for storing single bit data has one erase state and one program state according to the threshold voltage distribution. A flash memory device (hereinafter referred to as an MLC flash memory device) for storing multi-bit data has one erase state and a plurality of program states according to the threshold voltage distribution.
In particular, it is important for an MLC flash memory device to have a read margin between each program state. However, flash memory devices can vary in threshold voltage due to various causes during program operation. For example, due to an increase in the threshold voltage of the memory cell, the erase state may overlap with the program state. As a result, read failures may occur during a read operation. Factors that can change the threshold voltage of a memory cell include coupling noise, pass voltage disturbance, and program voltage disturbance.
An object of the present invention is to provide a nonvolatile memory device, a nonvolatile memory system, a program method, and a controller operation method capable of reducing a program disturbance generated in a program operation.
The present invention relates to a flash memory device including a coupling program control unit. A flash memory device according to an embodiment of the present invention includes a first memory cell for programming a first data pattern, a second memory cell for programming using a program voltage, Verifies whether or not the first data pattern of the memory cell is programmed, and terminates the program of the second memory cell when the verification result of the first memory cell is a pass.
 As an embodiment, the second memory cell verifies whether the first data pattern is programmed, using the verify voltage corresponding to the first data pattern, and then performs the program if the verification fails .
In another embodiment, the second cell is a dummy memory cell and is a memory cell having no data pattern provided from the memory controller.
In another embodiment, one non-volatile memory cell is coupled to a first word line, the second memory cell is coupled to a second word line, and the first word line and the second word line are adjacent to each other Line.
In yet another embodiment, a first memory cell is coupled to a first bit line, the second memory cell is coupled to a second bit line, and the first bit line and the second bit line are different bit lines .
According to the present invention, a program operation can be performed while reducing program disturbance.
1 is a block diagram illustrating a flash memory system according to an embodiment of the present invention.
2 is a block diagram illustrating an exemplary flash memory device shown in FIG.
3 is a diagram showing a threshold voltage distribution of a program and erase state after normal program execution of a 3-bit multi-level cell (3-bit-MLC) flash memory.
Figure 4 illustrates a portion of a memory cell array in accordance with an embodiment of the present invention.
5 is a timing diagram of program and verify voltages provided to a portion of the memory cell array shown in FIG.
Figure 6 illustrates a portion 1110B of a memory cell array according to another embodiment of the present invention.
7 is a timing diagram of program and verify voltages provided to a portion of the memory cell shown in FIG.
8A and 8B are conceptual diagrams for programming a selected word line and an adjacent word line according to an embodiment of the present invention.
Figure 9 illustrates a portion of a memory cell array in accordance with another embodiment of the present invention.
Figures 10 and 11 are timing diagrams of program and verify voltages provided in a portion of the memory cell shown in Figure 9.
12 is a block diagram of a non-volatile memory system in accordance with one embodiment of the present invention.
13 to 17 show an example of a three-dimensional implementation of the flash memory device according to the present invention.
18 is a block diagram of an electronic device including a non-volatile memory device according to an embodiment of the present invention.
19 is a block diagram of an electronic device including a non-volatile memory device according to another embodiment of the present invention.
20 is a block diagram of an electronic device including a non-volatile memory device in accordance with another embodiment of the present invention.
21 is a block diagram of an electronic device including a non-volatile memory device in accordance with another embodiment of the present invention.
22 is a block diagram of an electronic device including a non-volatile memory device in accordance with another embodiment of the present invention.
23 is a block diagram of an electronic device including a non-volatile memory device according to another embodiment of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to explain the present invention in detail so that those skilled in the art can easily carry out the technical idea of the present invention. .
1 is a block diagram illustrating a flash memory system according to an embodiment of the present invention. Referring to FIG. 1, a flash memory system 1000 includes a flash memory device 1100 and a memory controller 1200. The flash memory system 1000 shown in FIG. 1 may include all data storage media based on a flash memory such as a memory card, a USB memory, and an SSD.
The flash memory device 1100 can perform erase, write, or read operations under the control of the memory controller 1200. [ To this end, the flash memory device 1100 receives a command CMD, an address ADDR, and data DATA via an input / output line. Also, the flash memory device 1100 receives the power supply PWR through the power supply line and receives the control signal CTRL through the control line. The control signal CTRL may include a command latch enable CLE, an address latch enable ALE, a chip enable nCE, a write enable nWE, a read enable nRE, and the like.
The flash memory device 1100 may include a coupling program control unit 1165. The coupling program control unit 1165 controls the program of the selected word line of the flash memory device 1100 by using a coupling effect of the adjacent cell to program the selected word line . The coupling program control unit 1165 may be included in the memory controller 1200. In this case, the coupling program control unit 1165 can be managed by the flash conversion layer (FTL).
2 is a block diagram illustrating an exemplary flash memory device shown in FIG. 2, a flash memory device 1100 includes a memory cell array 1110, an address decoder 1120, a page buffer circuit 1130, a data input / output circuit 1140, a voltage generator 1150, and a control logic 1160).
The memory cell array 1110 may include a plurality of memory blocks. In Fig. 2, one memory block is shown as an example. Each memory block may be composed of a plurality of physical pages. Here, the physical page means a set of memory cells connected to one word line. Reference numeral 1111 in Fig. 2 is an example of one physical page. Each physical page may be composed of a plurality of memory cells. Each memory cell may be composed of a cell transistor having a control gate and a floating gate.
Single-bit data or multi-bit data of two or more bits can be stored in one memory cell. A memory cell in which single bit data can be stored is called a single level cell (SLC) or a single bit cell, and a memory cell in which multi-bit data can be stored is called a multi-level cell (MLC). Multi Level Cell) or a multi-bit cell.
In the case of a 2-bit MLC flash memory device, two logical pages may be stored on one physical page. Here, a logical page means a set of data that can be simultaneously programmed in one physical page. In the case of a 3-bit MLC flash memory device, three logical pages may be stored in one physical page 1111.
Meanwhile, the memory cell array 1110 includes a plurality of cell strings. Each cell string (e.g., 1101) includes a string selection transistor connected to a string selection line (SSL), a plurality of memory cells connected to a plurality of word lines (WL1 through WLn) And a ground selection transistor connected to a ground selection line (GSL). The string selection transistor is connected to the bit line (BL), and the ground selection transistor is connected to a common source line (CSL).
2, the address decoder 1120 is coupled to the memory cell array 1110 via select lines SSL and GSL or word lines WL1 to WLn. In a program or read operation, the address decoder 1120 receives the address ADDR and can select any word line (e.g., WLn-1). Hereinafter, this is referred to as a selected word line.
The page buffer circuit 1130 is connected to the memory cell array 1110 through the bit lines BL1 to BLm. The page buffer circuit 1130 is composed of a plurality of page buffers (not shown). One bit line may be connected to one page buffer (all BL structure), or two or more bit lines may be connected (shield BL structure). The page buffer circuit 1130 can temporarily store data to be programmed in the selected page 1111 or data read from the selected page 1111. [
The data input / output circuit 1140 is internally connected to the page buffer circuit 1130 through a data line DL and externally connected to a memory controller (see FIG. 1) 1200 through an input / output line (I / O) . The data input / output circuit 1140 receives program data (program data) from the memory controller 1200 during a program operation and provides read data to the memory controller 1200 during a read operation.
The voltage generator 1150 receives the power supply PWR from the memory controller 1200 and generates a word line voltage VWL required to read or write data. The word line voltage VWL is provided to the address decoder 1120. Referring to FIG. 2, the voltage generator 1150 includes a high voltage generator 1151, a low voltage generator 1152, and a negative voltage generator 1153.
The high voltage generator 1151 may generate a high voltage (HV) higher than the power supply voltage. The high voltage can be used as a program voltage (Vpgm) or a pass voltage (Vpass). The low voltage generator 1152 may generate a low voltage (LV) that is equal to or lower than the power supply voltage. The power supply voltage or the low voltage may be used as the bit line pre-charge voltage or the CSL voltage. The negative voltage generator 1153 may generate a negative voltage (NV) lower than the OV. The negative voltage can be used as a program verify voltage.
The control logic 1160 can control operations such as programming, reading, erasing, etc. of the flash memory device 1100 using the command CMD, the address ADDR, and the control signal CTRL. For example, the control logic 1160 allows the program voltage to be provided to the selected word line (e.g., WLn-1) by controlling the address decoder 1120 during program operation, and the page buffer circuit 1130 and / By controlling the data input / output circuit 1140, the program data can be provided to the selected page 1111.
On the other hand, the control logic 1160 may include a coupling program control unit 1165. The coupling program control unit 1165 can control the program operation on the adjacent page 1112 of the selected page 1111 during the program operation. This will be described in detail below.
3 is a diagram showing a program state of a 3-bit MLC flash memory. As shown in FIG. 3, in the case of a 3-bit MLC, it has one erase state E and seven program states P1 to P7.
In the case of a flash memory, over time, a charge loss may occur in which electrons trapped in a floating gate or a tunnel oxide are emitted. Further, if the program and erase are repeated, the tunnel oxide is deteriorated and the charge loss can be further increased. Charge loss can reduce the threshold voltage and consequently shift the threshold voltage distribution to the left.
Also, program disturbance and back pattern dependency can increase the threshold voltage. Therefore, due to such deterioration of cell characteristics, the threshold voltage distributions of adjacent states can overlap each other. When the threshold voltage distributions are superimposed, errors may be included in the read data when a specific read voltage is applied. The present invention eliminates or reduces the program disturb phenomenon, thereby reducing the phenomenon that the threshold voltage distribution changes. According to the present invention, a reading error can be reduced.
4 is a circuit diagram showing a portion 1110A of a memory cell array according to an embodiment of the present invention. 5 is a timing diagram of program and verify voltages provided to a portion of the memory cell array shown in FIG.
Referring to FIG. 4, one block of the memory cell array includes n word lines. The first memory cell A and the first memory cell B storing the first data pattern provided from the memory controller 1200 are located in the selected page 1111 and the second memory cell A, (a, b) are located in the adjacent page 1112.
The flash memory device (see FIG. 2, 1100) is controlled by the coupling program control unit (see FIG. 2, 1165) a, b) and verify the first data pattern using the verify voltage corresponding to the first data pattern in the first memory cell (A, B).
The coupling program control unit 1165 programs the second memory cell a, b again by receiving the program voltage again until the verification result of the first memory cell A, B is passed. When the verification result of the first memory cell (A, B) is a path, the program of the second memory cell (a, b) is ended. The first data pattern may be a data pattern having a highest threshold voltage in the multi-level data pattern. For example, the first data pattern may be in the P7 state.
The coupling program control unit 1165 controls the program operation of the second memory cell (a, b). The coupling program control unit 1165 provides the program voltage to the second memory cell a, b in accordance with the first data pattern and the program state of the first memory cell A, B.
The coupling program control unit 1165 verifies whether the first data pattern is programmed, for example, by using the verification voltage corresponding to the first data pattern in the first memory cell A, B, , It is possible to control to execute the program for the second memory cell (a, b).
The coupling program control unit 1165 also controls the coupling of the second memory cells a and b when the program voltage loop applied to the first memory cells A and B is equal to or greater than a predetermined number of reference loops, b) can be programmed. The coupling program control unit 1165 determines whether the number of fail bits of the selected word line WLn-1 to which the first memory cells A and B are connected is greater than or equal to a certain reference value, b can be programmed.
 4, the first memory cells A and B are located at the n-1 th word line WLn-1 of the memory block, but they are located at the lower word line WL2. .
The second memory cell a, b is connected to the first memory cell A, B and the adjacent dummy word line WLn, 1112. Here, the dummy word line is connected to the memory controller 1200, It is a word line that does not store data patterns. The dummy word lines may be located adjacent to the string select line (SSL) or the ground select line (GSL), respectively.
According to another embodiment of the present invention, a flash memory device is provided in an n-1-th word line (WLn-1) connected to a first memory cell (A, B) And a page buffer 1130 for storing first data pattern information. In addition, the flash memory device includes an n-th word line (WLn) supplied with a program voltage based on the first data pattern information. The coupling program control unit 1165 provides the program voltage to the nth word line WLn.
The voltage generator 1150 provides the verify voltage corresponding to the first data pattern to the (n-1) th word line WLn-1. The n-1 th word line WLn-1 is the upper or lower word line of one memory block of the memory cell array and the nth word line WLn is connected to the n-1 th word line WLn- Word line. The dummy word line is a word line that does not have the data pattern input from the memory control 1200. The dummy word line may be located adjacent to each of the string select line and the ground select line.
The page buffer 1130 identifies a pass or fail of the data pattern of the selected word line in accordance with the verify voltage provided on the selected word line WLn-1. The coupling program control unit 1165 re-applies the program voltage to the dummy word line WLn if it is a pile, depending on the result of the pass or fail.
5 is a timing diagram of program and verify voltages provided to a portion of the memory cell array shown in FIG. Referring to FIG. 5, the abscissa represents time, and the ordinate represents voltage applied to the selected word line WLn-1 and the dummy word line WLn.
5, in accordance with the control of the coupling program control unit 1165, in the first program period PGM1, the first program voltage VPGM1 is applied to the dummy word line WL connected to the second memory cells a and b (WLn).
Next, the first verify voltage Vver1 is connected to the first memory cell A, B and is provided to the selected word line WLn-1 adjacent to the dummy word line WLn. The buffer buffer 1130 can verify the data programmed into the selected word line WLn-1 when a verify voltage is applied to the selected word line WLn-1. The coupling program control unit 1165 may again provide the program voltage to the dummy word line WLn until the verify result of the buffer buffer 1130 is a pass.
5, in accordance with the control of the coupling program control unit 1165, in the second program period PGM2, the second program voltage VPGM2 is applied to the dummy memory cells connected to the second memory cells a and b, And is provided to the word line WLn. The second program voltage VPGM2 is higher than the first program voltage VPGM1.
Next, the second verify voltage Vver2 is connected to the first memory cells A and B and is provided to the selected word line WLn-1 adjacent to the dummy word line WLn. The page buffer 1130 can verify whether the first data programmed to the selected word line WLn-1 is programmed when the verify voltage is applied to the selected word line WLn-1. The coupling program control unit 1165 may again provide the program voltage to the dummy word line WLn until the verify result of the page buffer 1130 is a pass. The coupling program control unit 1165 can control to repeatedly program the dummy word line WLn to the n-th program period.
6 is a circuit diagram showing a portion 1110B of a memory cell array according to another embodiment of the present invention. FIG. 7 is a timing diagram of program and verify voltages provided to a portion 1110B of the memory cell array shown in FIG. FIG. 6 shows an example where the selected word line and the dummy word line are located at the middle portions (WL3 and WL4).
6, the memory cell array includes select word lines (WL3, 1113) programming a first data pattern input from a memory controller (see FIG. 1, 1200) and dummy word lines (WL4, 1114 ). The coupling program control unit 1165 confirms the information of the first data pattern programmed into the selected word line WL3.
The coupling program control unit 1165 applies the first program voltage VPGM1 to the dummy word lines WL4 and 1114 based on the confirmed data information. The coupling program control unit 1165 controls the program of the dummy word line WL4. The coupling program control unit 1165 provides the program voltage to the dummy word line WL4 according to the first data pattern and the program state of the selected word line WL3.
7 is a timing diagram of program and verify voltages provided to a portion of the memory cell shown in FIG. Referring to FIG. 7, the horizontal axis represents time, and the vertical axis represents a voltage provided to the selected word line and the dummy word line.
And the first data information to be programmed in the selected word line WL3 is checked. If the first data information is in the P7 state, the coupling program control unit 1165 sets the first program voltage VPGM1 in the first program period PGM1 To the dummy word line WL4.
Next, the first verify voltage VVER1 is provided to the selected word line WL3 adjacent to the dummy word line WL4. The page buffer 1130 can verify whether the first data programmed into the selected word line WL3 is programmed when the first verify voltage VVER1 is applied to the selected word line WL3. The coupling program control unit 1165 can again provide the program voltage to the dummy word line WL4 until the verify result of the page buffer 1130 is a pass.
Referring to FIG. 7, the coupling program control unit 1165 provides the second program voltage VPGM2 to the dummy word line WL4 in the second program period PGM2. The second program voltage VPGM2 is higher than the first program voltage VPGM1.
Next, the second verify voltage VVER2 is provided to the selected word line WL3 adjacent to the dummy word line WL4. The page buffer 1130 can verify whether the first data programmed to the selected word line WL3 is programmed when the verify voltage is applied to the selected word line WL3. The coupling program control unit 1165 can again provide the program voltage to the dummy word line WL4 until the verify result of the page buffer 1130 is a pass. The coupling program control unit 1165 can control to repeatedly program the dummy word line WL4 to the nth program period.
8A and 8B are diagrams for explaining an operation of programming a dummy word line adjacent to a selected word line according to an embodiment of the present invention. 8A and 8B show the threshold voltage distributions of the 3-bit MLC flash memory shown in FIG. The program state or MLC data pattern of the flash memory device is determined according to the magnitude of the threshold voltage. In FIGS. 8A and 8B, the P7 state, which is the data pattern having the largest threshold voltage in the 3-bit flash memory, will be described as an example.
8A, the selected word line 1111 is a word line that programs data provided from a memory controller (see FIG. 1, 1200), the dummy word line 1112 has an erase state E all, Which does not program the data provided from the memory 1200.
Since the P7 data pattern has the highest threshold voltage, the highest program voltage (Vpgm) is required to produce the P7 data pattern. The threshold voltage of the erase cell may be increased due to the influence of the program disturbance due to the high program voltage VPGM, and the reliability of the flash memory may be impaired.
Referring to FIG. 8A, there are memory cells having a threshold voltage lower than the verify voltage corresponding to the P7 data pattern of the P7 data pattern. That is, on the selected word line WLn-1, there are P7 data pattern memory cells that have not been programmed. The selected word line WLn-1 can know the memory cells that fail by using the verify voltage corresponding to the P7 data pattern.
Referring to FIG. 8B, the coupling program control unit 1165 may program the cells adjacent to the failed memory cell of the P7 data pattern verification. In other words, the coupling program control unit 1165 selects only the memory cells Px adjacent to the failed memory cell in the P7 data pattern verification on the selected word line WLn-1 among the memory cells included in the dummy word line WLn .
As the memory cell of the dummy word line WLn is programmed, the unprogrammed memory cell of the selected word line WLn-1 has its threshold voltage raised by the coupling effect of the adjacent cell. Thus, when verifying the selected word line WLn-1 using the P7 data pattern verify voltage, verification may succeed.
Referring to FIG. 8B, there are no memory cells having a threshold voltage lower than the verify voltage corresponding to the P7 data pattern in the P7 data pattern. Also, programming the dummy word line WLn and completing the programming of the selected word line WLn-1, using the coupling effect of the adjacent cell, is included in the selected word line WLn-1 due to program disturbance effects It is possible to prevent the threshold voltage of the erased cell from increasing.
9 is a circuit diagram showing a portion 1110C of a memory cell array according to another embodiment of the present invention. 10 and 11 are timing diagrams of program and verify voltages provided to a portion of the memory cell array shown in FIG.
Referring to FIG. 9, a selected memory cell A for storing data representing specific information is connected to a second bit line BL2. A dummy memory cell B not storing data indicating specific information is connected to the third bit line BL3. The selected memory cell A and the dummy memory cell B are connected to the same word line WLn-1.
The coupling program control unit (see FIG. 2, 1165) programs the selected memory cell A connected to the second bit line BL2 in a first pattern, confirms whether the first pattern is programmed, And the dummy memory cell B connected to the third bit line BL3 adjacent to the bit line BL2 in the second pattern. The coupling program control unit 1165 programs the dummy memory cell B in the second pattern in the case of a path as a result of checking whether or not the selected memory cell A is programmed. The coupling program control unit 1165 can also perform the verify operation using the verify voltage corresponding to the second pattern in the dummy memory cell B. [
The selected memory cell A is a flag cell and may include information indicating the program state of the memory cells. The coupling program control unit 1165 allows the dummy memory cell B to be programmed simultaneously with the flag cell A. [ This will be described in detail in FIG.
10 is a timing diagram of program and verify voltages provided to a portion of the memory cell array shown in FIG. 10, the horizontal axis represents time, and the vertical axis represents voltages applied to the second and third bit lines and the (n-1) th word line WLn-1.
10, in accordance with the control of the coupling program control unit 1165, in the program period A (PGMA), the program voltages VPGM1 to VPGMn are supplied to the flag cells A and the word lines to which the dummy memory cells B are connected Line WLn-1. The power supply voltage Vdd is provided to the bit line BL3 to which the dummy memory cell B is connected so that the dummy memory cell B is not programmed. The bit line BL2 to which the flag cell A is connected is provided with a ground voltage so that the flag cell A can be programmed in the first pattern.
The program voltage VPGM1 'to VPGMn' is provided to the bit line BL3 to which the dummy memory cell B is connected in the program period PGMB. The second bit line BL2 to which the dummy memory cell B is connected is provided with a ground voltage so that the dummy memory cell B can be programmed in the second pattern. The power supply voltage Vdd is applied to the bit line BL2 to which the flag cell A is connected and the flash cell A is not programmed while the program voltage is applied to the word line WLn-1.
11, the program voltages VPGM1, VPGM2, ..., VPGMn are stored in the flag cell A and in the dummy memory cell 1110 in the C program period t0 to t1, under the control of the coupling program control unit 1165. [ (B) is connected to the connected word line WLn-1.
C program period t0 to t1), while the program voltage VPGM1 to VPGMn is supplied to the word line WLn-1, the second bit line BL2 and the dummy memory cell A ground voltage is applied to the third bit line BL3 to which the flag cell A and the dummy memory cell B are programmed. Each time the program voltages VPGM1 to VPGMn are supplied, the verify voltages VVER1 to VVERn corresponding to the first pattern are applied to the word lines. At this time, the power supply voltage Vdd may be applied to the second and third bit lines BL2 and BL3.
The programming voltages VPGM1 to VPGMn that are higher than the C program period are provided to the word line WLn-1 to which the flag cell A and the dummy memory cell B are connected in the D program period t2 to t3. In the program period, the power supply voltage is supplied to the bit line BL2 to which the flag cell A is connected, and the ground voltage is applied to the bit line BL3 to which the dummy memory cell B is connected. The program is no longer executed, and the dummy memory cell B is programmed.
A predetermined number of program voltage loops can be applied to the dummy memory cell B and thereafter the verify voltage corresponding to the second pattern is used to verify whether the dummy memory cell B is programmed .
12 is a block diagram of a non-volatile memory system in accordance with one embodiment of the present invention. 12, a non-volatile memory system 2000 includes a memory controller 2200 and a flash memory device 2100.
The memory controller 2100 controls the nonvolatile memory system 2000 as a whole. The flash memory device 2100 programs the data provided from the memory controller 2200 under the control of the memory controller 2200. The flash memory device 2100 reads the programmed data under control of the memory controller 2200, and provides the read data to the memory controller 2200. The flash memory device 2100 includes a plurality of word lines and a plurality of memory cells coupled to a plurality of bit lines.
The memory controller 2200 includes a central processing unit (CPU) 2210, a buffer memory 2220, an ECC decoder 2230, and a coupling program control unit 2240.
The central processing unit 2210 controls the operation of the memory controller 2200 as a whole. The central processing unit 2210 can interpret the instruction applied at the host (not shown) and control the overall operation of the flash memory device 2100 according to the analysis result.
The buffer memory 2220 may store various data in order to control the overall operation of the non-volatile memory system 2000. The buffer memory 2220 may store data to be programmed into the flash memory device 2100 or data read from the flash memory device 2100.
 The ECC encoder 2230 can detect and correct errors contained in data read from the flash memory device 2100. A circuit, a system or an apparatus for error correction.
The coupling program control unit 2240 can control the program for the selected word line by using the coupling effect of the adjacent cell to program the specific data pattern of the selected word line of the flash memory device 2100 . The coupling program control unit 1165 may be managed by a flash translation layer (FTL).
The ECC decoder 2230, under the control of the coupling program control unit 2240, The first data error bit can be corrected with reference to the second data received at the dummy word line adjacent to the selected word line at the time of correcting the error bit of the first data received from the selected word line.
The coupling program control unit 2240 may receive the page information deteriorated from the non-volatile memory device 2100 and may refer to the degraded information to provide program instructions to the word line of the degraded page and to a different word line have. For example, the coupling program control unit 2240 may provide program instructions to the degraded word line and adjacent word lines.
13 to 17 show an example of a three-dimensional implementation of the flash memory device according to the present invention. 13 is a block diagram showing the memory cell array 1100 shown in FIG. Referring to FIG. 13, the memory cell array 1100 includes a plurality of memory blocks BLK1 to BLKh. Each memory block BLK has a three-dimensional structure (or vertical structure). For example, each memory block BLK includes structures extending along the first to third directions.
Each memory block BLK includes a plurality of NAND strings NS extending along a second direction. A plurality of NAND strings NS will be provided along the first and third directions. Each NAND string NS includes a bit line BL, at least one string select line SSL, at least one ground select line GSL, a plurality of word lines WL, at least one dummy word line DWL ), And a common source line (CSL). That is, each memory block includes a plurality of bit lines (BL), a plurality of string selection lines (SSL). A plurality of ground select lines GSL, a plurality of word lines WL, a plurality of dummy word lines DWL, and a plurality of common source lines CSL. The memory blocks BLK1 to BLKh are described in more detail with reference to Fig.
Fig. 14 is a perspective view exemplarily showing the memory block BLKi in Fig. 13, and Fig. 15 is a cross-sectional view taken along the line I-I 'in the memory block BLKi in Fig. 14 and 15, the memory block BLKi includes structures extended along the first to third directions.
First, a substrate 111 is provided. Illustratively, substrate 111 will comprise a silicon material doped with a first type impurity. For example, substrate 111 may comprise a silicon material doped with a p-type impurity, or may be a p-type well (e. G., A pocket p-well) . In the following, it is assumed that the substrate 111 is p-type silicon. However, the substrate 111 is not limited to p-type silicon.
On the substrate 111, a plurality of doped regions 311 to 314 extending along the first direction are provided. For example, the plurality of doped regions 311 - 314 may have a second type different from the substrate 111. For example, the plurality of doped regions 311 to 314 may have n-type. In the following, it is assumed that the first to fourth doping regions 311 to 314 are n-type. However, the first to fourth doping regions 311 to 314 are not limited to being n-type.
A plurality of insulating materials 112 extending along the first direction are sequentially provided along the second direction in an area on the substrate 111 corresponding to between the first and second doped regions 311 and 312 . For example, the plurality of insulating materials 112 and the substrate 111 may be provided spaced apart by a predetermined distance along the second direction. For example, the plurality of insulating materials 112 may be provided spaced apart by a predetermined distance, respectively, along the second direction. Illustratively, the insulating materials 112 will comprise an insulating material such as silicon oxide.
(Not shown) disposed sequentially along the first direction in the region on the substrate 111 corresponding to the first and second doped regions 311 and 312 and extending through the insulating materials 112 along the second direction The pillars 113 are provided. Illustratively, each of the plurality of pillars 113 will be connected to the substrate 111 through the insulating materials 112.
Illustratively, each pillar 113 will comprise a plurality of materials. For example, the surface layer 114 of each pillar 113 may comprise a silicon material doped with a first type. For example, the surface layer 114 of each pillar 113 may comprise a doped silicon material of the same type as the substrate 111. In the following, it is assumed that the surface layer 114 of each pillar 113 includes p-type silicon. However, the surface layer 114 of each pillar 113 is not limited to including p-type silicon.
The inner layer 115 of each pillar 113 is comprised of an insulating material. For example, the inner layer 115 of each pillar 113 may be filled with an insulating material such as silicon oxide.
In an area between the first and second doped regions 311 and 312 an insulating layer 116 is provided along the exposed surfaces of the insulating materials 112, the pillars 113, and the substrate 111. Illustratively, the thickness of the insulating film 116 may be less than one-half the distance between the insulating materials 112. That is, between the insulating film 116 provided on the lower surface of the first insulating material of the insulating materials 112 and the insulating film 116 provided on the upper surface of the second insulating material below the first insulating material, 112 and the insulating film 116 may be disposed.
In the region between the first and second doped regions 311 and 312, conductive materials 211 to 291 are provided on the exposed surface of the insulating film 116. For example, a conductive material 211 is provided between the substrate 111 and the insulating material 112 adjacent to the substrate 111 and extending along the first direction. More specifically, a conductive material 211 extending in a first direction is provided between the insulating film 116 and the substrate 111 on the lower surface of the insulating material 112 adjacent to the substrate 111.
A conductive material extending along the first direction is provided between the insulating film 116 on the upper surface of the specific insulating material and the insulating film 116 on the lower surface of the insulating material disposed over the specific insulating material among the insulating materials 112 . Illustratively, a plurality of conductive materials 221 - 281 extending in a first direction are provided between the insulating materials 112. Also provided is a conductive material 291 extending in a first direction in an area on the insulative materials 112. Illustratively, the conductive materials 211-291 in the first direction will be metallic materials. Illustratively, the conductive materials 211-291 in the first direction will be conductive materials such as polysilicon.
In the region between the second and third doped regions 312 and 313, the same structure as the structure on the first and second doped regions 311 and 312 will be provided. Illustratively, in regions between the second and third doped regions 312, 313, a plurality of insulating materials 112 extending in a first direction, sequentially disposed along a first direction, A plurality of pillars 113 passing through the plurality of insulating materials 112, an insulating film 116 provided on the exposed surfaces of the plurality of insulating materials 112 and the plurality of pillars 113, A plurality of conductive materials 212-292 extending along one direction are provided.
In the region between the third and fourth doped regions 313 and 314, the same structure as the structure on the first and second doped regions 311 and 312 will be provided. Illustratively, in a region between the third and fourth doped regions 312, 313, a plurality of insulating materials 112 extending in a first direction, sequentially disposed along a first direction, A plurality of pillars 113 passing through the plurality of insulating materials 112, an insulating film 116 provided on the exposed surfaces of the plurality of insulating materials 112 and the plurality of pillars 113, A plurality of conductive materials 213 to 293 extending along one direction are provided.
Drains 320 are provided on the plurality of pillars 113, respectively. Illustratively, drains 320 will be silicon materials doped with a second type. For example, the drains 320 may be n-type doped silicon materials. In the following, it is assumed that the drains 320 comprise n-type silicon. However, the drains 320 are not limited to including n-type silicon. Illustratively, the width of each drain 320 may be greater than the width of the corresponding pillar 113. For example, each drain 320 may be provided in the form of a pad on the upper surface of the corresponding pillar 113.
On the drains 320, conductive materials 331 to 333 extended in the third direction are provided. The conductive materials 331 to 333 are sequentially disposed along the first direction. Each of the conductive materials 331 to 333 is connected to the drains 320 of the corresponding region. Illustratively, the drains 320 and the conductive material 333 extending in the third direction can each be connected through contact plugs. Illustratively, the conductive materials 331 - 333 extending in the third direction will be metallic materials. Illustratively, the conductive materials 331-333 extended in the third direction will be conductive materials such as polysilicon or the like.
14 and 15, each pillar 113 includes an adjacent region of the insulating film 116 and a plurality of conductor lines 211 to 291, 212 to 292, and 213 to 293 extending along the first direction, Together form a string. For example, each of the pillars 113 may include a plurality of conductor lines 211 to 291, 212 to 292, and 213 to 293 extending along an adjacent region of the insulating film 116 and the first direction, (NS). The NAND string NS includes a plurality of transistor structures TS. The transistor structure TS is described in more detail with reference to FIG.
16 is a cross-sectional view showing the transistor structure (TS) of FIG. 14 to 16, the insulating film 116 includes first to third sub-insulating films 117, 118, and 119.
The p-type silicon 114 of the pillar 113 will operate as a body. The first sub-insulating film 117 adjacent to the pillar 113 will act as a tunneling insulating film. For example, the first sub-insulating film 117 adjacent to the pillar 113 may include a thermally-oxidized film.
The second sub-insulating film 118 will act as a charge storage film. For example, the second sub-insulating film 118 will act as a charge trapping layer. For example, the second sub-insulating film 118 may include a nitride film or a metal oxide film (for example, an aluminum oxide film, a hafnium oxide film, or the like).
The third sub-insulating film 119 adjacent to the conductive material 233 will function as a blocking insulating film. Illustratively, the third sub-insulating layer 119 adjacent to the conductive material 233 extended in the first direction may be formed as a single layer or a multilayer. The third sub-insulating layer 119 may be a high-k dielectric layer having a dielectric constant higher than that of the first and second sub-insulating layers 117 and 118 (for example, an aluminum oxide layer, a hafnium oxide layer, or the like).
Conductive material 233 will operate as a gate (or control gate). That is, the gate (or control gate 233), the blocking insulating film 119, the charge storage film 118, the tunneling insulating film 117, and the body 114 will form a transistor (or memory cell transistor structure). Illustratively, the first to third sub-insulating layers 117 to 119 may constitute an ONO (oxide-nitride-oxide) layer. Hereinafter, the p-type silicon 114 of the pillar 113 will be referred to as a body in the second direction.
The memory block BLKi includes a plurality of pillars 113. That is, the memory block BLKi includes a plurality of NAND strings NS. More specifically, the memory block BLKi includes a plurality of NAND strings NS extending in a second direction (or a direction perpendicular to the substrate).
Each NAND string NS includes a plurality of transistor structures TS disposed along a second direction. At least one of the plurality of transistor structures TS of each NAND string NS operates as a string selection transistor (SST). At least one of the plurality of transistor structures TS of each NAND string NS operates as a ground selection transistor GST.
The gates (or control gates) correspond to the conductive materials 211-291, 212-292, 213-293 extended in the first direction. That is, the gates (or control gates) extend in a first direction to form word lines and at least two select lines (e.g., at least one string select line SSL and at least one ground select line GSL).
The conductive materials 331 to 333 extending in the third direction are connected to one end of the NAND strings NS. Illustratively, the conductive materials 331-333 extending in the third direction act as bit lines BL. That is, in one memory block BLKi, a plurality of NAND strings are connected to one bit line BL.
Second type doped regions 311-314 extending in a first direction are provided at the other end of the NAND strings. The second type doped regions 311 - 314 extending in the first direction act as common source lines (CSL).
In summary, the memory block BLKi includes a plurality of NAND strings extended in a direction perpendicular to the substrate 111 (second direction), and a plurality of NAND strings NS are formed on one bit line BL And operates as a connected NAND flash memory block (for example, charge capturing type).
14 to 16, it has been described that the conductor lines 211 to 291, 212 to 292, and 213 to 293 extending in the first direction are provided in nine layers. However, the conductor lines 211 to 291, 212 to 292, and 213 to 293 extending in the first direction are not limited to being provided in nine layers. For example, conductor lines extending in a first direction may be provided in eight layers, sixteen layers, or a plurality of layers. That is, in one NAND string, the transistors may be 8, 16, or more.
14 to 16, it has been described that three NAND strings NS are connected to one bit line BL. However, it is not limited that three NAND strings NS are connected to one bit line BL. Illustratively, in the memory block BLKi, m NAND strings NS may be connected to one bit line BL. At this time, the number of conductive materials 211 to 291, 212 to 292, and 213 to 293 extending in the first direction and the number of conductive materials 211 to 293 extending in the first direction are the same as the number of NAND strings NS connected to one bit line BL, 311 to 314 will also be adjusted.
14 to 16, three NAND strings NS are connected to one conductive material extending in the first direction. However, it is not limited that three NAND strings NS are connected to one conductive material extending in the first direction. For example, n conductive n-strings NS may be connected to one conductive material extending in a first direction. At this time, the number of bit lines 331 to 333 will also be adjusted by the number of NAND strings NS connected to one conductive material extending in the first direction.
17 is a circuit diagram showing an equivalent circuit of the memory block BLKi described with reference to Figs. 14 to 16. Fig. 14 to 17, NAND strings NS11 to NS31 are provided between the first bit line BL1 and the common source line CSL. The first bit line BL1 will correspond to the conductive material 331 extending in the third direction. NAND strings NS12, NS22, and NS32 are provided between the second bit line BL2 and the common source line CSL. The second bit line BL2 will correspond to the conductive material 332 extending in the third direction. Between the third bit line BL3 and the common source line CSL, NAND strings NS13, NS23, NS33 are provided. The third bit line BL3 will correspond to the conductive material 333 extending in the third direction.
The string selection transistor SST of each NAND string NS is connected to the corresponding bit line BL. The ground selection transistor GST of each NAND string NS is connected to the common source line CSL. Memory cells MC are provided between the string selection transistor SST and the ground selection transistor GST of each NAND string NS.
In the following, NAND strings NS are defined in units of rows and columns. The NAND strings NS connected in common to one bit line form one column. For example, the NAND strings NS11 to NS31 connected to the first bit line BL1 will correspond to the first column. NAND strings NS12 to NS32 connected to the second bit line BL2 will correspond to the second column. The NAND strings NS13 to NS33 connected to the third bit line BL3 will correspond to the third column. NAND strings NS connected to one string select line SSL form one row. For example, the NAND strings NS11 to NS13 connected to the first string selection line SSL1 form a first row. The NAND strings NS21 to NS23 connected to the second string selection line SSL2 form a second row. The NAND strings NS31 to NS33 connected to the third string selection line SSL3 form the third row.
For each NAND string NS, the height is defined. Illustratively, in each NAND string NS, the height of the memory cell MC1 adjacent to the ground selection transistor GST is one. In each NAND string NS, the height of the memory cell increases as it is adjacent to the string selection transistor SST. In each NAND string NS, the height of the memory cell MC7 adjacent to the string selection transistor SST is seven.
The string selection transistors (SST) of the NAND strings (NS) in the same row share a string selection line (SSL). The string selection transistors SST of the NAND strings NS of the different rows are connected to the different string selection lines SSL1, SSL2 and SSL3, respectively.
The memory cells at the same height of the NAND strings NS in the same row share the word line WL. At the same height, the word lines WL connected to the memory cells MC of the NAND strings NS of the different rows are connected in common. The dummy memory cells DMC of the same height of the NAND strings NS in the same row share the dummy word line DWL. At the same height, the dummy word lines DWL connected to the dummy memory cells DMC of the NAND strings NS of the different rows are connected in common.
Illustratively, word lines WL or dummy word lines DWL may be connected in common in layers provided with conductive materials 211-291 212-292, 213-293 extending in a first direction . Illustratively, the conductive materials 211-291 212-292, 213-293 extending in the first direction will be connected to the top layer through the contacts. Conductive materials 211 to 291 212 to 292 and 213 to 293 extending in the first direction in the upper layer may be connected in common. The ground selection transistors GST of the NAND strings NS in the same row share the ground selection line GSL. The ground selection transistors GST of the NAND strings NS of the different rows share the ground selection line GSL. That is, the NAND strings NS11 to NS13, NS21 to NS23, and NS31 to NS33 are commonly connected to the ground selection line GSL.
The common source line CSL is connected in common to the NAND strings NS. For example, in the active region on the substrate 111, the first to fourth doped regions 311 to 314 may be connected. For example, the first to fourth doped regions 311 to 314 may be connected to the upper layer through the contact. The first to fourth doped regions 311 to 314 may be connected in common in the upper layer.
As shown in Fig. 17, the word lines WL having the same depth are connected in common. Thus, when a particular word line WL is selected, all NAND strings NS connected to a particular word line WL will be selected. The NAND strings NS in the different rows are connected to the different string select lines SSL. Therefore, by selecting the string selection lines SSL1 to SSL3, the NAND strings NS of unselected rows among the NAND strings NS connected to the same word line WL are selected from the bit lines BL1 to BL3 Can be separated. That is, by selecting the string selection lines SSL1 to SSL3, a row of NAND strings NS can be selected. Then, by selecting the bit lines BL1 to BL3, the NAND strings NS of the selected row can be selected in units of columns.
In each NAND string NS, a dummy memory cell DMC is provided. The first to third memory cells MC1 to MC3 are provided between the dummy memory cell DMC and the ground selection line GST. The fourth to sixth memory cells MC4 to MC6 are provided between the dummy memory cell DMC and the string selection line SST. In the following, it is assumed that the memory cells MC of each NAND string NS are divided into memory cell groups by the dummy memory cells DMC. Memory cells (for example, MC1 to MC3) adjacent to the ground selection transistor GST among the divided memory cell groups will be referred to as a lower memory cell group. The memory cells (for example, MC4 to MC6) adjacent to the string selection transistor SST among the divided memory cell groups will be referred to as an upper memory cell group.
The function of the coupling program control unit according to the embodiment of the present invention can also be applied to a flash memory device having a 3D structure. The flash memory device having the 3D structure according to the present invention can perform the program of the data pattern using the coupling effect.
18 shows a block diagram of an electronic device 10000 including a non-volatile memory device 16000 in accordance with an embodiment of the present invention.
18, an electronic device 10000, such as a cellular phone, a smart phone, or a tablet PC, includes a non-volatile memory device 16000, which may be embodied as a flash memory device, , And a memory controller 15000 that can control the operation of the non-volatile memory device 16000.
The non-volatile memory device 16000 may refer to the non-volatile memory device shown in Figs. The nonvolatile memory device 16000 includes a first memory cell for programming a first data pattern, a second memory cell for programming using a program voltage, and a verify voltage corresponding to the first data pattern, The program of the second memory cell may be terminated when the verification result of the first memory cell is a path.
Also, the memory controller 15000 may refer to the memory controller shown in Fig. Memory controller 15000 is controlled by processor 11000 which controls the overall operation of the electronic device.
The data stored in the nonvolatile memory device 16000 may be displayed through the display 13000 under the control of the memory controller 15000 operating in accordance with the control of the processor 11000.
The wireless transceiver 12000 may provide or receive a wireless signal via the antenna ANT. For example, the wireless transceiver 12000 may convert the wireless signal received via the antenna ANT into a signal that the processor 11000 can process. The processor 11000 may therefore process the signals output from the wireless transceiver 12000 and store the processed signals in the nonvolatile memory device 16000 via the memory controller 15000 or through the display 13000 have.
The wireless transceiver 12000 may convert the signal output from the processor 11000 into a wireless signal and output the converted wireless signal to the outside through the antenna ANT.
The input device 14000 is a device that can input control signals for controlling the operation of the processor 11000 or data to be processed by the processor 11000 and includes a touch pad and a computer mouse May be implemented with the same pointing device, keypad, or keyboard.
Processor 11000 may be configured to display data output from non-volatile memory device 16000, radio signals output from wireless transceiver 12000, or data output from input device 14000, (13000).
19 shows a block diagram of an electronic device 20000 including a memory controller 24000 and a non-volatile memory device 25000 in accordance with another embodiment of the present invention.
19, a personal computer (PC), a tablet computer, a netbook, an e-reader, a personal digital assistant (PDA), a portable multimedia player (PMP) , An MP3 player, or an MP4 player, may be implemented in a non-volatile memory device 25000, such as a flash memory device, and a non-volatile memory device 25000, And a memory controller 24000 having the same function.
The non-volatile memory device 25000 may refer to the non-volatile memory device shown in Figs. 1 and 2. The non-volatile memory device 25000 includes a first memory cell for programming a first data pattern, a second memory cell for programming using a program voltage, and a verify voltage corresponding to the first data pattern, The program of the second memory cell may be terminated when the verification result of the first memory cell is a path.
Further, the memory controller 24000 may refer to the memory controller shown in Fig.
The electronic device 20000 may include a processor 21000 for controlling the overall operation of the electronic device 20000. The memory controller 24000 is controlled by the processor 21000.
The processor 21000 can display data stored in the nonvolatile memory device through a display in accordance with an input signal generated by the input device 22000. [ For example, the input device 22000 may be implemented as a pointing device such as a touch pad or a computer mouse, a keypad, or a keyboard.
20 shows a block diagram of an electronic device 30000 including a non-volatile memory device 34000 in accordance with another embodiment of the present invention. Referring to FIG. 20, an electronic device 30000 includes a card interface 31000, a memory controller 32000, and a non-volatile memory device 34000, such as a flash memory device.
The electronic device 30000 can issue or receive data with the host (HOST) through the card interface 31000. According to an embodiment, the card interface 31000 may be, but is not limited to, a secure digital (SD) card interface or a multi-media card (MMC) interface. Card interface 31000 may interface data exchange between host (HOST) and memory controller 32000 in accordance with the communication protocol of the host (HOST) capable of communicating with electronic device 30000.
The memory controller 32000 controls the overall operation of the electronic device 30000 and can control the exchange of data between the card interface 31000 and the nonvolatile memory device 34000. In addition, the buffer memory 325 of the memory controller 32000 can buffer data exchanged between the card interface 31000 and the nonvolatile memory device 34000.
The memory controller 32000 is connected to the card interface 31000 and the nonvolatile memory device 34000 via the data bus DATA and the address bus ADDRESS. According to the embodiment, the memory controller 32000 receives the address of the data to be read or written from the card interface 31000 via the address bus ADDRESS and transmits it to the nonvolatile memory device 34000.
The memory controller 32000 also receives or transmits data to be read or written via the data bus (DATA) connected to the card interface 31000 or the nonvolatile memory device 34000, respectively.
The non-volatile memory device 34000 may refer to the non-volatile memory device shown in Figs. The nonvolatile memory device 16000 includes a first memory cell for programming a first data pattern, a second memory cell for programming using a program voltage, and a verify voltage corresponding to the first data pattern, The program of the second memory cell may be terminated when the verification result of the first memory cell is a pass. Also, the memory controller 32000 may refer to the memory controller 1200 shown in FIG.
When the electronic device 30000 in Fig. 20 is connected to a host (HOST) such as a PC, a tablet PC, a digital camera, a digital audio player, a mobile phone, a console video game hardware, or a digital set- Volatile memory device 34000 via the card interface 31000 and the memory controller 32000. The non-volatile memory device 34000 can also receive or receive data stored in the non-volatile memory device 34000 via the card interface 31000 and the memory controller 32000.
Figure 21 shows a block diagram of an electronic device including a memory controller and a non-volatile memory device in accordance with another embodiment of the present invention. 21, the electronic device 40000 includes a non-volatile memory device 45000 such as a flash memory device, a memory controller 44000 for controlling data processing operations of the non-volatile memory device 45000, and an electronic device And an image sensor 41000 capable of controlling the overall operation of the image sensor 40000.
The non-volatile memory device 45000 may refer to the non-volatile memory device shown in Figs. The nonvolatile memory device 45000 includes a first memory cell for programming a first data pattern, a second memory cell for programming using a program voltage, and a verify voltage corresponding to the first data pattern, The program of the second memory cell may be terminated when the verification result of the first memory cell is a pass. Also, the memory controller 44000 may refer to the memory controller shown in Fig.
The image sensor 42000 of the electronic device 40000 converts the optical signal to a digital signal and the converted digital signal is stored in the nonvolatile memory device 45000 under the control of the image sensor 41000 or the display 43000 . Further, the digital signal stored in the nonvolatile memory device 45000 is displayed through the display 43000 under the control of the image sensor 41000.
22 shows a block diagram of an electronic device 60000 including a memory controller 61000 and a non-volatile memory device 62000A, 62000B, 62000C in accordance with another embodiment of the present invention. Referring to FIG. 22, the electronic device 60000 may be implemented as a data storage device such as a solid state drive (SSD).
The electronic device 60000 includes a plurality of nonvolatile memory devices 62000A, 62000B and 62000C and a memory controller 61000 capable of controlling data processing operations of the plurality of nonvolatile memory devices 62000A, 62000B and 62000C, ). The electronic device 60000 may be implemented as a memory system or a memory module.
The non-volatile memory devices 62000A, 62000B, and 62000C may refer to the non-volatile memory devices shown in Figs. 1 and 2. The nonvolatile memory devices 62000A, 62000B, and 62000C may be configured to use a first memory cell to program a first data pattern, a second memory cell to program using a program voltage, and a verify voltage corresponding to the first data pattern, The program of the second memory cell may be terminated when the first data pattern of the first memory cell is programmed and the verification result of the first memory cell is the path. The memory controller 61000 may also refer to the memory controller shown in Fig.
According to an embodiment, the memory controller 61000 may be implemented inside or outside the electronic device 60000.
23 is a block diagram of a data processing system including the electronic device shown in Fig. 22 and 23, a data storage device 70000, which may be implemented as a redundant array of independent disks (RAID) system, includes a RAID controller 71000, a plurality of memory systems 72000A, 72000B to 72000N, N May be a natural number).
Each of the plurality of memory systems 72000A, 72000B to 72000N may be the electronic device 60000 shown in Fig. A plurality of memory systems 72000A, 72000B through 72000N may constitute a RAID array. The data storage device 70000 may be implemented as a personal computer (PC) or an SSD.
During the program operation, the RAID controller 71000 transmits the program data output from the host to the plurality of memory systems 72000A, 72000A, 7200A, and 7200B in accordance with any one selected RAID level based on the RAID level information output from the host among the plurality of RAID levels. 72000B to 72000N). ≪ / RTI >
In addition, during the read operation, the RAID controller 71000 is configured to select one of a plurality of memory systems (72000A, 72000B to 72000N) in accordance with any one selected RAID level based on the RAID level information output from the host among the plurality of RAID levels Data read from any one of the memory systems can be transmitted to the host.
While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.
While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made therein without departing from the spirit and scope of the invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the equivalents of the claims of the present invention as well as the claims of the following.
1000; Flash memory system 1100; Flash memory device
1110; A memory cell array 1200; Memory controller

Claims (53)

  1. A first memory cell in which a first data pattern is stored;
    A second memory cell programmed using a program voltage;
    A first word line coupled to the first memory cell;
    A second word line coupled to the second memory cell, the second word line adjacent to the first word line;
    A common bit line commonly connected to the first and second memory cells; And
    Performing a verify operation to verify whether the first memory cell is programmed with the first data pattern using a verify voltage corresponding to the first data pattern, The program voltage of the second memory cell is used to move the threshold voltage of the first memory cell when the result of the verify operation is a pass, A ring program control unit,
    During the first program period, the coupling program control unit applies a first level of the program voltage to the second word line and then applies the verify voltage to the first word line, but not to the second word line However,
    The coupling program control unit may cause the second level of the program voltage higher than the first level of the program voltage to be applied to the second word line if the result of the verify operation performed subsequent to the first program period is a verify failure And applies the verify voltage to the first word line after applying a second level of the program voltage to the second word line.
  2. The method according to claim 1,
    Wherein the second memory cell is a dummy memory cell having no data pattern provided from a memory controller.
  3. The method according to claim 1,
    Wherein the first data pattern has a highest threshold voltage in a multi-level data pattern.
  4. The method according to claim 1,
    The coupling program control unit applies the verify voltage to the first word line to perform the verify operation, and
    The coupling program control unit is operable to control a threshold of the first memory cell by applying a first level of the program voltage to the second word line when the first level of the program voltage is not applied to the first word line A nonvolatile memory device for moving a voltage.
  5. The method according to claim 1,
    Further comprising a memory cell array including the first and second memory cells,
    Wherein the memory cell array comprises vertical strings and each of the vertical strings comprises memory cells stacked together between a ground selection transistor and a string selection transistor.
  6. A first memory cell in which a first data pattern is stored;
    A second memory cell to which a program voltage is applied;
    A first word line coupled to the first memory cell;
    A second word line coupled to the second memory cell, the second word line adjacent to the first word line;
    A common bit line commonly connected to the first and second memory cells; And
    Applying the program voltage to the second memory cell based on the first data pattern and the program state of the first memory cell, and applying the program voltage when the first memory cell is not being programmed using the program voltage. And a coupling program control unit for shifting a threshold voltage of the first memory cell by a program of the used second memory cell,
    During the first program period, the coupling program control unit applies a verify voltage to the first word line after applying a first level of the program voltage to the second word line, but not to the second word line ,
    Wherein the coupling program control unit applies a second level of the program voltage higher than the first level of the program voltage to the second word line when the result of the verify operation performed subsequent to the first program period is a verify failure And applies a second level of the program voltage to the second word line and then applies the verify voltage to the first word line.
  7. The method according to claim 6,
    Wherein the second memory cell is a dummy memory cell in which a data pattern provided from a memory controller is not stored.
  8. The method according to claim 6,
    Wherein the coupling program control unit performs the verification operation for verifying whether the first memory cell is programmed with the first data pattern using a verify voltage corresponding to the first data pattern, And applies the program voltage to the second memory cell when the result is a verification failure.
  9. 9. The method of claim 8,
    Wherein the first data pattern has a highest threshold voltage in a multi-level data pattern.
  10. 9. The method of claim 8,
    Wherein the first and second memory cells are adjacent to each other.
  11. The method according to claim 6,
    The coupling program control unit applies the verify voltage to the first word line to perform the verify operation, and
    The coupling program control unit is operable to control a threshold of the first memory cell by applying a first level of the program voltage to the second word line when the first level of the program voltage is not applied to the first word line A nonvolatile memory device for moving a voltage.
  12. The method according to claim 6,
    Further comprising a memory cell array including the first and second memory cells,
    Wherein the memory cell array comprises vertical strings and each of the vertical strings comprises memory cells stacked together between a ground selection transistor and a string selection transistor.
  13. A memory cell array including a first memory cell and a second memory cell adjacent to the first memory cell;
    A first word line coupled to the first memory cell;
    A second word line coupled to the second memory cell, the second word line adjacent to the first word line;
    A common bit line commonly connected to the first and second memory cells; And
    And a second memory cell coupled to the memory cell array for detecting a pass or verify failure of the verify operation of the first memory cell and for detecting a program voltage And a control circuit for shifting a threshold voltage of the first memory cell by applying a voltage to the first memory cell,
    Wherein the control circuit applies the program voltage to the second memory cell when the program voltage is not applied to the first memory cell,
    During the first program period, the control circuit applies a verify voltage to the first word line after applying a first level of the program voltage to the second word line, but not to the second word line,
    The control circuit applies a second level of the program voltage to the second word line higher than a first level of the program voltage when the result of the verify operation performed subsequent to the first program period is a verify failure, And applies the verify voltage to the first word line after applying a second level of the program voltage to the second word line.
  14. 14. The method of claim 13,
    Wherein the first memory cell is configured to store a first data pattern,
    The control circuit applies the verify voltage corresponding to the first data pattern to the first memory cell via the first word line to verify whether the first memory cell is programmed with the first data pattern To perform the verification operation, and
    The control circuit terminates applying the program voltage to the second memory cell via the second word line if the result of the verify operation is a pass.
  15. 15. The method of claim 14,
    Wherein the first data pattern has a highest threshold voltage in a multi-level data pattern.
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  17. 14. The method of claim 13,
    Wherein the control circuit includes a coupling program control unit for applying the verify voltage to the first word line during the verify operation,
    The coupling program control unit is operable to control a threshold of the first memory cell by applying a first level of the program voltage to the second word line when the first level of the program voltage is not applied to the first word line A nonvolatile memory device for moving a voltage.
  18. 14. The method of claim 13,
    Wherein the second memory cell is a dummy memory cell having no data pattern provided from a memory controller.
  19. 14. The method of claim 13,
    Wherein the memory cell array comprises vertical strings and each of the vertical strings comprises memory cells stacked together between a ground selection transistor and a string selection transistor.
  20. At least one non-volatile memory device; And
    And a memory controller to control the at least one non-volatile memory device,
    Wherein the at least one non-volatile memory device comprises:
    A memory cell array including a first memory cell and a second memory cell adjacent to the first memory cell;
    A first word line coupled to the first memory cell;
    A second word line coupled to the second memory cell, the second word line adjacent to the first word line;
    A common bit line commonly connected to the first and second memory cells; And
    And a second memory cell coupled to the memory cell array for detecting a pass or verify failure of the verify operation of the first memory cell and for detecting a program voltage And a control circuit for shifting a threshold voltage of the first memory cell by applying a voltage to the first memory cell,
    Wherein the control circuit applies the program voltage to the second memory cell when the program voltage is not applied to the first memory cell,
    During the first program period, the control circuit applies a verify voltage to the first word line after applying a first level of the program voltage to the second word line, but not to the second word line,
    The control circuit applies a second level of the program voltage to the second word line higher than a first level of the program voltage when the result of the verify operation performed subsequent to the first program period is a verify failure, And applies the verify voltage to the first word line after applying a second level of the program voltage to the second word line.
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