CN105975416B - Multichannel friction speed data Transmission system based on FPGA - Google Patents
Multichannel friction speed data Transmission system based on FPGA Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
- G06F13/4226—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with asynchronous protocol
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Abstract
The invention discloses a kind of multichannel friction speed data Transmission system based on FPGA mainly solves the problems, such as that the prior art is difficult to realize that multichannel data friction speed is sent with single device.It includes：Data send software module (1), high speed data transfer module (2), channel selecting module (3) and framing sending module (4).Data send software module (1) and order and data are sent into high speed data transfer module (2), channel selecting module (3) are sent to by high speed data transfer module (2) again, moderator in channel selecting module (3) detects the transmission conditions in each channel according to channel priorities order traversal, jump to corresponding channel, and to upper level returned data request command, when data arrive, the data of transmission are sent into the corresponding channel of framing sending module (4), and data are completed according to the positive flyback length of setting and output clock and are sent.The present invention is adaptable, flexibility ratio is high, can be used for the data that friction speed sends multiple channels.
Description
Technical field
The invention belongs to field of data transmission, are related to a kind of multichannel friction speed data Transmission system, can be used for sending multiple
The data of channel friction speed.
Background technique
In electronic technology, today of computer communication technology high speed development, data transmission technology has become communication system
In one of key technology.The continuous change of the data volume as caused by guided missile, radar, spacecraft and data transfer bandwidth
Change, it is desirable that corresponding data transmission system has the ability of multichannel friction speed data receiver and transmission, to adapt to different rates number
According to the needs of transmission.
But requirement of the multichannel friction speed data transmission to transmission link is very high, and common circuit chip is difficult to meet the requirements,
Specific integrated circuit cost is excessively high, and the development cycle is long, and flexibility is poor, is not suitable for for realizing widely used data multiplex friction speed
Transmission.The existing multi-channel data transmitting system based on pci bus is as shown in Figure 1, it includes data to send software module, high speed
Data transmission module, DMA send control module, local bus module.The system is mainly controlled with high speed data transfer module and DMA
Molding block is core, and wherein high speed data transfer module is integrated with two mutually independent DMA and sends by taking PCI9054 as an example
Controller sends software module by data first and the two paths of data for needing to send is sent into high speed number when needing to send data
According to transmission module, and from PCI9054 to local bus module application local bus access right, after obtaining access right, by high speed
Data are sent control module by DMA and are sent into transmission interface by data transmission module, and after being transmitted, DMA sends control module
It sends and instructs to high speed data transfer module, sending control module setting DMA transfer stop bits to DMA from PCI9054 terminates to pass
It is defeated.This system is although easy to use, but due to that can only realize that twin-channel low speed data is sent, and two channels cannot be set
Friction speed is set, flexibility is poor, and multichannel friction speed data required for not being able to satisfy in most cases are sent.
Summary of the invention
In view of the above-mentioned deficiencies in the prior art, it is an object of the present invention to propose a kind of multichannel friction speed data hair based on FPGA
System is sent, freely to configure transmission speed, flexibly realizes and is sent while multichannel data.
To achieve the above object, the present invention has resourceful, using flexible, reconfigurable, exploitation week using FPGA
Phase short advantage, as the carrier of multichannel friction speed data transmission.The present invention includes：
Data send software module 1, for channel switch, positive flyback length to be arranged, sends data rate, the transmission of each channel
File, and channel switch order, positive flyback length command, output clock selection command, channel priorities order are sent to
High speed data transfer module 2；The data request command returned simultaneously according to high speed data transfer module 2 is in each channel data file
The data that the corresponding file of middle selection transmits 32KB every time give high speed data transfer module, and show data transmission speed and
Send total amount；
High speed data transfer module 2, including PCI-Express high speed interface and dynamic RAM DDR3, should
PCI-Express high speed interface carries out high-speed transfer to data, the data that data transmission software module 1 is transmitted is sent into dynamic
State random access memory DDR3 temporary cache, while data are exported and generate buffer data size indication signal by DDR3；The PCI-
Express high speed interface carries out transmitted in both directions to order, the order and DDR3 output that data transmission software module 1 is transmitted
The buffer data size indication signal data request command being sent into channel selecting module 3, while channel selecting module 3 being returned pass
Software module 1 is sent to data；
Channel selecting module 3, internal includes a channel moderator, realize data from high speed data transfer module 2 to
Channel selecting when framing sending module 4 transmits, guarantees the transmission of each channel data independence friction speed, while according to channel moderator
The current channel of selection and state is sent to 2 returned data request command of high speed data transfer module；
Framing sending module 4, including can produce the Direct Digital Synthesizer DDS of arbitrary size clock, each channel
Data buffer FIFO and each channel framer.When according to the incoming positive flyback length command of channel selecting module 3, output
Clock select command, control data buffer FIFO disposably export the data of trace length, are further continued for after being spaced the length of flyback
The data of output are carried out framing according to fixed frame format by framer and give rear end with serial or parallel form by output
Equipment.
The invention has the advantages that：
1. the data transmission of multichannel and multi tate may be implemented in data Transmission system proposed by the present invention, it has been able to satisfy more
The case where a rear end and needs a variety of transmission rates；
It, can be more in realization 2. multichannel friction speed data transmission mechanism proposed by the present invention compares single pass data transmission
While the high-speed transfer of channel, guarantees that data do not lose, do not malfunction, do not reduce efficiency of transmission；
3. data proposed by the present invention, which send software module, can voluntarily judge data channel priority, each channel hair can be carried out
It send the selection of file, the switch control in each channel and positive flyback length and exports the setting of clock size, it is simple, convenient,
Meet the requirement of a variety of situations；
4. channel selecting module proposed by the present invention, only using a channel moderator to automatic time of data transmission channel
The transmission to realize multichannel data is gone through and arbitrated, resource is saved, improves efficiency；
5. the framing format of data transmitted by framing sending module proposed by the present invention can be changed according to demand, adapt to
Property is strong, flexibility ratio is high.
Detailed description of the invention
Fig. 1 is the block diagram of the existing multi-channel data transmitting system based on pci bus；
Fig. 2 is multichannel friction speed data Transmission system block diagram of the invention；
Fig. 3 is the channel moderator operation schematic diagram in the present invention；
Fig. 4 is the channel moderator channel selecting flow chart in the present invention.
Specific embodiment
The present invention is described in further details below in conjunction with drawings and concrete examples：
Referring to Fig. 2, the present invention is based on the multichannel friction speed data Transmission system of FPGA, including data send software module 1,
High speed data transfer module 2, channel selecting module 3 and framing sending module 4.Wherein：
The data send software module 1, designs based on VS2010, and reading arbitrary size, more can be recycled
The file of kind format, such as：.dat, the formats such as .raw .jpg .bmp .png .GIF .jpeg are opened with the control of each channel
It closes and the setting of positive flyback length, the selection of file to be sent and output clock, the judgement of channel priorities and data is sent
The function that speed and traffic volume are shown.Wherein：
The channel switch of setting is for opening or closing some transmission channel, by channel selecting module (3) according to data
The on and off for the order control channel that software module is sent is sent to realize；
The positive flyback length being arranged is to send software module according to data by framing sending module (4) as unit of byte
The order sent carries out the length of length and interval flyback that data continue trace to send realization；
The transmission data rate of setting is to send software module (1) according to user by data as unit of Mbps or Gbps
The parameter being arranged calculates clock size automatically, generates corresponding control word by framing sending module (4) and controls DDS output institute
The clock for needing size realizes that the friction speed of data is sent as the reading clock of corresponding channel FIFO；
Each channel being arranged file to be sent can be multiple format and up to 8 channels, by channel selecting module
(3) data are sent into each data file that software module is read and carries out channel selecting, realize the channel transmission of data.
Channel priorities order, be calculated automatically by software and the throughput in more each channel obtain, throughput by
Ratio, output clock and the product of output data bit wide three of trace length and the sum of positive flyback calculates, and throughput is bigger
Channel priorities it is higher；
Data transmission speed and data traffic volume show, is that the data volume of transmission per second and total is constantly counted by software
Traffic volume, and by the primary display of the two numerical value refreshing per second on interface.
After the control switch in each channel, positive flyback length, transmission file, output clock are respectively set, data send soft
Part module 1 independently judges sendaisle priority, and channel switch order, positive flyback length command, channel priorities are ordered
It enables, export clock selection command and send high speed data transfer module 2 to, then channel choosing is sent to by high speed data transfer module 2
Select module 3.
The high speed data transfer module 2, including PCI-Express high speed interface and dynamic RAM
The director demon of DDR3, PCI-Express high speed interface and DDR3 are by the basis of Xilinx company IP kernel
Write user interface program realization, wherein PCI-Express high speed interface is counted using DMA direct access method
According to high-speed transfer and software and hardware interaction, the fifo buffer for being 128KB comprising capacity in its control program, being used to will be to
The data of transmission carry out bit width conversion and data buffering, when the programmable full signal of the fifo buffer is effective, feed back to number
According to 1 interrupt request singal of software module is sent, data send pause after software module 1 receives interrupt request singal and send number,
To guarantee that data are not lost while quick transmission；The memory grain that DDR3 is 2GB using cache size, by PCI-
The data of Express high speed interface transmission carry out temporary cache, and the buffer data size indication signal of output is used to real-time
Whether the data volume inside display DDR3 reaches threshold value；
The PCI-Express high speed interface carries out transmitted in both directions to order simultaneously, and data transmission software module 1 is passed
The buffer data size indication signal of the order sent and DDR3 output is sent into channel selecting module 3, while channel selecting module 3 being returned
The data request command returned is transmitted to data and sends software module 1.
The channel selecting module 3, includes a channel moderator, and the clock used is maximum in output clock
Clock guarantees data transmission efficiency to reduce arbitration time.The moderator sends the channel that software module 1 transmits according to data
Priority command judges whether current channel meets transmission conditions, to arbitrate to channel, realizes channel when data transmission
Selection.Wherein, channel transfer condition includes：The programmable full signal of current channel FIFO is low level, i.e. data volume in FIFO
The data volume of not up to set programmable full value representative；The switch life for the current channel that high speed data transfer module 2 transmits
Enabling is high level, i.e. current channel is in the open state；The buffer data size indication signal of DDR3 output is low level, i.e., currently
There are enough spatial caches inside DDR3 data cached.
If current channel is unsatisfactory for three above channel transfer condition, channel moderator detects next channel automatically；If
Current channel meets the condition of transmission, then channel is locked and is sent into the 32KB data in the channel pair of framing sending module 4
It answers in FIFO, after being transmitted, discharges the channel, channel moderator starts to continue to test whether next channel meets transmission item
Part.
Referring to Fig. 3 and Fig. 4, the working principle of channel moderator is illustrated by taking four-way friction speed data Transmission system as an example：
When initial, channel moderator is in traversal detecting state, and each channel is waited for, if the four of user setting
The transmission rate in a channel is respectively：2Gbps, 1.5Gbps, 1Gbps, 800Mbps, then data send software module 1 and count first
The output clock size for calculating four channels is respectively：256MHz,192MHz,128MHz,100MHz；If the trace in four channels
Length is respectively 1000,1100,1200,1300 bytes, and flyback length is respectively 10,20,30,40 bytes, then data are sent soft
Part module 1 judges automatically out four channel priorities sequences according to throughput calculation formula and is followed successively by：1,2,3,4.Channel at this time
Moderator is first begin to the switching signal in the 1st channel of detection, programmable completely signal and DDR3 buffer data size indication signal are
No all to meet condition, if having any one to be unsatisfactory in these three conditions, channel moderator directly detects the biography in the 2nd channel
Defeated condition, the 1st channel are still within wait state；Otherwise channel moderator selects the 1st channel and locks the channel, will
The data of the 32KB of transmission are sent into the FIFO of corresponding channel in framing sending module 4；
After being transmitted, channel moderator enters traversal detecting state again, whether full starts simultaneously at the 2nd channel of detection
Sufficient transmission conditions：If there is any one to be unsatisfactory for, channel moderator directly detects the transmission conditions in the 3rd channel, and the 2nd logical
Road is still within wait state；Otherwise channel moderator selects the 2nd channel and locks the channel, by the number of the 32KB of transmission
According to the FIFO for being sent into corresponding channel in framing sending module 4；
After being transmitted, channel moderator enters traversal detecting state again, whether full starts simultaneously at the 3rd channel of detection
Sufficient transmission conditions：If there is any one to be unsatisfactory for, channel moderator directly detects the transmission conditions in the 4th channel, and the 3rd logical
Road is still within wait state；Otherwise channel moderator selects the 3rd channel and locks the channel, by the number of the 32KB of transmission
According to the FIFO for being sent into corresponding channel in framing sending module 4；
After being transmitted, channel moderator enters traversal detecting state again, whether full starts simultaneously at the 4th channel of detection
Sufficient transmission conditions：If there is any one to be unsatisfactory for, channel moderator directly detects the transmission conditions in the 1st channel, and the 4th logical
Road is still within wait state；Otherwise channel moderator selects the 4th channel and locks the channel, by the number of the 32KB of transmission
According to the FIFO for being sent into corresponding channel in framing sending module 4；
So circulation, by the cycle detection of channel moderator, completes the transmission and transmission of four channel datas.
The framing sending module 4, the Direct Digital Synthesizer DDS, each including can produce arbitrary size clock
The data buffer FIFO in channel and the framer in each channel.The positive flyback length command, defeated being passed to according to channel selecting module 3
Clock selection command out, control data buffer FIFO disposably export the data of trace length, are spaced after the length of flyback again
It continues to output, the data of output are subjected to framing according to fixed frame format by framer and are sent with serial or parallel form
To rear end equipment.Wherein, each channel data buffer FIFO may be programmed full value most greater than trace length in framing sending module 4
8 times be worth greatly, to guarantee that the data volume cached in each channel FIFO in framing sending module 4 meets transmission demand always；FIFO
Capacity and the difference of programmable full value of setting be greater than 32KB, to guarantee not lose during data normal transmission.In the module
The data for exporting trace length are by the rising edge of triggering output clock, and starting counter is counted 1 between trace value
Number, and make the reading of current channel FIFO enable to realize for high level in the count range；It is carried out according to fixed frame format
Framing is to be counted by framer to clock, and add required word in the place that trace data start according to user demand
The header and frame counter of section are realized in the place of the trace end of data plus the mark tail of required byte.
The working principle of present system is as follows：
Data send switch, positive flyback length, the output clock that each channel is arranged in software module 1, select each channel pending
The file sent, and high speed data transfer module 2 is sent into order first, then send channel choosing to through high speed data transfer module 2
Select module 3；Channel moderator in channel selecting module 3 sends the channel priorities order that software module 1 is sent according to data
Traversal detects the transmission conditions in each channel, and locks the corresponding channel for meeting transmission conditions, while sending software mould to data
The data request command of the return corresponding channel of block 1；Data send software module 1 and read corresponding data text according to data request command
The data of 32KB in part, are sent to high speed data transfer module 2；Channel selecting module 3 transmits high speed data transfer module 2
Data are sent into the corresponding channel of framing sending module 4, and channel moderator starts again at work after completing transmission, and traversal detection is next
The channel transfer condition in channel；Framing sending module 4 according to the positive flyback length of setting and the output clock of selection, and utilizes
Each channel data is carried out framing according to fixed frame format and is sent to rear end equipment by clock count.
The above is only an example of the present invention, do not constitute any limitation of the invention, it is clear that on basis of the invention
On can carry out extension and improvement appropriate, but these belong to the scope of the present invention.
Claims (9)
1. a kind of multichannel friction speed data Transmission system based on FPGA, including：
Data send software module (1), and for being arranged, channel switch, positive flyback length, to send data rate, each channel to be sent
File, and channel switch order, positive flyback length command, output clock selection command, channel priorities order are sent to
High speed data transfer module (2)；The data request command returned simultaneously according to high speed data transfer module (2) is in each channel data
The data for selecting corresponding file to transmit 32KB every time in file give high speed data transfer module, and show the transmission speed of data
Degree and transmission total amount；
High speed data transfer module (2), including PCI-Express high speed interface and dynamic RAM DDR3, should
PCI-Express high speed interface carries out high-speed transfer to data, and the data that data send software module (1) transmission are sent into
Dynamic RAM DDR3 temporary cache, while data are exported and generate buffer data size indication signal by DDR3；The PCI-
Express high speed interface carries out transmitted in both directions to order, and the order of data transmission software module (1) transmission and DDR3 is defeated
Buffer data size indication signal out is sent into channel selecting module (3), while the request of data that channel selecting module (3) are returned
Order is transmitted to data and sends software module (1)；
Channel selecting module (3), internal includes a channel moderator, realize data from high speed data transfer module (2) to
Channel selecting when framing sending module (4) transmits, guarantees the transmission of each channel data independence friction speed, while arbitrating according to channel
The current channel and send state to high speed data transfer module (2) returned data request command that device selects；
Framing sending module (4), including can produce the Direct Digital Synthesizer DDS of arbitrary size clock, each channel
The framer of data buffer FIFO and each channel, when according to channel selecting module (3) incoming positive flyback length command, output
Clock select command, control data buffer FIFO disposably export the data of trace length, are further continued for after being spaced the length of flyback
The data of output are carried out framing according to fixed frame format by framer and give rear end with serial or parallel form by output
Equipment；
Channel moderator is the channel priorities that software module (1) transmission is sent according to data in the channel selecting module (3)
Channel is looped through and is arbitrated, and transmission channel is selected according to arbitration result：If current channel is unsatisfactory for transmission conditions,
Then channel moderator detects next channel automatically；If current channel meets the condition of transmission, channel is locked and by the channel
32KB data be sent into framing sending module (4) correspondence FIFO in, after being transmitted, discharge the channel, channel moderator is opened
Beginning continues to test whether next channel meets transmission conditions.
2. multichannel friction speed data Transmission system according to claim 1, which is characterized in that data send software module
(1) set each parameter function is realized as follows in：
The channel switch of setting is sent by channel selecting module (3) according to data for opening or closing some transmission channel
The on and off for the order control channel that software module is sent is realized；
The positive flyback length being arranged is to be sent software module as unit of byte according to data by framing sending module (4) and sent
The order by data continue trace length and interval flyback length carry out sending realization；
The transmission data rate of setting is to send software module (1) according to user setting by data as unit of Mbps or Gbps
The parameter calculate clock size automatically, by framing sending module (4) generate corresponding control word control it is big needed for DDS output
Small clock realizes that the friction speed of data is sent as the reading clock of corresponding channel FIFO；
Each channel being arranged file to be sent can be multiple format and up to 8 channels, will by channel selecting module (3)
Data send each data file that software module is read and carry out channel selecting, realize the channel transmission of data.
3. multichannel friction speed data Transmission system according to claim 1, which is characterized in that data send software module
(1) the channel priorities order in, be calculated automatically by software and the throughput in more each channel obtain, throughput is by just
Ratio, output clock and the product of output data bit wide three of Cheng Changdu and the sum of positive flyback calculates, and throughput is bigger
Channel priorities are higher.
4. multichannel friction speed data Transmission system according to claim 1, which is characterized in that data send software module
(1) data transmission speed and data traffic volume are shown in, are the data volume that transmission per second is constantly counted by software and total hair
The amount of sending, and by the primary display of the two numerical value refreshing per second on interface.
5. multichannel friction speed data Transmission system according to claim 1, which is characterized in that high speed data transfer module
(2) PCI-Express high speed interface in is to realize high speed error free transmission function by writing user control program,
The fifo buffer for being 128KB comprising amount of capacity in program is controlled, for data to be sent are carried out bit width conversion sum number
According to buffering, when the programmable full signal of FIFO is effective, software module (1) is sent to data and feeds back interrupt request singal, data
It sends pause after software module (1) receives interrupt request singal and send number, to guarantee that data are not lost while quick transmission
It loses.
6. multichannel friction speed data Transmission system according to claim 1, which is characterized in that channel selecting module (3)
In channel transfer condition include：The programmable full signal of current channel FIFO is low level, i.e. data volume is not up in FIFO
The data volume that set programmable full value represents；The switch command of current channel of high speed data transfer module (2) transmission is
High level, i.e. current channel are in the open state；The buffer data size indication signal of DDR3 output is low level, i.e., current DDR3
It is data cached that inside has enough spatial caches.
7. multichannel friction speed data Transmission system according to claim 1, which is characterized in that framing sending module (4)
In each channel data buffer FIFO, may be programmed full value and be greater than 8 times of trace length maximum value, to guarantee that framing is sent
The data volume cached in each channel FIFO in module (4) meets transmission demand always；The capacity of FIFO and setting it is programmable full
The difference of value is greater than 32KB, to guarantee not lose during data normal transmission.
8. multichannel friction speed data Transmission system according to claim 1, which is characterized in that framing sending module (4)
The data of middle output trace length are by the rising edge of triggering output clock, and starting counter is carried out 1 between trace value
It counts, and makes the reading of current channel FIFO enable to realize for high level in the count range.
9. multichannel friction speed data Transmission system according to claim 1, which is characterized in that framing sending module (4)
According to fixed frame format carry out framing, be to be counted by framer to clock, and according to user demand in trace data
The place of beginning adds the header and frame counter of required byte, adds the mark tail of required byte in the place of the trace end of data
And realize.
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| CN107145457B (en) * | 2017-04-25 | 2019-10-29 | 电子科技大学 | The device and method of multichannel valid data transmission is promoted based on piece RAM |
| CN109684244A (en) * | 2018-11-14 | 2019-04-26 | 珠海慧联科技有限公司 | I2C bus host optimized transmission method and device for more slave systems |
| CN109413392B (en) * | 2018-11-23 | 2020-10-16 | 中国兵器装备集团自动化研究所 | Embedded multi-channel video image acquisition and parallel processing system and method |
| CN110413562B (en) * | 2019-06-26 | 2021-09-14 | 北京全路通信信号研究设计院集团有限公司 | Synchronization system and method with self-adaptive function |
| CN113556618B (en) * | 2021-07-20 | 2023-03-24 | 北京奇艺世纪科技有限公司 | Data transmission method and device |
| CN113655956B (en) * | 2021-07-26 | 2024-02-02 | 武汉极目智能技术有限公司 | Method and system for high-bandwidth multi-channel data storage and reading unit based on FPGA and DDR4 |
| CN113824649B (en) * | 2021-09-17 | 2023-10-27 | 上海航天计算机技术研究所 | Data flow control device for fixed frame length |
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| CN101729088B (en) * | 2009-11-30 | 2012-11-14 | 西安空间无线电技术研究所 | Data transmission method based on AOS encoding |
| CN103164375A (en) * | 2013-03-19 | 2013-06-19 | 中国科学院声学研究所 | Multichannel digital-to-analogue conversion device communicating with computer through peripheral component interconnect (PCI) bus |
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