CN105975416A - GPFA-based multichannel different-speed data transmission system - Google Patents
GPFA-based multichannel different-speed data transmission system Download PDFInfo
- Publication number
- CN105975416A CN105975416A CN201610273516.2A CN201610273516A CN105975416A CN 105975416 A CN105975416 A CN 105975416A CN 201610273516 A CN201610273516 A CN 201610273516A CN 105975416 A CN105975416 A CN 105975416A
- Authority
- CN
- China
- Prior art keywords
- data
- module
- channel
- transmission
- passage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
- G06F13/4226—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with asynchronous protocol
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Communication Control (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
The invention discloses an FPGA-based multichannel different-speed data transmission system, and mainly aims at solving the problem that the multichannel different-speed data transmission is difficult to realize by single equipment in the prior art. The system comprises a data transmission software module (1), a high-speed data transmission module (2), a channel selection module (3) and a framing transmission module (4), wherein the data transmission software module (1) is used for transmitting a command and data to the high-speed data transmission module (2); the high-seed data transmission module (2) is used for transmitting the command and the data to the channel selection module (3); and an arbiter in the channel selection module (3) is used for traversing and detecting the transmission condition of each channel according to a channel priority command, skipping to corresponding channels, returning data request command to the higher level, transmitting the data to the channel corresponding to the framing transmission module when the data comes, and completing the data transmission according to a set trace and retrace lengths and an output clock. The system disclosed in the invention is strong in adaptability and high in flexibility, and can be used for transmitting the data of a plurality of channels at different speeds.
Description
Technical field
The invention belongs to field of data transmission, relate to a kind of multichannel friction speed data Transmission system, can be used for sending multiple
The data of passage friction speed.
Background technology
In electronic technology, today of computer communication technology high speed development, data transmission technology has become as communication system
In one of key technology.Data volume and data transfer bandwidth produced by guided missile, radar, spacecraft
It is continually changing, it is desirable to corresponding data transmission system has multichannel friction speed data receiver and the ability of transmission, to adapt to
The needs of data with different rate transmission.
But the transmission of multichannel friction speed data is the highest to the requirement of transmission link, and common circuit chip is difficult to meet requirement,
Special IC high cost, the construction cycle is long, very flexible, is not suitable for for realizing widely used data many
Road friction speed transmission.Existing multi-channel data transmitting system based on pci bus is as it is shown in figure 1, it comprises data transmission
Software module, high speed data transfer module, DMA sends control module, local bus module.This system is mainly with height
Speed data transmission module and DMA control module are core, and wherein high speed data transfer module is as a example by PCI9054,
It is integrated with two separate DMA and sends controller, when needs send data, is first sent software by data
Module will need the two paths of data sent to send into high speed data transfer module, and by PCI9054 to local bus module Shen
Please local bus access right, after obtaining access right, by high speed data transfer module by data by DMA send control
Module sends into transmission interface, and after being transmitted, DMA sends control module and sends instruction to high speed data transfer module,
Sent control module setting DMA transfer stop bits by PCI9054 to DMA and terminate transmission.Although this system is the easiest
With, but send owing to twin-channel low speed data can only be realized, and two passages can not arrange friction speed, spirit
Poor activity, it is impossible to meet in most cases required multichannel friction speed data and send.
Summary of the invention
Present invention aims to the deficiencies in the prior art, propose a kind of multichannel friction speed data based on FPGA
Transmission system, freely to configure transmission speed, sends while realizing multichannel data flexibly.
For achieving the above object, the present invention utilizes FPGA to have aboundresources, use flexibly, reconfigurable, the construction cycle
Short advantage, as the carrier of multichannel friction speed data transmission.The present invention includes:
Data send software module 1, for arrange channel switching, positive flyback length, send data rate, each passage send
File, and send channel switching order, positive flyback length command, output clock selection command, channel priorities order to height
Speed data transmission module 2；The data request command simultaneously returned according to high speed data transfer module 2 is in each channel data file
The data selecting corresponding file every time to transmit 32KB give high speed data transfer module, and the transmission speed of video data and sending out
Send total amount；
High speed data transfer module 2, including PCI-Express high speed interface and dynamic RAM DDR3, should
PCI-Express high speed interface carries out high-speed transfer to data, data sends the data that software module 1 transmits and sends into dynamic
State random access memory DDR3 temporary cache, data are exported and produce buffer data size indication signal by DDR3 simultaneously；Should
PCI-Express high speed interface carries out transmitted in both directions to order, and data send order and DDR3 that software module 1 transmits
The buffer data size indication signal of output sends into channel selecting module 3, and the request of data simultaneously channel selecting module 3 returned is ordered
Order is passed to data and is sent software module 1；
Channel selecting module 3, comprises a passage moderator inside it, it is achieved data from high speed data transfer module 2 to framing
Channel selecting when sending module 4 transmits, it is ensured that the transmission of each channel data independence friction speed, selects according to passage moderator simultaneously
Current channel and transmission state return data request command to high speed data transfer module 2；
Framing sending module 4, including producing the Direct Digital Synthesizer DDS of arbitrary size clock, the number of each passage
According to buffer FIFO and the framer of each passage.According to the incoming positive flyback length command of channel selecting module 3, output clock
Select command, controls data buffer FIFO and disposably exports the data of trace length, be further continued for defeated after the length of interval flyback
Go out, framer the data of output carried out framing according to anchor-frame form and give rear end with serial or parallel form and set
Standby.
Present invention have the advantage that
1. the present invention propose data Transmission system can realize multichannel and multi tate data transmission, can meet have multiple
Rear end and the situation of the multiple transmission rate of needs；
2. the multichannel friction speed data transmission mechanism that the present invention proposes, contrasts the transmission of single pass data, can realize manifold
While road high-speed transfer, it is ensured that data are not lost, do not made mistakes, do not reduce efficiency of transmission；
3. the data that the present invention proposes send software module can judge data channel priority voluntarily, can carry out each passage transmission
The selection of file, the on-off control of each passage and positive flyback length and the setting of output clock size, simple to operate, side
Just, the requirement of multiple situation is met；
4. the channel selecting module that the present invention proposes, only utilizes the passage moderator automatic traversal to data transmission channel
Transmission with arbitration realizes multichannel data, saves resource, improves efficiency；
5. the framing format of the sent data of framing sending module that the present invention proposes can be changed according to demand, adaptability
By force, flexibility ratio is high.
Accompanying drawing explanation
Fig. 1 is the block diagram of existing multi-channel data transmitting system based on pci bus；
Fig. 2 is the multichannel friction speed data Transmission system block diagram of the present invention；
Fig. 3 is the passage moderator operating diagram in the present invention；
Fig. 4 is the passage moderator channel selecting flow chart in the present invention.
Detailed description of the invention
Below in conjunction with accompanying drawing and instantiation, the present invention is described in further details:
With reference to Fig. 2, present invention multichannel based on FPGA friction speed data Transmission system, send software module including data
1, high speed data transfer module 2, channel selecting module 3 and framing sending module 4.Wherein:
Described data send software module 1, design based on VS2010, and it can circulate reading arbitrary size, multiple
The file of form, such as: the forms such as .dat .raw .jpg .bmp .png .GIF .jpeg, it has each passage and controls switch
Setting with positive flyback length, file to be sent and the output selection of clock, the judgement of channel priorities and data transmission speed
The function shown with traffic volume.Wherein:
The channel switching arranged, is used to be turned on and off certain transmission channel, channel selecting module (3) sends out according to data
This order sending software module to send controls the on an off of passage and realizes；
The positive flyback length arranged, is in units of byte, framing sending module (4) send software module according to data and send out
The length of length and interval flyback that data are continued trace by this order sent is transmitted realizing；
The transmission data rate arranged, is in units of Mbps or Gbps, data sends software module (1) according to user
This parameter arranged calculates clock size automatically, produces corresponding control word by framing sending module (4) and controls DDS output
The clock of required size, as the reading clock of respective channel FIFO, it is achieved the friction speed of data sends；
The each passage file to be sent arranged, can be multiple format and up to 8 passages, by channel selecting module (3)
Each data file that data send software module reading carries out channel selecting, it is achieved the channel transmission of data.
Channel priorities order, is that the throughput automatically being calculated and comparing each passage by software is obtained, and throughput is long by trace
The product spending the ratio with positive flyback sum, output clock and outputs data bits width three calculates, and the passage that throughput is the biggest is excellent
First level is the highest；
Data transmission speed and data traffic volume show, are constantly to be added up the data volume of transmission per second and total transmission by software
Amount, and refreshing per second for the two numerical value is once shown on interface.
After the control switch of each passage, positive flyback length, transmission file, output clock are respectively provided with, data send software mould
Block 1 independently judges sendaisle priority, and by channel switching order, positive flyback length command, channel priorities order,
Output clock selection command sends high speed data transfer module 2 to, then is sent to channel selecting mould by high speed data transfer module 2
Block 3.
Described high speed data transfer module 2, including PCI-Express high speed interface and dynamic RAM DDR3,
The director demon of PCI-Express high speed interface and DDR3 is by writing use on the basis of Xilinx company IP kernel
Family interface routine realizes, and wherein, PCI-Express high speed interface uses DMA direct access method to carry out the height of data
Speed transmission is mutual with software and hardware, comprises the fifo buffer that capacity is 128KB, be used for be sent in its control program
Data carry out bit width conversion and data buffering, when the able to programme full signal of this fifo buffer is effective, feeds back to data and send out
Sending software module 1 interrupt request singal, data send to suspend after software module 1 receives interrupt request singal send number, to protect
Card data are not lost while quickly transmission；DDR3 uses the memory grain that cache size is 2GB, will
The data of PCI-Express high speed interface transmission carry out temporary cache, and the buffer data size indication signal of its output is used for real
Time show whether the data volume within DDR3 reaches threshold value；
This PCI-Express high speed interface carries out transmitted in both directions to order simultaneously, and data send what software module 1 transmitted
The buffer data size indication signal of order and DDR3 output sends into channel selecting module 3, channel selecting module 3 is returned simultaneously
Data request command pass to data send software module 1.
Described channel selecting module 3, comprises a passage moderator, and its clock used is clock maximum in output clock,
To reduce arbitration time, it is ensured that data transmission efficiency.This moderator sends, according to data, the channel priorities that software module 1 transmits
Whether command determination current channel meets transmission conditions, arbitrates passage, it is achieved channel selecting during data transmission.Its
In, channel transfer condition includes: the able to programme full signal of current channel FIFO is that data volume does not reaches in low level, i.e. FIFO
The data volume represented to set full value able to programme；The switch command of the current channel that high speed data transfer module 2 transmits is high
Level, i.e. current channel are in opening；The buffer data size indication signal of DDR3 output is low level, i.e. current DDR3
It is data cached that inside has enough spatial caches.
If current channel is unsatisfactory for three above channel transfer condition, then passage moderator detects next passage automatically；If currently leading to
Road meets the condition of transmission, then by passage locking and by the corresponding FIFO of the 32KB data feeding framing sending module 4 of this passage
In, after being transmitted, discharging this passage, passage moderator starts to continue to detect whether next passage meets transmission conditions.
With reference to Fig. 3 and Fig. 4, the operation principle of explanation passage moderator as a example by four-way friction speed data Transmission system:
Time initial, passage moderator is in traversal detection state, and each passage is waited for, if the four of user setup lead to
The transmission rate in road is respectively as follows: 2Gbps, 1.5Gbps, 1Gbps, 800Mbps, then first data transmission software module 1 is counted
The output clock size calculating four passages is respectively as follows: 256MHz, 192MHz, 128MHz, 100MHz；If four passages
Trace length be respectively 1000,1100,1200,1300 bytes, flyback length is respectively 10,20,30,40 bytes,
Then data send software module 1 and go out four channel priorities order according to throughput computing formula automatic decision and be followed successively by: 1,2,3,4.
Now passage moderator is first begin to detect the switching signal of the 1st passage, completely signal and DDR3 buffer data size able to programme refer to
Showing that signal the most all meets condition, if having any one to be unsatisfactory in these three condition, then passage moderator directly detects the 2nd
The transmission conditions of passage, the 1st passage is still within waiting state；Otherwise passage moderator selects the 1st passage and this is led to
Road locks, and the data of the 32KB of transmission are sent into the FIFO of respective channel in framing sending module 4；
After being transmitted, passage moderator enters again traversal detection state, starts simultaneously at whether the 2nd passage of detection meets biography
Defeated condition: if there being any one to be unsatisfactory for, then passage moderator directly detects the transmission conditions of the 3rd passage, the 2nd passage
It is still within waiting state；Otherwise passage moderator selects the 2nd passage and is locked by this passage, by the number of the 32KB of transmission
According to sending into the FIFO of respective channel in framing sending module 4；
After being transmitted, passage moderator enters again traversal detection state, starts simultaneously at whether the 3rd passage of detection meets biography
Defeated condition: if there being any one to be unsatisfactory for, then passage moderator directly detects the transmission conditions of the 4th passage, the 3rd passage
It is still within waiting state；Otherwise passage moderator selects the 3rd passage and is locked by this passage, by the number of the 32KB of transmission
According to sending into the FIFO of respective channel in framing sending module 4；
After being transmitted, passage moderator enters again traversal detection state, starts simultaneously at whether the 4th passage of detection meets biography
Defeated condition: if there being any one to be unsatisfactory for, then passage moderator directly detects the transmission conditions of the 1st passage, the 4th passage
It is still within waiting state；Otherwise passage moderator selects the 4th passage and is locked by this passage, by the number of the 32KB of transmission
According to sending into the FIFO of respective channel in framing sending module 4；
So circulation, by the cycle detection of passage moderator, completes transmission and the transmission of four channel datas.
Described framing sending module 4, including producing the Direct Digital Synthesizer DDS of arbitrary size clock, each passage
Data buffer FIFO and the framer of each passage.According to the incoming positive flyback length command of channel selecting module 3, output
Clock selection command, controls data buffer FIFO and disposably exports the data of trace length, after the length of interval flyback followed by
Continuous output, after being carried out the data of output framing and be sent to serial or parallel form according to anchor-frame form by framer
End equipment.Wherein, in framing sending module 4, each channel data buffer FIFO full value able to programme is maximum more than trace length
8 times of value, to ensure that in framing sending module 4, in each passage FIFO, the data volume of caching meets transmission demand all the time；FIFO
The difference of full value able to programme of capacity and setting more than 32KB, not lose during ensureing data normal transmission.In this module
The data of output trace length, are the rising edges by triggering output clock, start enumerator and count between trace value 1
Number, and make current channel FIFO's to read what enable realized for high level in this count range；Carry out according to anchor-frame form
Framing, is to be counted clock by framer, and according to user's request in the place that trace data start plus required byte
Header and frame counter, in the place of the trace end of data plus required byte mark tail and realize.
The operation principle of present system is as follows:
Data send software module 1 and arrange the switch of each passage, positive flyback length, output clock, select each passage to be sent
File, and first high speed data transfer module 2 is sent in order, then send channel selecting mould to through high speed data transfer module 2
Block 3；Passage moderator in channel selecting module 3 sends, according to data, the channel priorities order traversal that software module 1 sends
Detect the transmission conditions of each passage, and lock the respective channel meeting transmission conditions, send software module 1 to data simultaneously and return
Return the data request command of respective channel；Data send software module 1 and read in corresponding data file according to data request command
The data of 32KB, are sent to high speed data transfer module 2；High speed data transfer module 2 is transmitted by channel selecting module 3
Data send into the passage of framing sending module 4 correspondence, and after completing transmission, passage moderator starts again at work, and traversal detects next
The channel transfer condition of passage；Framing sending module 4, according to the positive flyback length arranged and the output clock of selection, and utilizes
Each channel data is carried out framing according to anchor-frame form and is sent to rear end equipment by clock count.
Below it is only an example of the present invention, does not constitute any limitation of the invention, it is clear that on the basis of the present invention
On can carry out suitable extension and improvement, but these broadly fall into the scope of the present invention.
Claims (10)
1. a multichannel friction speed data Transmission system based on FPGA, including:
Data send software module (1), are used for arranging channel switching, positive flyback length, to send data rate, each passage pending
The file sent, and by channel switching order, positive flyback length command, output clock selection command, channel priorities order transmission
To high speed data transfer module (2)；The data request command simultaneously returned according to high speed data transfer module (2) is at each port number
The data every time transmitting 32KB according to the file selecting correspondence in file give high speed data transfer module, and the transmission of video data
Speed and transmission total amount；
High speed data transfer module (2), including PCI-Express high speed interface and dynamic RAM DDR3, should
PCI-Express high speed interface carries out high-speed transfer to data, and data send the data feeding that software module (1) is transmitted
Dynamic RAM DDR3 temporary cache, data are exported and produce buffer data size indication signal by DDR3 simultaneously；Should
PCI-Express high speed interface carries out transmitted in both directions to order, and data send order and DDR3 that software module (1) transmits
The buffer data size indication signal of output sends into channel selecting module (3), and the data simultaneously channel selecting module (3) returned please
Ask order to pass to data and send software module (1)；
Channel selecting module (3), comprises a passage moderator inside it, it is achieved data from high speed data transfer module (2) to
Channel selecting during framing sending module (4) transmission, it is ensured that the transmission of each channel data independence friction speed, arbitrates according to passage simultaneously
Current channel and the state of transmission that device selects return data request command to high speed data transfer module (2)；
Framing sending module (4), including producing the Direct Digital Synthesizer DDS of arbitrary size clock, each passage
Data buffer FIFO and the framer of each passage.According to the incoming positive flyback length command of channel selecting module (3), output
Clock selection command, controls data buffer FIFO and disposably exports the data of trace length, after the length of interval flyback followed by
The data of output are carried out framing according to anchor-frame form by framer and give rear end with serial or parallel form by continuous output
Equipment.
2. according to the multichannel friction speed data Transmission system described in claim 1, it is characterised in that data send software module
(1) each parameter function set in is accomplished by
The channel switching arranged, is used to be turned on and off certain transmission channel, channel selecting module (3) send according to data
This order that software module sends controls the on an off of passage and realizes；
The positive flyback length arranged, is in units of byte, framing sending module (4) send software module according to data and send
This order by data continue trace length and be spaced flyback length be transmitted realizing；
The transmission data rate arranged, is in units of Mbps or Gbps, data sends software module (1) according to user
This parameter arranged calculates clock size automatically, produces corresponding control word by framing sending module (4) and controls DDS output
The clock of required size, as the reading clock of respective channel FIFO, it is achieved the friction speed of data sends；
The each passage file to be sent arranged, can be multiple format and up to 8 passages, by channel selecting module (3) general
Data send each data file of software module reading and carry out channel selecting, it is achieved the channel transmission of data.
3. according to the multichannel friction speed data Transmission system described in claim 1, it is characterised in that data send software module
(1) the channel priorities order in, is that the throughput automatically being calculated and comparing each passage by software is obtained, and throughput is by just
Cheng Changdu calculates with the product of ratio, output clock and the outputs data bits width three of positive flyback sum, the biggest the leading to of throughput
Road priority is the highest.
4. according to the multichannel friction speed data Transmission system described in claim 1, it is characterised in that data send software module
(1) in, data transmission speed and data traffic volume show, are constantly to be added up the data volume of transmission per second and total transmission by software
Amount, and refreshing per second for the two numerical value is once shown on interface.
5. according to the multichannel friction speed data Transmission system described in claim 1, it is characterised in that high speed data transfer module
(2) PCI-Express high speed interface in, is to realize high speed error free transmission function by writing user control program, its
Control program comprises the fifo buffer that amount of capacity is 128KB, is used for data to be sent are carried out bit width conversion sum
According to buffering, when the able to programme full signal of FIFO is effective, send software module (1) feedback interrupt request singal, number to data
Number is sent, to ensure that data are not lost while quickly transmission according to sending to suspend after software module (1) receives interrupt request singal
Lose.
6. according to the multichannel friction speed data Transmission system described in claim 1, it is characterised in that channel selecting module (3)
In channel transfer condition include: the able to programme full signal of current channel FIFO is that data volume is not up in low level, i.e. FIFO
The data volume that set full value able to programme represents；The switch command of the current channel that high speed data transfer module (2) transmits is height
Level, i.e. current channel are in opening；The buffer data size indication signal of DDR3 output is low level, i.e. current DDR3
It is data cached that inside has enough spatial caches.
7. according to the multichannel friction speed data Transmission system described in claim 1, it is characterised in that channel selecting module (3)
Middle passage moderator is to send software module (1) channel priorities that transmits according to data passage is circulated traversal and arbitration,
And according to arbitration result select transmission channel: if current channel is unsatisfactory for transmission conditions, then passage moderator automatically detect next lead to
Road；If current channel meets the condition of transmission, then by passage locking and the 32KB data of this passage are sent into framing sending module
(4) in corresponding FIFO, after being transmitted, discharging this passage, it is the fullest that passage moderator starts to continue to detect next passage
Foot transmission conditions.
8. according to the multichannel friction speed data Transmission system described in claim 1, it is characterised in that framing sending module (4)
In the data buffer FIFO of each passage, its full value able to programme is more than 8 times of trace length maximum, to ensure that framing sends
In module (4), in each passage FIFO, the data volume of caching meets transmission demand all the time；The capacity of FIFO is able to programme with setting
The difference of full value is more than 32KB, not lose during ensureing data normal transmission.
9. according to the multichannel friction speed data Transmission system described in claim 1, it is characterised in that framing sending module (4)
The data of middle output trace length, are the rising edges by triggering output clock, start enumerator and carry out between 1 to trace value
Counting, and make current channel FIFO's to read what enable realized for high level in this count range.
10. according to the multichannel friction speed data Transmission system described in claim 1, it is characterised in that framing sending module (4)
In carry out framing according to anchor-frame form, be by framer, clock to be counted, and open in trace data according to user's request
The place begun plus the header of required byte and frame counter, in the place of the trace end of data plus the mark tail of required byte reality
Existing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610273516.2A CN105975416B (en) | 2016-04-28 | 2016-04-28 | Multichannel friction speed data Transmission system based on FPGA |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610273516.2A CN105975416B (en) | 2016-04-28 | 2016-04-28 | Multichannel friction speed data Transmission system based on FPGA |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105975416A true CN105975416A (en) | 2016-09-28 |
| CN105975416B CN105975416B (en) | 2018-11-20 |
Family
ID=56993274
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610273516.2A Active CN105975416B (en) | 2016-04-28 | 2016-04-28 | Multichannel friction speed data Transmission system based on FPGA |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105975416B (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107145457A (en) * | 2017-04-25 | 2017-09-08 | 电子科技大学 | The device and method of multichannel valid data transmission is lifted based on RAM on piece |
| CN109413392A (en) * | 2018-11-23 | 2019-03-01 | 中国兵器装备集团自动化研究所 | A kind of system and method for embedded type multichannel video image acquisition and parallel processing |
| CN109684244A (en) * | 2018-11-14 | 2019-04-26 | 珠海慧联科技有限公司 | I2C bus host optimized transmission method and device for more slave systems |
| CN110413562A (en) * | 2019-06-26 | 2019-11-05 | 北京全路通信信号研究设计院集团有限公司 | A kind of synchronization system and method with adaptation function |
| CN113556618A (en) * | 2021-07-20 | 2021-10-26 | 北京奇艺世纪科技有限公司 | Data transmission method and device |
| CN113655956A (en) * | 2021-07-26 | 2021-11-16 | 武汉极目智能技术有限公司 | Method and system for high-bandwidth multi-channel data storage and reading unit based on FPGA and DDR4 |
| CN113824649A (en) * | 2021-09-17 | 2021-12-21 | 上海航天计算机技术研究所 | Data flow control device for fixed frame length |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101729088A (en) * | 2009-11-30 | 2010-06-09 | 西安空间无线电技术研究所 | Data transmission method based on AOS encoding |
| CN101740102A (en) * | 2008-11-11 | 2010-06-16 | 西安奇维测控科技有限公司 | Multi-channel flash memory chip array structure and write-in and read-out methods thereof |
| CN103164375A (en) * | 2013-03-19 | 2013-06-19 | 中国科学院声学研究所 | Multichannel digital-to-analogue conversion device communicating with computer through peripheral component interconnect (PCI) bus |
| CN203786732U (en) * | 2013-12-02 | 2014-08-20 | 天津光电通信技术有限公司 | Multi-channel data collecting and processing equipment based on DSP and FPGA |
-
2016
- 2016-04-28 CN CN201610273516.2A patent/CN105975416B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101740102A (en) * | 2008-11-11 | 2010-06-16 | 西安奇维测控科技有限公司 | Multi-channel flash memory chip array structure and write-in and read-out methods thereof |
| CN101729088A (en) * | 2009-11-30 | 2010-06-09 | 西安空间无线电技术研究所 | Data transmission method based on AOS encoding |
| CN103164375A (en) * | 2013-03-19 | 2013-06-19 | 中国科学院声学研究所 | Multichannel digital-to-analogue conversion device communicating with computer through peripheral component interconnect (PCI) bus |
| CN203786732U (en) * | 2013-12-02 | 2014-08-20 | 天津光电通信技术有限公司 | Multi-channel data collecting and processing equipment based on DSP and FPGA |
Non-Patent Citations (2)
| Title |
|---|
| 俞则人: "基于FPGA的光纤通道HBA卡设计与实现", 《信息技术》 * |
| 李吉锋 等: "一种高速并行信号处理系统涉及", 《现代电子技术》 * |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107145457A (en) * | 2017-04-25 | 2017-09-08 | 电子科技大学 | The device and method of multichannel valid data transmission is lifted based on RAM on piece |
| CN107145457B (en) * | 2017-04-25 | 2019-10-29 | 电子科技大学 | The device and method of multichannel valid data transmission is promoted based on piece RAM |
| CN109684244A (en) * | 2018-11-14 | 2019-04-26 | 珠海慧联科技有限公司 | I2C bus host optimized transmission method and device for more slave systems |
| CN109413392A (en) * | 2018-11-23 | 2019-03-01 | 中国兵器装备集团自动化研究所 | A kind of system and method for embedded type multichannel video image acquisition and parallel processing |
| CN110413562A (en) * | 2019-06-26 | 2019-11-05 | 北京全路通信信号研究设计院集团有限公司 | A kind of synchronization system and method with adaptation function |
| CN110413562B (en) * | 2019-06-26 | 2021-09-14 | 北京全路通信信号研究设计院集团有限公司 | Synchronization system and method with self-adaptive function |
| CN113556618A (en) * | 2021-07-20 | 2021-10-26 | 北京奇艺世纪科技有限公司 | Data transmission method and device |
| CN113655956A (en) * | 2021-07-26 | 2021-11-16 | 武汉极目智能技术有限公司 | Method and system for high-bandwidth multi-channel data storage and reading unit based on FPGA and DDR4 |
| CN113655956B (en) * | 2021-07-26 | 2024-02-02 | 武汉极目智能技术有限公司 | Method and system for high-bandwidth multi-channel data storage and reading unit based on FPGA and DDR4 |
| CN113824649A (en) * | 2021-09-17 | 2021-12-21 | 上海航天计算机技术研究所 | Data flow control device for fixed frame length |
| CN113824649B (en) * | 2021-09-17 | 2023-10-27 | 上海航天计算机技术研究所 | Data flow control device for fixed frame length |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105975416B (en) | 2018-11-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105975416A (en) | GPFA-based multichannel different-speed data transmission system | |
| US7752411B2 (en) | Chips providing single and consolidated commands | |
| EP1716474B1 (en) | Adaptive-allocation of i/o bandwidth using a configurable interconnect topology | |
| US9105316B2 (en) | Integrated circuit package with multiple dies and a multiplexed communications interface | |
| EP2333673B1 (en) | Signal sampling and transfer | |
| EP2339795B1 (en) | Inter-chip communication interface for a multi-chip package | |
| EP2330514B1 (en) | An integrated circuit package | |
| EP2339476B1 (en) | Interface connecting dies in an IC package | |
| US5515523A (en) | Method and apparatus for arbitrating conflicts by monitoring number of access requests per unit of time in multiport memory systems | |
| CN110781112A (en) | Dual-channel serial RapidIO interface supporting multiple transmission modes | |
| CN102023947B (en) | Direct interface method of institute of electrical and electronic engineers (IEEE) 1394 bus and high-speed intelligent unified bus | |
| CN110188059A (en) | The flow control type FIFO buffer structure and method of the unified configuration of data valid bit | |
| CN103814367A (en) | Communications assembly comprising multi-channel logic communication via physical transmission path, for serial interchip data transmission | |
| CN101478487B (en) | Control method and apparatus for Ethernet exchange device working rate | |
| US8468381B2 (en) | Integrated circuit package with multiple dies and a synchronizer | |
| Zhou et al. | Optimization design of high-speed data acquisition system based on DMA double cache mechanism | |
| CN103905339A (en) | Computer arbitration system and bandwidth allocation device and method thereof | |
| CN101702714A (en) | Method, system, and apparatus for a credit based flow control in a computer system | |
| CN101192208A (en) | Dual bus circuit based on 8-bit processor | |
| CN206097101U (en) | Multichannel IIC expander circuit system | |
| CN210724858U (en) | Switch control circuit and switch | |
| CN107453781A (en) | A kind of high speed signal change-over circuit | |
| CN202694337U (en) | Data exchange unit based on data sharing of dual-port RAM (random access memory) and communication of 422 serial port | |
| CN103235770B (en) | Based on the solid-state memory at the wide digital interface of carry interface | |
| CN114490474A (en) | System for realizing extension of multi-path UART (universal asynchronous receiver/transmitter) interface through CPLD (complex programmable logic device) |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |