CN206097101U - Multichannel IIC expander circuit system - Google Patents
Multichannel IIC expander circuit system Download PDFInfo
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- CN206097101U CN206097101U CN201620623400.2U CN201620623400U CN206097101U CN 206097101 U CN206097101 U CN 206097101U CN 201620623400 U CN201620623400 U CN 201620623400U CN 206097101 U CN206097101 U CN 206097101U
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Abstract
The utility model provides a multichannel IIC expander circuit system, include: IIC bus module, expander circuit processing module and parallel C neural network P0, expander circuit processing module's one end with IIC bus module connects, expander circuit processing module's the other end with the parallel bus module is connected, IIC bus module has 8 buses, through expander circuit processing module will the parallel bus module expands to 8 IIC buses. Multichannel IIC expander circuit system, through FPGA chip extension multichannel IIC, solve the problem that the serial port expansion module can't carry out high speed communication, have very strong commonality.
Description
Technical field
The utility model is related to a kind of multichannel IIC expanded circuit system, and in particular to a kind of power distribution automation high speed IIC
Extension module, and especially in regard to used in MAX10 types FPGA, bus, IIC, power system.
Background technology
IIC English full name " Inter-Integrated Circuit ", Chinese full name IC bus, a kind of multidirectional control
Bus processed.Because it is using simply, occupancy resource is few, ROM, RAM, I/O end necessary to CPU and system that works independently
The peripheral circuit such as mouth, A/D, D/A is more and more popularized using IIC communications.It is widely used in power distribution automation equipment, CPU is past
IIC communications are carried out toward between needs and multi-disc peripheral hardware, but because the integrated IIC mouths of CPU are less, is unsatisfactory for demand, now
Need to extend IIC communication ports.Many times developer can extend IIC interfaces by UART.The method does not only take up CPU to count not
Many UART interfaces, and efficiency is very low.
Utility model content
The technical problems to be solved in the utility model is to provide a kind of multichannel IIC expanded circuit system, overcomes drawbacks described above,
Solve the problems, such as UART extension IIC and the inefficiency for taking CPU.
To solve above-mentioned technical problem, the utility model provides a kind of multichannel IIC expanded circuit system, including iic bus
Module, expanded circuit processing module and parallel bus module,
One end of the expanded circuit processing module is connected with the iic bus module, the expanded circuit processing module
The other end be connected with the parallel bus module, the iic bus module have 8 buses, at the expanded circuit
The parallel bus module is expanded to 8 iic bus by reason module.
As a kind of a kind of preferred version of multichannel IIC expanded circuit system described in the utility model, the expanded circuit
Processing module includes fpga chip.
As a kind of a kind of preferred version of multichannel IIC expanded circuit system described in the utility model, the fpga chip
Including IIC modules, configuration register module and fifo module,
The IIC modules are made up of 8 IIC, are followed successively by IIC1 to IIC8, and 1 to 8 passage is responsible for successively,
The fifo module includes sending data field, receiving data area and instruction area,
Device CPU configures the communication speed of the IIC modules, the configuration register by the configuration register module
Module writes data into transmission data field, writes the instruction into the instruction area by the IIC modules,
To be deposited to the configuration by the IIC module transfers from the data received by the external world in the receiving data area
Device transfers to the process of described device CPU.
As a kind of a kind of preferred version of multichannel IIC expanded circuit system described in the utility model, the expanded circuit
Processing module also includes the spr registers for depositing communication speed, and the spr registers include eight kinds of communication speeds, wherein,
00 be 1k communication speeds, 01 be 10k communication speeds, 02 be 20k communication speeds, 03 be 50k communication speeds, 04 be 100k communication speed
Rate, 05 be 200k communication speeds, 06 be 500k communication speeds, 07 be 1000k communication speeds.
Compared with prior art, the utility model proposes a kind of multichannel IIC expanded circuit system, by fpga chip expand
Exhibition multichannel IIC, solves the problems, such as that serial ports expansion module cannot carry out high speed communication, with very strong versatility.
Description of the drawings
In order to be illustrated more clearly that the technical scheme of the utility model embodiment, below will be to wanting needed for embodiment description
The accompanying drawing for using is briefly described, it should be apparent that, drawings in the following description are only some enforcements of the present utility model
Example, for those of ordinary skill in the art, without having to pay creative labor, can be with according to these accompanying drawings
Obtain other accompanying drawings.Wherein,
Fig. 1 is a kind of hardware block diagram of multichannel IIC expanded circuit system of the present utility model；
Fig. 2 is a kind of system block diagram of multichannel IIC expanded circuit system of the present utility model；
Fig. 3 is that a kind of IIC of multichannel IIC expanded circuit system of the present utility model writes data flowchart；
Fig. 4 is a kind of IIC time data stream journey figures of multichannel IIC expanded circuit system of the present utility model；
Fig. 5 is a kind of clock system block diagram of multichannel IIC expanded circuit system of the present utility model.
Wherein：1 be iic bus module, 2 be expanded circuit processing module, 3 be parallel bus module, 4 be IIC modules, 5
For configuration register module, 51 be spr registers, 6 be fifo module, 61 for send data field, 62 be receiving data area, 63 be
Instruction area.
Specific embodiment
A kind of multichannel IIC expanded circuit system described in the utility model, it includes：Iic bus module 1, expanded circuit
Processing module 2 and parallel bus module 3.
It is understandable to enable above-mentioned purpose of the present utility model, feature and advantage to become apparent from, with reference to being embodied as
Mode is described in further detail to the utility model.
First, " one embodiment " or " embodiment " referred to herein is referred to and may be included in the utility model at least one in fact
Special characteristic, structure or characteristic in existing mode." in one embodiment " that in this manual different places occur is not
Same embodiment is referred both to, nor single or selectively mutually exclusive with other embodiment embodiment.
Secondly, the utility model is described in detail using structural representation etc., when the utility model embodiment is described in detail,
For purposes of illustration only, schematic diagram can disobey general ratio makees partial enlargement, and the schematic diagram is example, and its here should not be limited
The scope of the utility model protection processed.Additionally, the three dimensions of length, width and depth should be included in actual fabrication.
Fig. 1 is referred to, Fig. 1 is a kind of hardware block diagram of multichannel IIC expanded circuit system of the present utility model.Such as Fig. 1 institutes
Show, multichannel IIC expanded circuit system includes：Iic bus module 1, expanded circuit processing module 2 and parallel bus module 3, it is described
One end of expanded circuit processing module 2 is connected with the iic bus module 1, the other end of the expanded circuit processing module 2 with
The parallel bus module connection 3, the iic bus module 1 has 8 buses, will by the expanded circuit processing module 2
The parallel bus module 3 expands to 8 iic bus.Using fpga chip as the chip of expanded circuit processing module 2, pass through
Bus mode extends 8 road IIC interfaces.
Fig. 2 is referred to, Fig. 2 is a kind of system block diagram of multichannel IIC expanded circuit system of the present utility model.Such as Fig. 2 institutes
Show, fpga chip is made up of IIC modules 4, configuration register module 5, the part of fifo module 6 three.
IIC modules 4 are made up of 8 IIC, are followed successively by IIC1 to IIC8, and they are responsible for successively 1 to 8 passage.
8 IIC transmitter-receiver systems in IIC modules 4 are identical, and this is sentenced as a example by IIC1.Device CPU first passes through instruction area
63 configuration IIC1 communication speeds.Start to write data from address 0, each cycle writes a 8bit data, at most can write
500, after data all write transmission data field 61 are sent, then write in the instruction area 63 of the IIC1 that address is 8000
0x01, the write in address is for the instruction area 63 of 8001-8002 needs the data amount check for sending.Now FPGA begins through IIC1
Data are sent, after whole has sent IIC1 sends the data in data field 61, the instruction area 63 of this sector address can be reset, together
When the instruction area 63 of IIC1 to address for 8000-8002 reset, and in the instruction that the command register address of IIC1 is 8003
Area 63 writes 0x01.When the value that device CPU is read in the instruction area 63 that address is 8003 is 0x01, that is, represent that device CPU can
To carry out the transmission of lower secondary data, while can be that 8003 instruction area 63 resets to address.
Data are sent to device by IIC1 when outside, data can be carried out serioparallel exchange by IIC1, from address 4000 to
The data that the write of receiving data area 62 of IIC1 is received, it is 500 that maximum receives length, after external data has been received,
FPGA can write 0x01 in the instruction area 63 of the IIC1 that address is 8010 again, write in address is 8011-8012 instruction areas 63
Enter to need the data amount check for sending.It is 0x01 when device CPU detects the value that address is 8010 instruction areas 63, and is according to address
8011-8012 can now read the data in IIC1 receiving datas area 62, after having read, can be clear to the register of this sector address
Zero, while the instruction area 63 of IIC1 to address for 8010-8013 resets, and it is 8013 to post in the address of instruction area 63 of IIC1
Storage writes 0x01.When it is 0x01 that device CPU read address to be value in 8013 registers, that is, represent that FPGA can be carried out down
The reception of secondary data, while can be 8003 register clearing to address.
Fig. 3 is referred to, Fig. 3 is that a kind of IIC of multichannel IIC expanded circuit system of the present utility model writes data flowchart.
Once as shown in figure 3, detecting startup order, " startup " state can be entered from " standby " state.In starting state, configuration is posted
Buffer module 5 is configured accordingly, after the completion of configuration, enters " device address " state.In " device address " state, according to sending out
Sending needs the external device address of operation, after having sent 7 device addresses, enters " response 1 " state.In " response 1 " state
FPGA can wait the response signal of external equipment, once detect response signal, i.e., into " data address " state.In " data
Address " state, if operating to single address, only need to send current address, if operating to continuation address,
Only need to send first address, after being sent completely, enter " response 2 " state.In " response 2 " state FPGA outside can be waited to set
Standby response signal, once detect response signal, i.e., into " data " state.Into after " data " state, can be in " data "
Circulate back and forth between state and " response 3 ", until writing all data after, enter " stopping " state.
Fig. 4 is referred to, Fig. 4 is a kind of IIC time data stream journey figures of multichannel IIC expanded circuit system of the present utility model.
Once as shown in figure 4, detecting startup order, " startup " state can be entered from " standby " state.In starting state, configuration is posted
Buffer module 5 is configured accordingly, after the completion of configuration, enters " device address " state.In " device address " state, according to sending out
Sending needs the external device address of operation, after having sent 7 device addresses, enters " response 1 " state.In " response 1 " state
FPGA can wait the response signal of external equipment, once detect response signal, i.e., into " data " state.In data mode,
FPGA from address 0, can read the total data of the inside of address 255, after often running through a data, wait external equipment, enter
" response 2 ", after external-device response, enters back into " data " state, so circulation, until reading is complete, afterwards into " stopping "
State.
Configuration register module 5 can carry out separate configurations to each IIC, and spr registers 51 are communication speed register,
Have eight kinds of communication speeds and be available for configuration, 00 is 1k communication speeds；01 is 10k communication speeds；02 is 20k communication speeds；03 is
50k communication speeds；04 is 100k communication speeds；05 is 200k communication speeds；06 is 500k communication speeds；07 is 1000k communications
Speed.
Fig. 5 is referred to, Fig. 5 is a kind of clock system block diagram of multichannel IIC expanded circuit system of the present utility model.As schemed
Shown in 5, the utility model can provide 8 kinds of communication speeds, be followed successively by 1k, 10k, 20k, 50k, 100k, 200k, 500k, 1000k
Several communication speed clock generation mechanisms are identical, and this is sentenced as a example by 1k communication speeds." 1k frequency dividers " is first to system clock
(F1) divided, frequency dividing multiple is F1/1k；" 1k counters " is counted to system clock, at (0- (F1/1k-2)),
Data are 0, as F1/1k-1, export high level, and data are 1；" 1k clocks " basis " 1k counters " Data Data output height
Level, if data are low level for 0, if data are high level for 1.
Those of ordinary skill in art it should be appreciated that, the characteristics of the utility model or one of purpose exists
In：Multichannel IIC expanded circuit system described in the utility model, by fpga chip multichannel IIC is extended, and solves serial ports expansion mould
Part cannot carry out the problem of high speed communication, with very strong versatility.
It should be noted that above example is only to illustrate the technical solution of the utility model and unrestricted, although reference
Preferred embodiment has been described in detail to the utility model, it will be understood by those within the art that, can be to this reality
Modified with new technical scheme or equivalent, without deviating from the spirit and scope of technical solutions of the utility model,
It all should cover in the middle of right of the present utility model.
Claims (4)
1. multichannel IIC expanded circuit system, it is characterised in that include：Iic bus module, expanded circuit processing module and parallel
Bus module,
One end of the expanded circuit processing module is connected with the iic bus module, the expanded circuit processing module it is another
One end is connected with the parallel bus module, and the iic bus module has 8 buses, and by the expanded circuit mould is processed
The parallel bus module is expanded to 8 iic bus by block.
2. multichannel IIC expanded circuit system as claimed in claim 1, is characterized in that：The expanded circuit processing module includes
Fpga chip.
3. multichannel IIC expanded circuit system as claimed in claim 2, is characterized in that：The fpga chip include IIC modules,
Configuration register module and fifo module,
The IIC modules are made up of 8 IIC, are followed successively by IIC1 to IIC8, and 1 to 8 passage is responsible for successively,
The fifo module includes sending data field, receiving data area and instruction area,
Device CPU configures the communication speed of the IIC modules, the configuration register module by the configuration register module
Write data into transmission data field, write the instruction into the instruction area by the IIC modules,
To be handed over to the configuration register by the IIC module transfers from the data received by the external world in the receiving data area
By the process of described device CPU.
4. multichannel IIC expanded circuit system as claimed in claim 3, is characterized in that：The expanded circuit processing module is also wrapped
The spr registers for depositing communication speed are included, the spr registers include eight kinds of communication speeds, wherein, 00 is 1k communication speed
Rate, 01 be 10k communication speeds, 02 be 20k communication speeds, 03 be 50k communication speeds, 04 be 100k communication speeds, 05 be 200k
Communication speed, 06 be 500k communication speeds, 07 be 1000k communication speeds.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620623400.2U CN206097101U (en) | 2016-06-22 | 2016-06-22 | Multichannel IIC expander circuit system |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620623400.2U CN206097101U (en) | 2016-06-22 | 2016-06-22 | Multichannel IIC expander circuit system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109491946A (en) * | 2018-11-12 | 2019-03-19 | 郑州云海信息技术有限公司 | A kind of chip and method for I2C bus extension |
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2016
- 2016-06-22 CN CN201620623400.2U patent/CN206097101U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109491946A (en) * | 2018-11-12 | 2019-03-19 | 郑州云海信息技术有限公司 | A kind of chip and method for I2C bus extension |
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