CN209118268U - A kind of high robust spi bus driving circuit - Google Patents

Abstract

The utility model relates to a kind of high robust spi bus driving circuits, including a SPI main equipment and N number of SPI from equipment, N >=1, SPI main equipment is connected with N number of SPI from equipment via MOSI signal wire and MISO signal wire, the port CS of SPI main equipment is connected with N number of SPI from the port CS of equipment via different CS signal wires respectively, it is characterized in that, it further include N number of Schmidt trigger, SPI main equipment and N number of SPI are when n-th of SPI is connected from equipment from the device, n=1, ..., N, the port SCLK of SPI main equipment is connected with n-th of SPI from the port SCLK of equipment via SCLK signal line and the n Schmidt trigger on SCLK signal line.Driving SPI is from equipment after the spi bus clock signal that SPI main equipment generates is overturn by Schmidt trigger, to improve the robustness of spi bus driving circuit.

Description

A kind of high robust spi bus driving circuit

Technical field

The utility model relates to a kind of spi bus driving circuits.

Background technique

SPI is the abbreviation of Serial Peripheral Interface (SPI) (Serial Peripheral Interface).SPI be a kind of high speed, Full duplex, synchronization communication bus, and only take up four lines on the pin of chip, saved the pin of chip, be simultaneously The layout of PCB saves space.Exactly for this characteristic easy to use, nowadays more and more integrated chips are this logical Believe agreement, such as STM32F207.SPI is communicated with master-slave mode, this mode usually have a main equipment and it is one or more from Equipment needs at least 4 signal wires, as shown in Figure 1, they are respectively:

(1) MOSI signal wire --- host output/slave input (Master Output/Slave Input)；

(2) MISO signal wire --- host input/slave output (Master Input/Slave Output)；

(3) SCLK signal line --- clock signal is generated by main equipment；

(4) CS signal wire --- from equipment enable signal, (Chip select) is controlled by main equipment.

Wherein CS signal wire is whether control chip is selected, that is to say, that only chip selection signal is prespecified makes It is just effective to the operation of this chip when energy signal (high potential or low potential).This allows for connecting multiple SPI on same bus Equipment is possibly realized.

SPI is serial communication bus, that is to say, that data are one one transmission.Here it is the presence of SCLK signal line The reason of, clock pulses is provided by SCLK signal line, MOSI signal wire and MISO signal wire are then based on this pulse and complete data biography It is defeated.By MOSI signal wire, data change in rising edge clock or failing edge for data output, back to back failing edge or on Edge is risen to be read.A data transmission is completed, input also uses same principle.In this way, in the change of at least 8 times clock signals (above edge and lower edge are primary), so that it may complete the transmission of 8 data.

SPI main equipment should be consistent with polarity with the clock phase of the slave equipment communicated.First, when main equipment SPI Clock and polar configuration should be determined by peripheral hardware；Second, the configuration of the two should be consistent, i.e. the MOSI of main equipment with from The MOSI configuration consistency of equipment, the MISO of main equipment is the same as the MISO configuration consistency from equipment.Because master-slave equipment is in SCLK Under control, while data are sent and received, and exchanges data by 2 bidirectional shift registers.

Existing main equipment and the mode robustness communicated from equipment utilization SPI are poor, have not been able to satisfy special want The application for the occasion asked.

Summary of the invention

The purpose of this utility model is: providing a kind of spi bus driving circuit with high robust.

In order to achieve the above object, there is provided a kind of high robust spi bus to drive for the technical solution of the utility model Circuit, including a SPI main equipment and N number of SPI, from equipment, N >=1, SPI main equipment is via MOSI signal wire and MISO signal wire It is connected with N number of SPI from equipment, the port CS of SPI main equipment is respectively via different CS signal wire and N number of SPI from the CS of equipment Port is connected, which is characterized in that further include N number of Schmidt trigger, SPI main equipment and N number of SPI from the device n-th of SPI from When equipment is connected, n=1 ... ..., N, the port SCLK of SPI main equipment is via SCLK signal line and the n on SCLK signal line A Schmidt trigger is connected with n-th of SPI from the port SCLK of equipment.

In the present invention, the spi bus clock signal that SPI main equipment generates overturns rear-guard by Schmidt trigger SPI is moved from equipment, to improve the robustness of spi bus driving circuit, and the clock of SPI main equipment is compareed from equipment Spi bus timing realizes the correct configuration of SPI main equipment clock.

Detailed description of the invention

Fig. 1 is the circuit diagram of existing spi bus driving circuit；

Fig. 2 is the circuit diagram of the utility model.

Specific embodiment

The present invention will be further illustrated below in conjunction with specific embodiments.It should be understood that these embodiments are merely to illustrate this Utility model rather than limitation the scope of the utility model.In addition, it should also be understood that, in the content for having read the utility model instruction Later, those skilled in the art can make various changes or modifications the utility model, and such equivalent forms equally fall within this Shen It please the appended claims limited range.

As shown in Fig. 2, a kind of high robust spi bus driving circuit disclosed in the present embodiment, including a SPI main equipment And three SPI are from equipment.SPI main equipment and three SPI are same from passing through between the data transmission port of the spi bus of equipment MOSI signal wire and MISO signal wire are connected.

The port CS of SPI main equipment is connected with first SPI from the port CS of equipment via CS signal wire 0.SPI main equipment The port CS be connected with second SPI from the port CS of equipment via CS signal wire 1.Believe via CS the port CS of SPI main equipment Number line 2 is connected with third SPI from the port CS of equipment.

The port SCLK of SPI main equipment is via SCLK signal line and a Schmidt trigger and first SPI from equipment The port SCLK be connected.The port SCLK of SPI main equipment is via SCLK signal line and two Schmidt triggers and second SPI It is connected from the port SCLK of equipment.The port SCLK of SPI main equipment is via SCLK signal line and three Schmidt triggers and Three SPI are connected from the port SCLK of equipment.

Claims (1)

1. a kind of high robust spi bus driving circuit, including a SPI main equipment and N number of SPI are from equipment, N >=1, SPI master Equipment is connected with N number of SPI from equipment via MOSI signal wire and MISO signal wire, and the port CS of SPI main equipment is not respectively via Same CS signal wire is connected with N number of SPI from the port CS of equipment, which is characterized in that further includes N number of Schmidt trigger, SPI master Equipment and N number of SPI are when n-th of SPI is connected from equipment from the device, n=1 ... ..., N, the port SCLK of SPI main equipment via SCLK signal line and the n Schmidt trigger on SCLK signal line are connected with n-th of SPI from the port SCLK of equipment.