CN107229589B - TTL communication bus sub-module expansion circuit - Google Patents
TTL communication bus sub-module expansion circuit Download PDFInfo
- Publication number
- CN107229589B CN107229589B CN201710475673.6A CN201710475673A CN107229589B CN 107229589 B CN107229589 B CN 107229589B CN 201710475673 A CN201710475673 A CN 201710475673A CN 107229589 B CN107229589 B CN 107229589B
- Authority
- CN
- China
- Prior art keywords
- sub
- tri
- bus
- ttl
- module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004891 communication Methods 0.000 title claims abstract description 22
- 239000000872 buffer Substances 0.000 claims abstract description 66
- 238000000034 method Methods 0.000 description 8
- 230000009471 action Effects 0.000 description 5
- 230000005540 biological transmission Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000004044 response Effects 0.000 description 4
- 230000008569 process Effects 0.000 description 3
- 230000001360 synchronised effect Effects 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000001419 dependent effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4086—Bus impedance matching, e.g. termination
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0002—Serial port, e.g. RS232C
Abstract
The invention relates to the field of bus communication, and discloses a TTL communication bus submodule extension circuit, which comprises: a TTL bus; a tri-state buffer; a main module including a transmitting pin and a receiving pin for transmitting a request signal and receiving a feedback signal; and the plurality of sub-modules respectively comprise a sending pin and a receiving pin, and are used for receiving the request signal and sending the feedback signal. The sending pins of the main module and the receiving pins of all the sub-modules are connected with a first TTL bus, and the receiving pins of the main module and the sending pins of all the sub-modules are connected with a second TTL bus; a tri-state buffer is arranged between the sending pin of the main module and the first TTL bus, a tri-state buffer is respectively arranged between the sending pin of each sub-module and the second TTL bus, and the sub-modules on the communication bus are expanded through the signal enhancement function and the enabling output function of the tri-state buffer.
Description
Technical Field
The invention relates to the field of bus communication, in particular to a TTL bus communication sub-module expansion technology.
Background
The traditional communication buses have TTL standards, RS-232 standards, 485 standards and the like, but due to the reasons of hardware circuits and transmission signals of the hardware circuits and the modules, the number of sub-modules mounted on the buses is very strictly limited, for example, the 485 standard theory can only mount 256 modules at most, but in practice, due to various unavoidable circuit problems, various problems can occur when the sub-modules are mounted to more than 100 modules, and the speed needs to be reduced.
The TTL bus connection mode is as follows: the TX of the main module and the RX of the sub-module are connected on the same bus, and the RX of the main module and the TX of the sub-module are connected on the same bus. The problems are: when the master module transmits a signal via TX, the RX of each sub-module receives the signal simultaneously, but only the designated sub-module will respond. But when there are more sub-modules, the driving force of the main module TX is insufficient and the signal is too weak to allow the sub-modules to respond. In addition, the TX of the sub-module cannot be realized, because the TX defaults to a high level in an inactive state, the entire bus is always in a high level state, the signal at the TX end of the sub-module cannot be sent, the level of the bus is not low, and even the device is burned out when the bus is pulled down.
Disclosure of Invention
The invention aims to provide a TTL communication bus sub-module expansion circuit, which solves the communication mode among different modules of the most common circuit.
Without solving the technical problems, the embodiment of the invention discloses a sub-module expansion circuit of a TTL communication bus, which is characterized by comprising the following components: a first TTL bus and a second TTL bus;
a main module including a transmitting pin and a receiving pin for transmitting a request signal and receiving a feedback signal;
the sub-modules respectively comprise a sending pin and a receiving pin and are used for receiving a request signal and sending a feedback signal;
the sending pin of the main module and the receiving pins of the plurality of sub-modules are connected with the first TTL bus, and the receiving pin of the main module and the sending pin of the plurality of sub-modules are connected with the second TTL bus;
a tri-state buffer is arranged between the sending pin of the main module and the first TTL bus;
a tri-state buffer is respectively arranged between the sending pin of each sub-module and the second TTL bus;
the main module sends a request signal to the plurality of sub-modules through a tri-state buffer and the first TTL bus connected with the main module, wherein the tri-state buffer has a signal enhancement function; at most one sub-module responds and sends a feedback signal to the main module via a tri-state buffer connected with the sub-module and the second TTL bus, wherein the tri-state buffer has a tri-state output function.
In a preferred embodiment of the invention, a resistor is arranged between the second TTL bus and the power supply, which resistor is 5KΩ to 10KΩ.
In a preferred embodiment of the present invention, the enable end and the input end of the tri-state buffer connected with the main module are connected with the sending pin of the main module, and the output end is connected with the first TTL bus; the enabling end and the input end of the tri-state buffer connected with each sub-module are connected with the sending pin of each sub-module, and the output end of the tri-state buffer is connected with the second TTL bus.
In a preferred embodiment of the invention, the output of the tri-state buffer is either low or high impedance. When the input end and the enabling end are in low level, the output end is the same as the input level and presents low level; when the input terminal and the enable terminal are high level, the output terminal presents high resistance state.
Compared with the prior art, the embodiment of the invention has at least the following differences and effects:
the invention uses TTL serial bus communication, the request signal and the feedback signal are respectively and independently transmitted in two circuits, and the two circuits cannot interfere with each other, so that the transmission speed is high. And a tri-state buffer is arranged between the main module and the first TTL bus, and has the function of enhancing signals, so that the request signals can be simultaneously sent to all the sub-modules. And three-state buffers are respectively arranged between all the submodules and the second TTL bus, and have a three-state output function, so that feedback signals sent by the responding submodules can completely reach the main module and are not interfered by other submodules.
Further, a power supply and a resistor are connected to the second TTL bus, and the bus is always in a high-level state when no signal is transmitted. Only when the feedback occurs the sub-module outputs a low level, the bus level is pulled low and the signal is synchronized to the receive pin of the main module. The data transmission rate in the circuit is completely dependent on the response of the tri-state gate, the transmission delay time is short, the circuit work rate is high, and meanwhile, the tri-state gate is an active device, so that the driving of the circuit can be increased.
It is understood that within the scope of the present invention, the above-described technical features of the present invention and technical features specifically described below (as embodiments and examples) may be combined with each other to constitute new or preferred technical solutions. And are limited to a space, and are not described in detail herein.
Drawings
FIG. 1 is a schematic diagram of a TTL communication bus sub-module expansion system;
FIG. 2 is an electrical schematic of a tri-state buffer;
fig. 3 is a circuit diagram of a TTL communication bus 2 submodule extension.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, it will be understood by those skilled in the art that the claimed invention may be practiced without these specific details and with various changes and modifications from the embodiments that follow.
In the present application, some concepts are explained and exemplified:
TTL is mainly composed of BJT (Bipolar Junction Transistor ), transistor and resistor, and has the advantage of high speed.
The first TTL bus refers to a line connecting the main module transmitting pin and the plurality of sub-module receiving pins.
The second TTL bus refers to a line connecting the main module receiving pin and the plurality of sub-module transmitting pins.
The tri-state buffer, also called tri-state gate, tri-state driver, whose tri-state output is controlled by the enable output, when the enable output is active, the device implements a normal logic state output (logic 0, logic 1), when the enable input is inactive, the output is in a high resistance state, i.e. equivalent to being disconnected from the connected circuit.
TX pin, i.e. transmit pin.
RX pin, i.e. the receive pin.
Some of the innovative features of the present application are described below:
in order to solve the problem that the number of sub-modules on a bus in hardware circuit communication is limited, a method for expanding the sub-modules by using TTL bus communication is disclosed. The main module and the sub-module are communicated by using TTL serial buses, so that a request signal sent by the main module and a feedback signal sent by the sub-module are independently and parallelly transmitted, and mutual interference is avoided.
In addition, a tri-state buffer is provided as a buffer circuit at the transmitting end of each module. The tri-state buffer is an active device and has a tri-state enabling function, which can increase the driving force of the main module and realize the output feedback function of the sub-module. The enabling end and the input end of the tri-state buffer connected with the main module are connected with the sending pin of the main module, and the output end of the tri-state buffer is connected with the first TTL bus. The enabling end and the input end of the tri-state buffer connected with the sub-module are connected with the sending pin of the sub-module, the output end is connected with the second TTL bus, and the output high level or low level of the sub-module which responds can be synchronously output through the tri-state buffer. The other unresponsive submodule transmit pins are in a high impedance state and do not interfere with the bus level. The sub-modules on the bus can be extended to a sufficiently large number.
Further, in the above connection method, although a tri-state buffer is used as the tri-state buffer, the actual output is in two states of low level or high resistance. When the input end and the enabling end are in low level, the output end is the same as the input level and presents low level; when the input terminal and the enable terminal are high level, the output terminal presents high resistance state.
When the submodule does not work, the input end and the enabling end are in a high level, and the output end is in a high resistance state. At this time, the second TTL bus is connected to the power supply through the resistor, and the second TTL bus is at a high level, so that the receiving pin of the main module is at a high level.
When the submodule works, the input end and the enabling end of the tri-state buffer are low level when the submodule responds to output low level, the tri-state buffer is conducted, the output end is synchronous to low level, at the moment, the second TTL bus is pulled to low level, and the main module receives a low level signal sent by the submodule;
when the responding submodule outputs high level, the input end and the enabling end of the tri-state buffer are high level, the tri-state buffer outputs high resistance state, and at the moment, the second TTL bus is connected with the power supply through the resistor, and the second TTL bus presents high level, so that the receiving pin of the main module is high level.
Therefore, the enabling output function of the tri-state buffer can completely synchronize the output level of the submodule with which the response occurs to the receiving end of the main module, realize the circuit isolation of other submodules and further realize the expansion of the number of the submodules on the bus.
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.
The embodiment of the invention relates to a TTL communication submodule extension device. Fig. 1 is a schematic structural diagram of the system, comprising: a first TTL bus and a second TTL bus; a resistor;
a main module including a transmitting pin TX and a receiving pin RX for transmitting a request signal and receiving a feedback signal;
the sub-modules respectively comprise a sending pin TX and a receiving pin RX, and are used for receiving a request signal and sending a feedback signal;
the TX pins of the main module and the RX pins of all the sub-modules are connected with a first TTL bus, and the RX pins of the main module and the TX pins of all the sub-modules are connected with a second TTL bus; a tri-state buffer is arranged between the TX pin of the main module and the first TTL bus, the enabling end and the input end of the tri-state buffer are connected with the TX pin of the main module, and the input end of the tri-state buffer is connected with the first TTL bus; a tri-state buffer is respectively arranged between the TX pin of each sub-module and the second TTL bus, the enabling end and the input end of the tri-state buffer are connected with the TX pin of each sub-module, and the output end of the tri-state buffer is connected with the second TTL bus; one end of the resistor is connected with the second TTL bus, and the other end of the resistor is connected with a power supply.
The request signal sent by the TX pin of the main module is transferred to the RX pin of each sub-module via a tri-state buffer and a first TTL bus, wherein the tri-state buffer has an enhancement effect on the signal, and at most only one sub-module will respond when receiving the signal.
When all the sub-modules do not respond, the output pins of the sub-modules show high level, so the input end and the enabling end of the tri-state buffer are high level, and the output end is in high resistance state. At this time, the second TTL bus is connected to the power supply through the resistor, and the second TTL bus is at a high level, so that the receiving pin of the main module is at a high level.
When one of the submodules does not respond, the TX pin of the other submodule does not respond and is in a high level, and the TX pin is output to be in a high-resistance state through a tri-state buffer. The TX pin of the responding sub-module will send out a feedback signal:
when the responding submodule outputs low level, the input end and the enabling end of the tri-state buffer are low level, the tri-state buffer is conducted, the output end of the tri-state buffer is synchronous to low level, at the moment, the second TTL bus is pulled to low level, and the main module receives a low level signal sent by the submodule;
when the responding submodule outputs high level, the input end and the enabling end of the tri-state buffer are high level, the tri-state buffer outputs high resistance state, and at the moment, the second TTL bus is connected with the power supply through the resistor, and the second TTL bus presents high level, so that the receiving pin of the main module is high level.
Therefore, the enabling output function of the tri-state buffer can completely synchronize the output level of the submodule with which the response occurs to the receiving end of the main module, realize the circuit isolation of other submodules and further realize the expansion of the number of the submodules on the bus.
In one embodiment of the present invention, the electrical schematic diagram of the tri-state buffer is shown in fig. 2, and the truth table is shown in table 1:
table 1 functional table
When the OE pin is at a high level, the output Y presents a high resistance state; when the OE pin is low, the output Y is the same as the input a level.
In one embodiment of the invention, a TTL communication bus 2 sub-module expansion circuit is shown in FIG. 3. In fig. 3, when the sub-module 1 and the sub-module 2 have no data transmission, the TX pins of the sub-module 1 and the sub-module 2 are at high level, and the output is in a high-resistance state after passing through the tri-state buffer, but at this time, the RX bus is connected with a 10K pull-up 5V resistor, and at this time, the bus is in a high-level state;
when the sub-module 1 has data to send to the main module:
first, when the sub-module 2 does not transmit data, the TX pin of the sub-module 2 is high, and after passing through the tri-state buffer, the output is in a high-resistance state, so that the TX pin of the sub-module 2 does not interfere with the bus data.
Secondly, when the TX pin of the sub-module 1 is pulled high, although the output after passing through the tri-state buffer presents a high resistance state, the bus level is also high due to the pull-up resistor; when the TX pin of sub-module 1 is pulled low, the tri-state buffer is enabled, and the output of the tri-state buffer is kept consistent with the TX pin level of sub-module 1, and is also pulled low, at which time the bus level is pulled low. The bus level is exactly the same as the TX pin level of the sub-module 1, so that the sub-module 1 can send data to the main module without errors.
Since the added tri-state buffer presents a high impedance state at the OE input, no response occurs by the submodule and no disturbance is caused to the bus. Thus, an expansion in the number of sub-modules on the bus can be achieved.
It should be noted that in the present patent application, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. In the present patent application, if it is mentioned that an action is performed according to an element, it means that the action is performed at least according to the element, and two cases are included: the act is performed solely on the basis of the element and is performed on the basis of the element and other elements.
All documents mentioned in this application are incorporated by reference as if each were individually incorporated by reference. Further, it is understood that various changes or modifications of the present invention may be made by those skilled in the art after reading the above teachings, and such equivalents are intended to fall within the scope of the present application.
Claims (4)
1. A TTL communication bus sub-module expansion circuit, comprising:
a first TTL bus and a second TTL bus;
a main module including a transmitting pin and a receiving pin for transmitting a request signal and receiving a feedback signal;
the sub-modules respectively comprise a sending pin and a receiving pin and are used for receiving a request signal and sending a feedback signal;
the sending pin of the main module and the receiving pins of the plurality of sub-modules are connected with the first TTL bus, and the receiving pin of the main module and the sending pin of the plurality of sub-modules are connected with the second TTL bus;
a tri-state buffer is arranged between the sending pin of the main module and the first TTL bus;
a tri-state buffer is respectively arranged between the sending pin of each sub-module and the second TTL bus;
the main module sends a request signal to the plurality of sub-modules through a tri-state buffer and the first TTL bus connected with the main module, wherein the tri-state buffer has a signal enhancement function; at most, one sub-module responds to send a feedback signal, and the feedback signal reaches the main module through a tri-state buffer connected with the sub-module and the second TTL bus, wherein the tri-state buffer has a tri-state output function;
the enabling end and the input end of the tri-state buffer connected with the main module are connected with the sending pin of the main module, the output end of the tri-state buffer is connected with the first TTL bus, the enabling end and the input end of the tri-state buffer connected with each sub-module are connected with the sending pin of each sub-module, and the output end of the tri-state buffer is connected with the second TTL bus.
2. The TTL communication bus submodule extension circuit of claim 1, wherein a resistor is provided between the second TTL bus and the power supply.
3. The TTL communication bus submodule extension circuit of claim 2 wherein the resistance is 5kΩ to 10kΩ.
4. The TTL communication bus submodule extension circuit of claim 1 wherein the output of the tri-state buffer is either a low level or a high impedance state.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710475673.6A CN107229589B (en) | 2017-06-21 | 2017-06-21 | TTL communication bus sub-module expansion circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710475673.6A CN107229589B (en) | 2017-06-21 | 2017-06-21 | TTL communication bus sub-module expansion circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107229589A CN107229589A (en) | 2017-10-03 |
| CN107229589B true CN107229589B (en) | 2024-03-12 |
Family
ID=59936397
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710475673.6A Active CN107229589B (en) | 2017-06-21 | 2017-06-21 | TTL communication bus sub-module expansion circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107229589B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110247704A (en) * | 2018-12-28 | 2019-09-17 | 合肥工业大学 | Photoelectric conversion expanding unit and method |
| CN115499032A (en) * | 2022-09-01 | 2022-12-20 | 上海盛本智能科技股份有限公司 | One-to-many UART communication method |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2358653Y (en) * | 1997-10-29 | 2000-01-12 | 福建省漳州市双成智能技术开发应用有限公司 | Civil water, electricity, gas three-purpose meter intelligence integrated metering installation |
| CN101169773A (en) * | 2007-11-29 | 2008-04-30 | 中兴通讯股份有限公司 | Device and method for promoting system bus drive ability |
| CN102103564A (en) * | 2009-12-22 | 2011-06-22 | 中兴通讯股份有限公司 | Method and system for realizing bus connection |
| CN102901905A (en) * | 2012-11-12 | 2013-01-30 | 株洲南车时代电气股份有限公司 | Parallel bus testing device and method |
| CN103268301A (en) * | 2013-05-30 | 2013-08-28 | 华南理工大学广州学院 | Automatic-flowing half-duplex UART interface circuit |
| CN105721059A (en) * | 2016-04-06 | 2016-06-29 | 国网安徽省电力公司培训中心 | Profibus-DP photoelectric signal conversion system |
| CN207051890U (en) * | 2017-06-21 | 2018-02-27 | 上海景格信息科技有限公司 | TTL communication bus submodule expanded circuits |
-
2017
- 2017-06-21 CN CN201710475673.6A patent/CN107229589B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2358653Y (en) * | 1997-10-29 | 2000-01-12 | 福建省漳州市双成智能技术开发应用有限公司 | Civil water, electricity, gas three-purpose meter intelligence integrated metering installation |
| CN101169773A (en) * | 2007-11-29 | 2008-04-30 | 中兴通讯股份有限公司 | Device and method for promoting system bus drive ability |
| CN102103564A (en) * | 2009-12-22 | 2011-06-22 | 中兴通讯股份有限公司 | Method and system for realizing bus connection |
| CN102901905A (en) * | 2012-11-12 | 2013-01-30 | 株洲南车时代电气股份有限公司 | Parallel bus testing device and method |
| CN103268301A (en) * | 2013-05-30 | 2013-08-28 | 华南理工大学广州学院 | Automatic-flowing half-duplex UART interface circuit |
| CN105721059A (en) * | 2016-04-06 | 2016-06-29 | 国网安徽省电力公司培训中心 | Profibus-DP photoelectric signal conversion system |
| CN207051890U (en) * | 2017-06-21 | 2018-02-27 | 上海景格信息科技有限公司 | TTL communication bus submodule expanded circuits |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107229589A (en) | 2017-10-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20240086350A1 (en) | Efficient signaling scheme for high-speed ultra short reach interfaces | |
| US7269088B2 (en) | Identical chips with different operations in a system | |
| JP2013168164A5 (en) | ||
| US10198396B2 (en) | Master control board that switches transmission channel to local commissioning serial port of the master control board | |
| CN105284086A (en) | Driving data of multiple protocols through a single set of pins | |
| CN111427824B (en) | Serial port communication circuit | |
| CN105141491B (en) | RS485 communication circuit and method for realizing spontaneous self-receiving | |
| CN107229589B (en) | TTL communication bus sub-module expansion circuit | |
| JP2016004327A (en) | Transmission device | |
| CN103729333A (en) | Backplane bus structure sharing multiple channel time slots and implementation method thereof | |
| US20110219160A1 (en) | Fast two wire interface and protocol for transferring data | |
| US10346339B2 (en) | Signal path isolation for conductive circuit paths and multipurpose interfaces | |
| CN216873219U (en) | Communication circuit and multi-master communication system | |
| CN102609388B (en) | Slave node circuit, communication method and communication device | |
| CN112583401B (en) | Isolated single-wire bidirectional transmission circuit based on digital isolator | |
| KR101857088B1 (en) | Remote Input/output apparatus having return circuit and method for interfacing internal bus thereof | |
| CN209860929U (en) | Communication bus structure | |
| CN207051890U (en) | TTL communication bus submodule expanded circuits | |
| CN209118268U (en) | A kind of high robust spi bus driving circuit | |
| US20210303496A1 (en) | Actuation of data transmission lanes between states | |
| CN104978294A (en) | Compatible device of serial peripheral interface, serial peripheral interface and host device | |
| CN211826943U (en) | Communication control circuit and device | |
| CN204347831U (en) | Unidirectional RS-422 data communication system and receiving terminal | |
| US9762287B2 (en) | Crosstalk reduction in multiplexers | |
| CN114070666B (en) | Bus communication interface circuit and communication method for enhancing bus communication effect |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |