CN216873219U - Communication circuit and multi-master communication system - Google Patents
Communication circuit and multi-master communication system Download PDFInfo
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- CN216873219U CN216873219U CN202220677563.4U CN202220677563U CN216873219U CN 216873219 U CN216873219 U CN 216873219U CN 202220677563 U CN202220677563 U CN 202220677563U CN 216873219 U CN216873219 U CN 216873219U
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Abstract
The application discloses communication circuit and many owner communication system relates to communication technology field, and communication circuit includes: the circuit comprises a level conversion chip, an inverting circuit, a first pull-down resistor, a pull-up resistor and a second pull-down resistor. The driving output end of the level conversion chip is connected to the data receiving end of the control unit, and the driving input end of the level conversion chip is connected to the data sending end of the control unit; one end of the inverting circuit is connected with a data sending end of the control unit, and the other end of the inverting circuit is connected with an enabling end of the level conversion chip; one end of the first pull-down resistor is connected with the driving output end of the level conversion chip, and the other end of the first pull-down resistor is grounded; one end of the pull-up resistor is connected with the positive data end of the level conversion chip, and the other end of the pull-up resistor is connected with the power supply; one end of the second pull-down resistor is connected with the negative data terminal of the level conversion chip, and the other end of the second pull-down resistor is grounded. Therefore, the communication circuit has the self-sending and self-receiving functions, and whether the sent signal is consistent with the received signal or not can be judged.
Description
Technical Field
The present application relates to the field of communications technologies, and in particular, to a communication circuit and a multi-master communication system.
Background
A serial circuit is a circuit for transmitting and receiving bytes bitwise. It is simple and enables long-distance communication.
RS485 is a standard defined to balance the electrical characteristics of drivers and receivers in digital multipoint systems, which is defined by the telecommunications industry association and the electronics industry consortium. In the RS485 communication network, a master-slave communication mode is generally adopted, that is, one master is connected with a plurality of slaves through a serial circuit on the master and a twisted pair.
The existing RS485 communication network adopts a master-slave communication mode because a serial port circuit cannot judge whether a logic signal sent by the serial port circuit is consistent with a received logic signal.
SUMMERY OF THE UTILITY MODEL
The application discloses a communication circuit and a multi-master communication system, which can judge whether a transmitted logic signal is consistent with a received logic signal.
A first aspect of an embodiment of the present application discloses a communication circuit, including: the circuit comprises a level conversion chip, an inverting circuit, a first pull-down resistor, a pull-up resistor and a second pull-down resistor. The level conversion chip comprises a driving output end and a driving input end, wherein the driving output end is connected to a data receiving end of the control unit, and the driving input end is connected to a data sending end of the control unit; one end of the inverting circuit is connected with a data sending end of the control unit, and the other end of the inverting circuit is connected with an enabling end of the level conversion chip; one end of the first pull-down resistor is connected with the driving output end of the level conversion chip, and the other end of the first pull-down resistor is grounded; one end of the pull-up resistor is connected with the positive data end of the level conversion chip, and the other end of the pull-up resistor is connected with a power supply; and one end of the second pull-down resistor is connected with the negative data terminal of the level conversion chip, and the other end of the second pull-down resistor is grounded.
In an embodiment, the inverting circuit is a not-gate circuit, an input end of the not-gate circuit is connected to the data transmitting end, and an output end of the not-gate circuit is connected to the level conversion chip.
In one embodiment, the communication circuit further includes: and one end of the matching resistor is connected to the positive data terminal, and the other end of the matching resistor is connected to the negative data terminal.
In one embodiment, the communication circuit further includes: and one end of the transient diode is connected to the positive data terminal, and the other end of the transient diode is connected to the negative data terminal.
In an embodiment, the communication circuit further includes a first transient diode, one end of the first transient diode is connected to the negative data terminal, and the other end of the first transient diode is grounded.
In an embodiment, the communication circuit further includes a second transient diode, and one end of the second transient diode is connected to the positive data terminal, and the other end of the second transient diode is grounded.
In an embodiment, the communication circuit further includes a first isolation resistor, one end of the first isolation resistor is connected to the positive data terminal, and the other end of the first isolation resistor is connected to the RS485 bus.
In an embodiment, the communication circuit further includes a second isolation resistor, one end of the second isolation resistor is connected to the negative data terminal, and the other end of the second isolation resistor is connected to the RS485 bus.
In one embodiment, the level conversion chip is an RS485 interface chip.
A second aspect of an embodiment of the present application discloses a multi-master communication system, including: a plurality of communication devices connected to each other through an RS485 bus; and each of the communication devices comprises the communication circuit of the first aspect of the embodiments and any embodiment thereof.
Therefore, the communication circuit can receive and send by itself through the arrangement of the inverting circuit, the pull-up resistor and the second pull-down resistor, and whether the signal sent by the communication circuit is consistent with the received signal or not can be judged through the arrangement of the first pull-down resistor.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.
Fig. 1 is a block diagram of a communication circuit according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of a communication circuit according to an embodiment of the present application.
Icon:
100-level conversion chip; 101-a drive input; 102-a drive output; 103-an enable terminal; 104-negative data terminal; 105-data positive terminal; 110-an inverting circuit; 120-a first pull-down resistor; 121-pull-up resistor; 122-second pull-down resistance; 123-matching resistance; 130-transient diode.
201-data sending end; 202-data receiving end.
Detailed Description
The terms "first," "second," "third," and the like are used for descriptive purposes only and not for purposes of indicating or implying relative importance, and do not denote any order or order.
Furthermore, the terms "horizontal", "vertical", "overhang" and the like do not imply that the components are required to be absolutely horizontal or overhang, but may be slightly inclined. For example, "horizontal" merely means that the direction is more horizontal than "vertical" and does not mean that the structure must be perfectly horizontal, but may be slightly inclined.
In the description of the present application, it should be noted that the terms "inside", "outside", "left", "right", "upper", "lower", and the like indicate orientations or positional relationships based on orientations or positional relationships shown in the drawings or orientations or positional relationships that are conventionally arranged when products of the application are used, and are used only for convenience in describing the application and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the application.
In the description of the present application, unless expressly stated or limited otherwise, the terms "disposed," "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements.
The technical solution of the present application will be clearly and completely described below with reference to the accompanying drawings.
Please refer to fig. 1, which is a block diagram of a communication circuit according to an embodiment of the present disclosure. In this embodiment, the communication circuit includes: the level shift chip 100, the inverting circuit 110, the first pull-down resistor 120, the pull-up resistor 121, and the second pull-down resistor 122. The level shift chip 100 includes a driving output terminal 102 and a driving input terminal 101, the driving output terminal 102 of the level shift chip 100 is connected to the data receiving terminal 202 of the control unit, and the driving input terminal 101 thereof is connected to the data sending terminal 201 of the control unit; one end of the negation circuit 110 is connected with a data sending end 201 of the control unit, and the other end is connected with an enabling end 103 of the level conversion chip 100; one end of the first pull-down resistor 120 is connected to the driving output terminal 102 of the level shifter chip 100, and the other end is grounded; one end of the pull-up resistor 121 is connected with the positive data terminal 105 of the level shift chip 100, and the other end is connected with a power supply; one end of the second pull-down resistor 122 is connected to the negative data terminal 104 of the level shift chip 100, and the other end is grounded.
In an embodiment, the control unit may be a single chip, the data transmitting end 201 of the control unit may be a txd (transmit external data) pin, and the data receiving end 202 of the control unit may be an rxd (receive external data) pin.
In another embodiment, the control unit may also be a programmable logic controller or an electronic device such as an industrial computer or a notebook computer.
Please refer to fig. 2, which is a schematic structural diagram of a communication circuit according to an embodiment of the present application. In the present embodiment, the level converting chip 100 may be an RS-485 interface chip, and the model thereof may be SN75LBC184 or SN74AVC1T45 or other interface chips known or should be known to those skilled in the art, and is not limited thereto. The level conversion chip 100 includes: a drive input 101, i.e., a di (driver input) pin, connected to the TXD pin; a driving output terminal 102, i.e. an ro (receiver output) pin, connected to the RXD terminal; an enable terminal 103 connected to an output terminal of the negation circuit 110, wherein the enable terminal 103 includes a drive enable pin de (data enable) terminal and a receive enable pin re (receiver enable) terminal connected to each other; pin B (i.e., the data negative terminal 104) connected to the resistor R24 (i.e., the second pull-down resistor 122); pin a (i.e., data positive terminal 105) connected to resistor R20 (i.e., pull-up resistor 121). The RO pin of the level shift chip 100 is also connected to a resistor R1 (i.e., the first pull-down resistor 120). The inverting circuit 110 is a not gate circuit in the embodiment, and may be implemented by, for example, a general logic gate chip with model number SN74HC00D, or may be implemented by a corresponding circuit, which is not limited in this respect.
Further, one end of the first pull-down resistor 120 is connected to the RO pin, and the other end is grounded; one end of the pull-up resistor 121 is connected to the terminal a, and the other end is connected to a VCC power supply, which may provide a positive voltage of 5V or other voltages that can be thought of by those skilled in the art, and is not limited thereto; one end of the second pull-down resistor 122 is connected to B, and the other end is grounded.
In this embodiment, the communication circuit further includes: a resistor R21 (i.e., a matching resistor 123), two transient diodes 130, a resistor L2 (i.e., a first isolation resistor), and a resistor L3 (i.e., a second isolation resistor). One end of the resistor R21 (i.e., the matching resistor 123) is connected to the pin a, and the other end of the resistor R21 is connected to the pin B. The two transient diodes 130 are connected in series with each other, and then one end is connected to the pin a and the other end is connected to the pin B. One end of the resistor L2 is connected with the pin B, and the other end is used for connecting the RS485 bus. One end of the resistor L3 is connected with the pin A, and the other end is used for connecting the RS485 bus.
Therefore, in the present application, the inverting circuit 110 has an input terminal connected to the data transmitting terminal 201 and an output terminal connected to the enable terminal 103. When the control unit sends "logic 0" through the data sending end 201, the enable end 103 receives "logic 1" so as to enable the level conversion chip 100 to be in a sending state, and after the "logic 1" at this time is converted by the level conversion chip 100, a corresponding voltage difference is presented between the pin a and the pin B, so that the bus presents "logic 0".
When the control unit sends "logic 1" through the data sending end 201, the enable end 103 receives "logic 0", so that the level conversion chip 100 is in a receiving state, and the sending is prohibited, at this time, a positive voltage is simulated between the a end and the B end through the pull-up resistor 121 and the second pull-down resistor 122, so that the condition of sending "logic 1" is simulated between the a end and the B end, and thus the bus is in a "logic 1" state.
When the communication circuit is idle, according to a corresponding protocol, the data sending end 201 defaults to a state of "logic 1", and at this time, the enabling end 103 receives "logic 0" through the setting of the inverting circuit 110, so that the level conversion chip 100 is in a receiving state, and can receive "logic 1" or "logic 0" transmitted on the bus.
Therefore, through the arrangement of the inverting circuit 110, the pull-up resistor 121 and the second pull-down resistor 122, the communication circuit has a self-sending and self-receiving function, and since the sending of the "logic 1" is realized through the pull-up resistor 121 and the second pull-down resistor 122, when a device sends the "logic 1" and the "logic 0" simultaneously in a communication system having a plurality of communication circuits, a state of the "logic 0" is presented on the bus. Therefore, with the present communication circuit, the driving capability of transmitting "logic 0" can be made larger than the driving capability of transmitting "logic 1", that is, the priority of transmitting "logic 0" is higher than the priority of transmitting "logic 1".
In the present application, through the configuration that one end of the first pull-down resistor 120 is connected to the driving output terminal 102, and the other end is grounded, when the control unit sends "logic 0" through the data sending terminal 201, the inverting circuit 110 makes the enable terminal 103 receive "logic 1", so that the level shift chip 100 is in a sending state, and the data receiving terminal 202 at this time is disabled, but through the configuration of the first pull-down resistor 120, the control unit can receive "logic 0" through the communication circuit. If the control unit receives a signal other than a logical 0, the control unit proves that other devices on the bus are transmitting the signal.
When the control unit sends "logic 1" through its data sending end 201, the enable end 103 is enabled to receive "logic 0" through the inverting circuit 110, so that the level shift chip 100 is in a receiving state, and the data receiving end 202 is enabled at this time, so that the control unit can receive "logic 1" through the communication circuit. If the control unit does not receive a logic 1, the control unit proves that other devices on the bus are transmitting signals.
Therefore, the control unit can determine whether or not the signal it transmits matches the received signal by the setting of the first pull-down resistor 120 in the communication circuit.
An embodiment of the present application further provides a multi-master communication system, including: a plurality of communication devices connected to each other through an RS485 bus; and each communication device comprises the communication circuit of any of the embodiments described above. And the communication device that transmitted the data "logic 0" can transmit successfully when two communication means on the bus transmit data at the same time.
When a communication device in a multi-master communication system wants to implement multi-master communication, it can be implemented through steps S401 to S405:
step S401: and judging whether the bus has the data being transmitted within the preset time.
In this step, the communication device may determine whether data is received through the bus within a preset time, so as to determine whether other devices in the system are sending data, and if data being transmitted exists in the bus, the communication device does not operate, and the preset time may be 100 ms.
Step S402: if the bus does not transmit data within the preset time, the bus is declared to be occupied.
In this step, if the bus does not transmit data within the predetermined time, the communication device may send a logical 0 of several bytes, thereby declaring that the bus is occupied.
Step S403: send data and wait for a handshake.
In this step, the communication device may send corresponding data to other devices after declaring that the bus is occupied, and wait for a handshake. At this time, both the target device and the other devices in the bus can receive data, but when the other devices want to transmit data, they find that the transmitted data is not consistent with the received data, and thus cannot transmit data. And after the target device receives the data and completes the handshake, the target device sends feedback data to the communication device.
Step S404: receiving feedback data and waiting for waving hands.
In this step, after receiving the feedback data sent by the target device, the communication device may wait for the hand waving, and after finishing the hand waving action with the target device, the communication is ended.
Step S405: and sending a preset instruction and declaring the bus release.
In this step, after the communication device completes the waving of the hand with the target device, a preset instruction may be sent to declare that the bus is released. Other devices may begin transmitting the data they otherwise want to transmit upon receiving the release assertion for the bus.
In an embodiment, after the plurality of communication devices are powered on, the plurality of communication devices may generate a random delay value according to their own ID numbers, and actively report their own ID addresses after the delay. If no data report is received within 1s, the communication equipment can judge whether the ID address of the communication equipment is the minimum by inquiring all the ID addresses of the communication equipment received by the communication equipment. If the ID address of the slave is the minimum, the slave is set as the master, otherwise, the slave is set as the slave, and communication is performed.
It should be noted that the features of the embodiments in the present application may be combined with each other without conflict.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. A communication circuit, comprising:
the level conversion chip comprises a driving output end and a driving input end, wherein the driving output end is connected to a data receiving end of the control unit, and the driving input end is connected to a data sending end of the control unit;
one end of the inverting circuit is connected with the data sending end of the control unit, and the other end of the inverting circuit is connected with the enabling end of the level conversion chip;
one end of the first pull-down resistor is connected with the driving output end of the level conversion chip, and the other end of the first pull-down resistor is grounded;
one end of the pull-up resistor is connected with the positive data end of the level conversion chip, and the other end of the pull-up resistor is connected with a power supply; and the number of the first and second groups,
and one end of the second pull-down resistor is connected with the negative data terminal of the level conversion chip, and the other end of the second pull-down resistor is grounded.
2. The communication circuit according to claim 1, wherein the inverting circuit is a not-gate circuit, an input terminal of the not-gate circuit is connected to the data transmitting terminal, and an output terminal of the not-gate circuit is connected to the enable terminal of the level shift chip.
3. The communication circuit of claim 1, further comprising:
and one end of the matching resistor is connected to the positive data terminal, and the other end of the matching resistor is connected to the negative data terminal.
4. The communication circuit of claim 1, further comprising:
and one end of the transient diode is connected to the positive data terminal, and the other end of the transient diode is connected to the negative data terminal.
5. The communication circuit of claim 1, further comprising a first transient diode, wherein one end of the first transient diode is connected to the negative data terminal, and the other end of the first transient diode is connected to ground.
6. The communication circuit of claim 5, further comprising a second transient diode, wherein one end of the second transient diode is connected to the positive data terminal and the other end of the second transient diode is connected to ground.
7. The communication circuit of claim 1, further comprising:
and one end of the first isolation resistor is connected with the positive data terminal, and the other end of the first isolation resistor is used for connecting an RS485 bus.
8. The communication circuit of claim 7, further comprising:
and one end of the second isolation resistor is connected with the data negative terminal, and the other end of the second isolation resistor is used for connecting an RS485 bus.
9. The communication circuit of claim 1, wherein the level conversion chip is an RS485 interface chip.
10. A multi-master communication system, comprising:
a plurality of communication devices connected to each other through an RS485 bus; and (c) a second step of,
each of said communication devices comprising a communication circuit as claimed in any one of claims 1-9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202220677563.4U CN216873219U (en) | 2022-03-24 | 2022-03-24 | Communication circuit and multi-master communication system |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202220677563.4U CN216873219U (en) | 2022-03-24 | 2022-03-24 | Communication circuit and multi-master communication system |
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| CN216873219U true CN216873219U (en) | 2022-07-01 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115291556A (en) * | 2022-10-10 | 2022-11-04 | 山东华天电气有限公司 | Automatic lockout circuit and method for communication chip faults |
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2022
- 2022-03-24 CN CN202220677563.4U patent/CN216873219U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115291556A (en) * | 2022-10-10 | 2022-11-04 | 山东华天电气有限公司 | Automatic lockout circuit and method for communication chip faults |
| CN115291556B (en) * | 2022-10-10 | 2023-02-07 | 山东华天电气有限公司 | Automatic lockout circuit and method for communication chip faults |
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