CN107391411B - Interface circuit based on switch working mode selection - Google Patents

Interface circuit based on switch working mode selection Download PDF

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Publication number
CN107391411B
CN107391411B CN201710492697.2A CN201710492697A CN107391411B CN 107391411 B CN107391411 B CN 107391411B CN 201710492697 A CN201710492697 A CN 201710492697A CN 107391411 B CN107391411 B CN 107391411B
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pin
chip
enabled
state
low level
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CN107391411A (en
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张敏
胡奇
朱祥辉
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Shenzhen Hepai Electronics Co ltd
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Shenzhen Hepai Electronics Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4286—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a handshaking protocol, e.g. RS232C link
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0002—Serial port, e.g. RS232C
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The invention discloses an interface circuit based on switch working mode selection, which comprises a processor MCU, an isolation protection module, a mode gating module, a conversion module, a bypass protection module and a wiring terminal, wherein the processor MCU, the isolation protection module, the mode gating module, the conversion module, the bypass protection module and the wiring terminal are sequentially connected. The interface circuit based on the switch working mode selection provided by the invention can solve the defect of poor universality of the existing equipment, can use any one mode of RS232/RS485/RS422, and has strong practicability. The interface circuit of the invention has low power consumption and easy realization, adopts a chip with low power consumption, only one mode conversion chip works at the same time, and the other mode conversion chips are in a dormant state, so that the power consumption index of the whole system is hardly influenced, and the problems of the driving capability of a bus and the insufficient power supply of the system are solved.

Description

Interface circuit based on switch working mode selection
Technical Field
The invention belongs to the technical field of serial port communication, relates to an interface circuit, and particularly relates to an interface circuit based on switch working mode selection.
Background
Because serial communication is simple and practical, and is widely applied to various industrial fields, for serial communication, because various protocols such as RS232, RS485, RS422 and the like exist, to realize interconnection among devices, a user needs to be provided with different interface modules according to different protocols.
In practical application, the existing implementation methods have defects of different degrees:
(1) The existing equipment generally only supports one or two of an RS232 interface, an RS422 interface and an RS485 interface, and has poor universality;
(2) Due to the influence of the driving capability of the bus, the power supply of the system and the like, the problem of adding different interface converters at the same time is sometimes difficult to solve;
(3) The existing conversion method needs to write specific software control data flow, so that the difficulty of software development and debugging is increased;
(4) A toggle switch or a jumper is arranged in the equipment, so that the equipment shell is required to be opened for operation, and the field application is inconvenient;
(5) The requirements of the severe environment of the industrial field cannot be met.
In view of this, there is an urgent need to design a new interface circuit to overcome the above-mentioned drawbacks of the existing interface circuits.
Disclosure of Invention
The technical problems to be solved by the invention are as follows: the interface circuit based on the switch working mode selection can solve the defect of poor universality of the traditional equipment, can use any one mode of RS232/RS485/RS422, and has strong practicability.
In order to solve the technical problems, the invention adopts the following technical scheme:
an interface circuit based on switching mode selection, the interface circuit comprising: the processor MCU, the isolation protection module, the mode gating module, the conversion module, the bypass protection module and the wiring terminal are sequentially connected;
the isolation protection module is used for respectively and correspondingly connecting a receiving end MCU_RxD and a transmitting end MCU_TxD of the MCU UART interface of the processor to a processing chip U6 (ADuM 1402 ARW) of the isolation protection module, transferring transient high voltage to an electric isolation layer in the isolation interface, and protecting the interface because of high insulation resistance of the isolation layer, damaging surge current can not be generated;
the mode gating module is used for selecting a corresponding communication mode through the switch SW, the second chip U2 and the third chip U3; the mode gating module comprises a switch SW, a second chip U2 and a third chip U3;
when the first pin and the third pin of the switch SW are turned on, the RS232 mode is selected to enable the pins of the first chip U1 to beIs high level, pin->At low level, the pins TxOUT and RxOUT are enabled, i.e. the first chip U1 is activated, the pin DE of the fourth chip U4 is enabled, the RS485 output is disabled, the pin ∈4 of the fourth chip U4>If the voltage is at a high level, the RS485 receiving is not enabled, namely the fourth chip U4 is in a dormant state, and meanwhile, the pin DE of the fifth chip U5 is at a low level, and the RS485 output is not enabled, namely the fifth chip U5 is in the dormant state;
when the second pin and the third pin of the switch SW are turned on, the RS422 mode is selected to enable the pins of the first chip U1 to beIs low level, pin->At high level, neither the pin TxOUT nor the pin RxOUT is enabled, i.e. the first chip U1 is in a sleep state, the pin DE of the fourth chip U4 is at low level, the RS485 output is not enabled, pin->At the low level, the RS485 receives the enable, i.e. activates only the receive enable of the fourth chip U4, and simultaneously makes the pin DE of the fifth chip U5 at the high level, and the RS485 outputs the enable, i.e. activates only the output enable of the fifth chip U5;
when the fourth pin and the third pin of the switch SW are conducted, an RS485 mode is selected to enable the pins of the first chip U1 to be connectedIs low level, pin->At high level, neither pin TxOUT nor pin RxOUT is enabled, i.e. the first chip U1 is in sleep state, leading to pin DE and pin +.>Short circuit is altogetherMeanwhile, when the output enabling pin of the RS485 is received, the fourth chip U4 is activated to be in a half-duplex working mode, and meanwhile, the pin DE of the fifth chip U5 is at a low level, the RS485 output is not enabled, namely, the fifth chip U5 is in a dormant state;
the conversion module comprises a first chip U1, a fourth chip U4 and a fifth chip U5;
at the pin of the first chip U1Is high level, pin->In a low level state, the pins TxOUT and RxOUT are enabled; at pin->Is low level, pin->In a high level state, neither the pin TxOUT nor the pin RxOUT is enabled; at pin->Is high level, pin->In a high level state, the pin TxOUT is enabled, and the pin RxOUT is not enabled; at pin->Is low level, pin->In a low level state, the pin TxOUT is not enabled, and the pin RxOUT is enabled;
in a state that a pin DE of the fourth chip U4 is at a high level, the RS485 outputs an enable; in a state that the pin DE of the fourth chip U4 is at a low level, the RS485 output is not enabled; pins of the fourth chip U4In a high level state, the RS485 reception is not enabled; pin +.>In a low level state, RS485 receiving enables;
in a state that a pin DE of the fifth chip U5 is at a high level, the RS485 outputs an enable; in a state that the pin DE of the fifth chip U5 is at a low level, the RS485 output is not enabled; pins of the fifth chip U5In a high level state, the RS485 reception is not enabled; pin +.>In a low level state, RS485 receiving enables;
the first stage of bypass protection adopts a GDT for protection, the second stage adopts a TVS for protection, a lower clamping voltage can be obtained while a higher surge protection level is obtained, and a self-recovery fuse is adopted in the middle for decoupling, so that the GDT in front is easier to act, and the effect of releasing current is achieved; the RS422/485 signal output end is connected with two 20 omega resistors in series, so that the A end and the B end are isolated from the bus, the hardware fault of the sample machine can not influence the communication of the whole bus, the A end of the RS422/485 signal is additionally pulled, and the B end of the RS422/485 signal is additionally pulled down, so that the level of RXD presents unique high level during the period that the RS422/485 bus is not transmitted, namely, when the bus is suspended, the RS422/485 signal is not mistakenly interrupted to receive messy characters, the stability is improved, and the starting end and the tail end of the RS422/485 network transmission line are respectively connected with 1 120 omega matching resistor, so that the reflection of the transmission signal on the line is reduced;
the common anode ESD protection chip packaged by SOT23 is added on the RS232/422/485 signal line, and the electrostatic protection capability of the RS232/422/485 conversion chip, namely the first chip U1, the fourth chip U4 and the fifth chip U5 is added.
An interface circuit based on switching mode selection, the interface circuit comprising: the device comprises a processor MCU, an isolation protection module, a mode gating module, a conversion module, a bypass protection module and a wiring terminal, wherein the processor MCU, the isolation protection module, the mode gating module, the conversion module, the bypass protection module and the wiring terminal are sequentially connected.
As a preferable scheme of the invention, the isolation protection module is used for respectively and correspondingly connecting a receiving end MCU_RxD and a transmitting end MCU_TxD of the MCU UART interface of the processor to a processing chip of the isolation protection module, transferring transient high voltage to an electric isolation layer in the isolation interface, and protecting the interface because of high insulation resistance of the isolation layer without damaging surge current;
as a preferable mode of the invention, the conversion module comprises a first chip U1, a fourth chip U4 and a fifth chip U5;
at the pin of the first chip U1Is high level, pin->In a low level state, the pins TxOUT and RxOUT are enabled; at pin->Is low level, pin->In a high level state, neither the pin TxOUT nor the pin RxOUT is enabled; at pin->Is high level, pin->In a high level state, the pin TxOUT is enabled, and the pin RxOUT is not enabled; at pin->Is low level, pin->State of low levelDown, pin TxOUT is not enabled and pin RxOUT is enabled;
in a state that a pin DE of the fourth chip U4 is at a high level, the RS485 outputs an enable; in a state that the pin DE of the fourth chip U4 is at a low level, the RS485 output is not enabled; pins of the fourth chip U4In a high level state, the RS485 reception is not enabled; pin +.>In a low level state, RS485 receiving enables;
in a state that a pin DE of the fifth chip U5 is at a high level, the RS485 outputs an enable; in a state that the pin DE of the fifth chip U5 is at a low level, the RS485 output is not enabled; pins of the fifth chip U5In a high level state, the RS485 reception is not enabled; pin +.>In a low state, RS485 is enabled.
As a preferred solution of the present invention, the mode gating module is configured to select a corresponding communication mode through the switch SW, the second chip U2 and the third chip U3; the mode gating module comprises a switch SW, a second chip U2 and a third chip U3;
when the first pin and the third pin of the switch SW are turned on, the RS232 mode is selected to enable the pins of the first chip U1 to beIs high level, pin->At low level, the pins TxOUT and RxOUT are enabled, i.e. the first chip U1 is activated, the pin DE of the fourth chip U4 is enabled, the RS485 output is disabled, the pin ∈4 of the fourth chip U4>If the voltage is at a high level, the RS485 receiving is not enabled, namely the fourth chip U4 is in a dormant state, and meanwhile, the pin DE of the fifth chip U5 is at a low level, and the RS485 output is not enabled, namely the fifth chip U5 is in the dormant state;
when the second pin and the third pin of the switch SW are turned on, the RS422 mode is selected to enable the pins of the first chip U1 to beIs low level, pin->At high level, neither the pin TxOUT nor the pin RxOUT is enabled, i.e. the first chip U1 is in a sleep state, the pin DE of the fourth chip U4 is at low level, the RS485 output is not enabled, pin->At the low level, the RS485 receives the enable, i.e. activates only the receive enable of the fourth chip U4, and simultaneously makes the pin DE of the fifth chip U5 at the high level, and the RS485 outputs the enable, i.e. activates only the output enable of the fifth chip U5;
when the fourth pin and the third pin of the switch SW are conducted, an RS485 mode is selected to enable the pins of the first chip U1 to be connectedIs low level, pin->At high level, neither pin TxOUT nor pin RxOUT is enabled, i.e. the first chip U1 is in sleep state, leading to pin DE and pin +.>And the short circuit commonly receives the control of the output enabling pin of the RS485, namely activates the fourth chip U4 to be in a half-duplex working mode, and simultaneously enables the pin DE of the fifth chip U5 to be in a low level, so that the RS485 output is not enabled, namely the fifth chip U5 is in a dormant state.
As a preferred scheme of the invention, the first stage of bypass protection adopts GDT for protection, the second stage adopts TVS for protection, lower clamping voltage can be obtained while higher surge protection level is obtained, and the middle adopts self-recovery fuse for decoupling, so that the GDT in front is easier to act, and the effect of releasing current is achieved; the RS422/485 signal output end is connected with two 20 omega resistors in series, so that the A end and the B end are isolated from the bus, the hardware fault of the sample machine can not influence the communication of the whole bus, the A end of the RS422/485 signal is additionally pulled, and the B end of the RS422/485 signal is additionally pulled down, so that the level of RXD presents unique high level during the period that the RS422/485 bus is not transmitted, namely, when the bus is suspended, the RS422/485 signal is not mistakenly interrupted to receive messy characters, the stability is improved, and the starting end and the tail end of the RS422/485 network transmission line are respectively connected with 1 120 omega matching resistor, so that the reflection of the transmission signal on the line is reduced;
the common anode ESD protection chip packaged by SOT23 is added on the RS232/422/485 signal line, and the electrostatic protection capability of the RS232/422/485 conversion chip, namely the first chip U1, the fourth chip U4 and the fifth chip U5 is added.
The invention has the beneficial effects that: the interface circuit based on the switch working mode selection provided by the invention can solve the defect of poor universality of the existing equipment, can use any one mode of RS232/RS485/RS422, and has strong practicability.
The interface circuit of the invention has low power consumption and easy realization, adopts a chip with low power consumption, only one mode conversion chip works at the same time, and the other mode conversion chips are in a dormant state, so that the power consumption index of the whole system is hardly influenced, and the problems of the driving capability of a bus and the insufficient power supply of the system are solved.
The interface circuit solves the difficulty of software development and debugging, does not need to write specific software control data flow, and has the function of automatically judging the direction of the RS485 data flow.
The interface circuit solves the problem of troublesome operation, the equipment switch is external, and the 1P3T toggle switch is used, so that the on-site operation is convenient. The interface circuit of the invention adopts super-strong ESD and SURGE protection functions, and meets the requirements of industrial field severe environment.
Drawings
Fig. 1 is a schematic diagram of the interface circuit according to the present invention based on the selection of the switch operation mode.
Fig. 2 is a circuit schematic of an interface circuit according to the present invention based on switch operation mode selection.
Fig. 3 is a circuit schematic diagram of an interface circuit conversion module based on switch operation mode selection according to the present invention.
Fig. 4 is a circuit schematic diagram of an interface circuit mode gating module based on switch operation mode selection according to the present invention.
Fig. 5 is a circuit schematic diagram of an interface circuit bypass protection module based on switch operation mode selection according to the present invention.
Fig. 6 is a circuit schematic of the interface circuit connection terminal selected based on the switch operation mode according to the present invention.
Detailed Description
Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
Example 1
Referring to fig. 1, the present invention discloses an interface circuit based on switch operation mode selection, the interface circuit includes: the device comprises a processor MCU, an isolation protection module, a mode gating module, a conversion module, a bypass protection module and a wiring terminal, wherein the processor MCU, the isolation protection module, the mode gating module, the conversion module, the bypass protection module and the wiring terminal are sequentially connected.
Referring to fig. 2, the isolation protection module is configured to respectively and correspondingly connect a receiving end mcu_rxd and a transmitting end mcu_txd of the UART interface of the processor MCU to a processing chip of the isolation protection module, and transfer a transient high voltage to an electrical isolation layer in the isolation interface, so that no damaging surge current is generated due to a high insulation resistance of the isolation layer, thereby protecting the interface.
Referring to fig. 3, the conversion module includes a first chip U1, a fourth chip U4, and a fifth chip U5.
At the pin of the first chip U1Is high level, pin->In a low level state, the pins TxOUT and RxOUT are enabled; at pin->Is low level, pin->In a high level state, neither the pin TxOUT nor the pin RxOUT is enabled; at pin->Is high level, pin->In a high level state, the pin TxOUT is enabled, and the pin RxOUT is not enabled; at pin->Is low level, pin->In the low state, pin TxOUT is not enabled and pin RxOUT is enabled.
In a state that a pin DE of the fourth chip U4 is at a high level, the RS485 outputs an enable; in a state that the pin DE of the fourth chip U4 is at a low level, the RS485 output is not enabled; pins of the fourth chip U4In a high level state, the RS485 reception is not enabled; pin +.>In a low state, RS485 is enabled.
In a state that a pin DE of the fifth chip U5 is at a high level, the RS485 outputs an enable; in a state that the pin DE of the fifth chip U5 is at a low level, the RS485 output is not enabled; pins of the fifth chip U5In a high level state, the RS485 reception is not enabled; pin +.>In a low state, RS485 is enabled.
Referring to fig. 4, the mode gating module is configured to select a corresponding communication mode through the switch SW, the second chip U2 and the third chip U3; the mode gating module includes a switch SW, a second chip U2 and a third chip U3.
When the first pin and the third pin of the switch SW are turned on, the RS232 mode is selected to enable the pins of the first chip U1 to beIs high level, pin->At low level, the pins TxOUT and RxOUT are enabled, i.e. the first chip U1 is activated, the pin DE of the fourth chip U4 is enabled, the RS485 output is disabled, the pin ∈4 of the fourth chip U4>At the high level, the RS485 reception is not enabled, that is, the fourth chip U4 is in the sleep state, and the pin DE of the fifth chip U5 is at the low level, and the RS485 output is not enabled, that is, the fifth chip U5 is in the sleep state.
When the second pin and the third pin of the switch SW are turned on, the RS422 mode is selected to enable the pins of the first chip U1 to beIs low level, pin->At high level, neither the pin TxOUT nor the pin RxOUT is enabled, i.e. the first chip U1 is in a sleep state, the pin DE of the fourth chip U4 is at low level, the RS485 output is not enabled, pin->At the low level, the RS485 receives the enable, i.e. activates only the receive enable of the fourth chip U4, and simultaneously makes the pin DE of the fifth chip U5 at the high level, and the RS485 outputs the enable, i.e. activates only the output enable of the fifth chip U5.
When the fourth pin and the third pin of the switch SW are conducted, an RS485 mode is selected to enable the pins of the first chip U1 to be connectedIs low level, pin->At high level, neither pin TxOUT nor pin RxOUT is enabled, i.e. the first chip U1 is in sleep state, leading to pin DE and pin +.>And the short circuit commonly receives the control of the output enabling pin of the RS485, namely activates the fourth chip U4 to be in a half-duplex working mode, and simultaneously enables the pin DE of the fifth chip U5 to be in a low level, so that the RS485 output is not enabled, namely the fifth chip U5 is in a dormant state.
Referring to fig. 5, the first stage of the bypass protection adopts a GDT for protection, the second stage adopts a TVS for protection, a lower clamping voltage can be obtained while a higher surge protection level is obtained, and a self-recovery fuse is adopted in the middle for decoupling, so that the GDT in front is easier to act, and the effect of discharging current is achieved; the RS422/485 signal output end is connected with two 20 omega resistors in series, so that the A end and the B end are isolated from the bus, the hardware fault of the sample machine can not influence the communication of the whole bus, the A end of the RS422/485 signal is additionally pulled, the B end of the RS422/485 signal is additionally pulled down, the level of RXD presents unique high level during the period that the RS422/485 bus is not transmitted, namely, when the bus is suspended, the RS422/485 signal output end is not interrupted by mistake and is not received with messy characters, the stability is improved, and the starting end and the tail end of the RS422/485 network transmission line are respectively connected with 1 120 omega matching resistor, so that the reflection of the transmission signal on the line is reduced.
The common anode ESD protection chip packaged by SOT23 is added on the RS232/422/485 signal line, and the electrostatic protection capability of the RS232/422/485 conversion chip, namely the first chip U1, the fourth chip U4 and the fifth chip U5 is added.
Referring to fig. 6, the connection terminal used for outputting the RS232/RS485/RS422 signal is shown in fig. 6, and other structures may be used.
In summary, the interface circuit based on the switch working mode selection provided by the invention can solve the defect of poor universality of the existing equipment, can use any mode of RS232/RS485/RS422, and has strong practicability.
The interface circuit of the invention has low power consumption and easy realization, adopts a chip with low power consumption, only one mode conversion chip works at the same time, and the other mode conversion chips are in a dormant state, so that the power consumption index of the whole system is hardly influenced, and the problems of the driving capability of a bus and the insufficient power supply of the system are solved.
The interface circuit solves the difficulty of software development and debugging, does not need to write specific software control data flow, and has the function of automatically judging the direction of the RS485 data flow.
The interface circuit solves the problem of troublesome operation, the equipment switch is external, and the 1P3T toggle switch is used, so that the on-site operation is convenient. The interface circuit of the invention adopts super-strong ESD and SURGE protection functions, and meets the requirements of industrial field severe environment.
The description and applications of the present invention herein are illustrative and are not intended to limit the scope of the invention to the embodiments described above. Variations and modifications of the embodiments disclosed herein are possible, and alternatives and equivalents of the various components of the embodiments are known to those of ordinary skill in the art. It will be clear to those skilled in the art that the present invention may be embodied in other forms, structures, arrangements, proportions, and with other assemblies, materials, and components, without departing from the spirit or essential characteristics thereof. Other variations and modifications of the embodiments disclosed herein may be made without departing from the scope and spirit of the invention.

Claims (4)

1. An interface circuit based on switching mode selection, the interface circuit comprising: the processor MCU, the isolation protection module, the mode gating module, the conversion module, the bypass protection module and the wiring terminal are sequentially connected;
the isolation protection module is used for respectively and correspondingly connecting a receiving end MCU_RxD and a transmitting end MCU_TxD of the UART interface of the MCU processor to a four-way digital isolator chip U6 of the isolation protection module, and transferring transient high voltage to an electric isolation layer in the isolation interface, so that damaging surge current is not generated due to high insulation resistance of the isolation layer, and the function of protecting the interface is achieved;
the mode gating module is used for selecting a corresponding communication mode through the switch SW, the second chip U2 and the third chip U3; the mode gating module comprises a switch SW, a second chip U2 and a third chip U3;
when the first pin and the third pin of the switch SW are turned on, an RS232 mode is selected, so that the pin SHDN (- - - -) of the first chip U1 is at a high level, the pin EN (- - - -) is at a low level, both the pin TxOUT and the pin RxOUT are enabled, that is, the first chip U1 is activated, the pin DE of the fourth chip U4 is at a low level, the RS485 output is disabled, the pin RE (- - -) of the fourth chip U4 is at a high level, the RS485 is disabled, that is, the fourth chip U4 is in a sleep state, and the pin DE of the fifth chip U5 is at a low level, and the RS485 output is disabled, that is, the fifth chip U5 is in a sleep state;
when the second pin and the third pin of the switch SW are turned on, an RS422 mode is selected, so that the pin SHDN (- - - -) of the first chip U1 is at a low level, the pin EN (- - - -) is at a high level, and neither the pin TxOUT nor the pin RxOUT is enabled, i.e., the first chip U1 is in a sleep state, and the pin DE of the fourth chip U4 is at a low level, and the RS485 output is disabled, and the pin RE (- - - -) is at a low level, and the RS485 receives the enable, i.e., only activates the receiving enable of the fourth chip U4, and simultaneously, the pin DE of the fifth chip U5 is at a high level, and the RS485 output enables, i.e., only activates the output enable of the fifth chip U5;
when the fourth pin and the third pin of the switch SW are conducted, an RS485 mode is selected, so that the pin SHDN (- - - -) of the first chip U1 is low level, the pin EN (- - - -) is high level, the pin TxOUT and the pin RxOUT are not enabled, namely the first chip U1 is in a dormant state, the pin DE and the pin RE (- - -) of the fourth chip U4 are in short circuit and are commonly controlled by the output enabling pin of the RS485, namely the fourth chip U4 is activated, and is in a half-duplex working mode, and meanwhile, the pin DE of the fifth chip U5 is low level, the RS485 output is not enabled, namely the fifth chip U5 is in the dormant state;
the conversion module comprises a first chip U1, a fourth chip U4 and a fifth chip U5;
in the state that the pin SHDN (- - - -) of the first chip U1 is high and the pin EN (- - -) is low, both the pins TxOUT and RxOUT are enabled; in the state that pin SHDN (- - - -) is low and pin EN (- - -) is high, neither pin TxOUT nor pin RxOUT is enabled; in the state that the pin SHDN (- - - -) is high and the pin EN (- - -) is high, the pin TxOUT is enabled and the pin RxOUT is not enabled; when the pin SHDN (- - - -) is low and the pin EN (- - -) is low, the pin TxOUT is not enabled and the pin RxOUT is enabled;
in a state that a pin DE of the fourth chip U4 is at a high level, the RS485 outputs an enable; in a state that the pin DE of the fourth chip U4 is at a low level, the RS485 output is not enabled; in a state that the pin RE (- - - -) of the fourth chip U4 is at a high level, the RS485 reception is not enabled; in a state that the pin RE (- - - -) of the fourth chip U4 is at a low level, the RS485 receives the enable;
in a state that a pin DE of the fifth chip U5 is at a high level, the RS485 outputs an enable; in a state that the pin DE of the fifth chip U5 is at a low level, the RS485 output is not enabled; in a state that the pin RE (- - - -) of the fifth chip U5 is at a high level, the RS485 reception is not enabled; in a state that the pin RE (- - - -) of the fifth chip U5 is at a low level, the RS485 receives the enable;
the first stage of bypass protection adopts a GDT for protection, the second stage adopts a TVS for protection, a lower clamping voltage can be obtained while a higher surge protection level is obtained, and a self-recovery fuse is adopted in the middle for decoupling, so that the GDT in front is easier to act, and the effect of releasing current is achieved; the RS422/485 signal output end is connected with two 20 omega resistors in series, so that the A end and the B end are isolated from the bus, the hardware fault of the sample machine can not influence the communication of the whole bus, the A end of the RS422/485 signal is additionally pulled, and the B end of the RS422/485 signal is additionally pulled down, so that the level of RXD presents unique high level during the period that the RS422/485 bus is not transmitted, namely, when the bus is suspended, the RS422/485 signal is not mistakenly interrupted to receive messy characters, the stability is improved, and the starting end and the tail end of the RS422/485 network transmission line are respectively connected with 1 120 omega matching resistor, so that the reflection of the transmission signal on the line is reduced;
the common anode ESD protection chip packaged by SOT23 is added on the RS232/422/485 signal line, and the electrostatic protection capability of the RS232/422/485 conversion chip, namely the first chip U1, the fourth chip U4 and the fifth chip U5 is added.
2. An interface circuit based on switching mode selection, the interface circuit comprising: the processor MCU, the isolation protection module, the mode gating module, the conversion module, the bypass protection module and the wiring terminal are sequentially connected;
the conversion module comprises a first chip U1, a fourth chip U4 and a fifth chip U5;
in the state that the pin SHDN (- - - -) of the first chip U1 is high and the pin EN (- - -) is low, both the pins TxOUT and RxOUT are enabled; in the state that pin SHDN (- - - -) is low and pin EN (- - -) is high, neither pin TxOUT nor pin RxOUT is enabled; in the state that the pin SHDN (- - - -) is high and the pin EN (- - -) is high, the pin TxOUT is enabled and the pin RxOUT is not enabled; when the pin SHDN (- - - -) is low and the pin EN (- - -) is low, the pin TxOUT is not enabled and the pin RxOUT is enabled;
in a state that a pin DE of the fourth chip U4 is at a high level, the RS485 outputs an enable; in a state that the pin DE of the fourth chip U4 is at a low level, the RS485 output is not enabled; in a state that the pin RE (- - - -) of the fourth chip U4 is at a high level, the RS485 reception is not enabled; in a state that the pin RE (- - - -) of the fourth chip U4 is at a low level, the RS485 receives the enable;
in a state that a pin DE of the fifth chip U5 is at a high level, the RS485 outputs an enable; in a state that the pin DE of the fifth chip U5 is at a low level, the RS485 output is not enabled; in a state that the pin RE (- - - -) of the fifth chip U5 is at a high level, the RS485 reception is not enabled; in a state that the pin RE (- - - -) of the fifth chip U5 is at a low level, the RS485 receives the enable;
the isolation protection module is used for respectively and correspondingly connecting a receiving end MCU_RxD and a transmitting end MCU_TxD of the MCU UART interface of the processor to a processing chip of the isolation protection module, and transferring the transient high voltage to an electric isolation layer in the isolation interface, so that damaging surge current can not be generated due to the high insulation resistance of the isolation layer, and the function of protecting the interface is achieved.
3. The switching mode selection based interface circuit of claim 2, wherein:
the mode gating module is used for selecting a corresponding communication mode through the switch SW, the second chip U2 and the third chip U3; the mode gating module comprises a switch SW, a second chip U2 and a third chip U3;
when the first pin and the third pin of the switch SW are turned on, an RS232 mode is selected, so that the pin SHDN (- - - -) of the first chip U1 is at a high level, the pin EN (- - - -) is at a low level, both the pin TxOUT and the pin RxOUT are enabled, that is, the first chip U1 is activated, the pin DE of the fourth chip U4 is at a low level, the RS485 output is disabled, the pin RE (- - -) of the fourth chip U4 is at a high level, the RS485 is disabled, that is, the fourth chip U4 is in a sleep state, and the pin DE of the fifth chip U5 is at a low level, and the RS485 output is disabled, that is, the fifth chip U5 is in a sleep state;
when the second pin and the third pin of the switch SW are turned on, an RS422 mode is selected, so that the pin SHDN (- - - -) of the first chip U1 is at a low level, the pin EN (- - - -) is at a high level, and neither the pin TxOUT nor the pin RxOUT is enabled, i.e., the first chip U1 is in a sleep state, and the pin DE of the fourth chip U4 is at a low level, and the RS485 output is disabled, and the pin RE (- - - -) is at a low level, and the RS485 receives the enable, i.e., only activates the receiving enable of the fourth chip U4, and simultaneously, the pin DE of the fifth chip U5 is at a high level, and the RS485 output enables, i.e., only activates the output enable of the fifth chip U5;
when the fourth pin and the third pin of the switch SW are turned on, an RS485 mode is selected, so that the pin SHDN (- - - -) of the first chip U1 is at a low level, the pin EN (- - - -) is at a high level, and neither the pin TxOUT nor the pin RxOUT is enabled, i.e., the first chip U1 is in a sleep state, and the pin DE and the pin RE (- - -) of the fourth chip U4 are shorted together controlled by the output enable pin of the RS485, i.e., the fourth chip U4 is activated, and is in a half duplex working mode, and meanwhile, the pin DE of the fifth chip U5 is at a low level, and the RS485 output is disabled, i.e., the fifth chip U5 is in a sleep state.
4. The switching mode selection based interface circuit of claim 2, wherein:
the first stage of bypass protection adopts a GDT for protection, the second stage adopts a TVS for protection, a lower clamping voltage can be obtained while a higher surge protection level is obtained, and a self-recovery fuse is adopted in the middle for decoupling, so that the GDT in front is easier to act, and the effect of releasing current is achieved; the RS422/485 signal output end is connected with two 20 omega resistors in series, so that the A end and the B end are isolated from the bus, the hardware fault of the sample machine can not influence the communication of the whole bus, the A end of the RS422/485 signal is additionally pulled, and the B end of the RS422/485 signal is additionally pulled down, so that the level of RXD presents unique high level during the period that the RS422/485 bus is not transmitted, namely, when the bus is suspended, the RS422/485 signal is not mistakenly interrupted to receive messy characters, the stability is improved, and the starting end and the tail end of the RS422/485 network transmission line are respectively connected with 1 120 omega matching resistor, so that the reflection of the transmission signal on the line is reduced;
the common anode ESD protection chip packaged by SOT23 is added on the RS232/422/485 signal line, and the electrostatic protection capability of the RS232/422/485 conversion chip, namely the first chip U1, the fourth chip U4 and the fifth chip U5 is added.
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