CN107229589A - TTL communication bus submodule expanded circuits - Google Patents
TTL communication bus submodule expanded circuits Download PDFInfo
- Publication number
- CN107229589A CN107229589A CN201710475673.6A CN201710475673A CN107229589A CN 107229589 A CN107229589 A CN 107229589A CN 201710475673 A CN201710475673 A CN 201710475673A CN 107229589 A CN107229589 A CN 107229589A
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- submodule
- ttl
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- buses
- primary module
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- 238000004891 communication Methods 0.000 title claims abstract description 25
- 230000005540 biological transmission Effects 0.000 claims abstract description 24
- 230000002708 enhancing effect Effects 0.000 claims abstract description 4
- 230000003111 delayed effect Effects 0.000 claims 1
- 238000000034 method Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000007717 exclusion Effects 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4086—Bus impedance matching, e.g. termination
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0002—Serial port, e.g. RS232C
Abstract
The present invention relates to bus communication field, a kind of TTL communication buses submodule expanded circuit is disclosed, including：TTL buses；Three state buffer；Primary module, including send pin and receive pin, for sending request signal and receiving feedback signal；Multiple submodule, respectively including sending pin and receiving pin, for receiving request signal and sending feedback signals.The transmission pin of primary module and the reception pin of all submodules are connected with the first TTL buses, and the reception pin of primary module and the transmission pin of all submodules are connected with the 2nd TTL buses；Three state buffer is provided between the transmission pin and the first TTL buses of primary module, three state buffer is respectively arranged between the transmission pin and the 2nd TTL buses of each submodule, extension of the output function realization to submodule on communication bus is acted on and enable by the signal enhancing of three state buffer.
Description
Technical field
The present invention relates to bus communication field, more particularly to TTL bus communications submodule expansion technique.
Background technology
Traditional communication bus has TTL standards, rs-232 standard, 485 standards etc., but be due to hardware circuit and itself
The reason for transmitting signal, has very strict limitation, such as 485 standard theories most for submodule quantity of the carry in bus
More can only 256 modules of carry, it is but actual due to a variety of inevitable circuit problems, be mounted to more than 100 and just occur
Various problems, and need to reduce speed.
It is using TTL bus connecting modes：The TX of primary module and the RX of submodule are connected in same bus, primary module
RX and the TX of submodule be connected in same bus.The problem of existing has：When primary module sends signal by TX, each height
The RX of module receives signal simultaneously, but the submodule only specified can be responded.But when submodule is more, primary module TX
Driving force not enough, signal is too weak to be insufficient to allow submodule to respond.In addition, the TX of submodule can not be realized, because TX exists
Off position is defaulted as high level, so whole bus is in high level state all the time, the signal at submodule TX ends can not be sent out
Send, the level of the bus can not be dragged down, or even burn out device when dragging down.
The content of the invention
It is an object of the invention to provide a kind of TTL communication buses submodule expanded circuit, solve in the most frequently used electricity
Communication modes between the disparate modules of road.
Unresolved above-mentioned technical problem, embodiments of the present invention disclose a kind of TTL communication buses submodule extension electricity
Road, it is characterised in that including：First TTL buses and the 2nd TTL buses；
Primary module, including send pin and receive pin, for sending request signal and receiving feedback signal；
Multiple submodule, respectively including sending pin and receiving pin, for receiving request signal and sending feedback signal；
The transmission pin of the primary module and the reception pin of the multiple submodule are connected with the first TTL buses,
The reception pin of the primary module and the transmission pin of the multiple submodule are connected with the 2nd TTL buses；
Three state buffer is provided between the transmission pin of the primary module and the first TTL buses；
Three state buffer is respectively arranged between the transmission pin and the 2nd TTL buses of each submodule；
The primary module sends request signal, three state buffer and the first TTL buses through being connected with the primary module
The multiple submodule is reached, the three state buffer has signal enhancing effect；Be up to one submodule is responded, hair
Feedback signal is sent, three state buffer and the 2nd TTL buses through being connected with the submodule reach the primary module, described three
State buffer has ternary output function.
In the present invention in a preference, resistance is provided between the 2nd TTL buses and power supply, the resistance is 5K Ω
To 10K Ω.
In the present invention in a preference, Enable Pin and the input connection for the three state buffer being connected with primary module
The transmission pin of the primary module, output end connects the first TTL buses；The enable for the three state buffer being connected with each submodule module
End and input connect the transmission pin of each submodule, and output end connects the 2nd TTL buses.
In the present invention in a preference, the output of three state buffer is low level or high-impedance state.Work as input
During with Enable Pin for low level, output end is identical with incoming level, and low level is presented；When input and Enable Pin are high level
When, high-impedance state is presented in output end.
Embodiment of the present invention compared with prior art, at least with following difference and effect：
The present invention uses TTL serial bus communications, and request signal and feedback signal are separately passed in two circuits
It is defeated, it will not interfere, transmission speed is fast.Three state buffer is set between primary module and the first TTL buses, with enhancing letter
Number effect, enable request signal while sending to all submodules.Set respectively between all submodules and the 2nd TTL buses
Three state buffer is put, with ternary output function, the feedback signal that the submodule responded is sent is completely arrived at master
Module, and do not disturbed by other submodules.
Further, power supply and resistance are connected with the 2nd TTL buses, when no signal is transmitted, bus is in all the time
High level state.Only when the submodule fed back exports low level, bus level is pulled low, and signal is synchronized to primary module
Reception pin.Message transmission rate depends entirely on the response of triple gate in circuit, and the propagation delay time is short, circuit work speed
Rate is high, while triple gate is active device, can increase the driving of circuit.
It is appreciated that within the scope of the present invention, above-mentioned each technical characteristic of the invention and below (such as embodiment and
Example) in specifically describe each technical characteristic between can be combined with each other, so as to constitute new or preferred technical scheme.Limit
In length, no longer tire out one by one state herein.
Brief description of the drawings
Fig. 1 is the structural representation that TTL communication buses submodule extends system；
Fig. 2 is the electrical schematic diagram of three state buffer；
Fig. 3 is 2 submodule expanded circuit figures of TTL communication buses.
Embodiment
In the following description, in order that reader more fully understands the application and proposes many ins and outs.But, this
Even if the those of ordinary skill in field is appreciated that many variations without these ins and outs and based on following embodiment
And modification, the application technical scheme claimed can also be realized.
In the application documents of the application, part concept explanation and citing：
TTL refers to main by BJT (Bipolar Junction Transistor i.e. bipolar junction transistor), the pole of crystal three
Pipe and resistance are constituted, with fireballing feature.
First TTL buses, refer to the circuit that connection primary module sends pin and multiple submodule reception pin.
2nd TTL buses, refer to the circuit that connection primary module receives pin and multiple submodule transmission pin.
Three state buffer, also known as triple gate, three-state driver, its ternary output are controlled by output end is enabled, when
When enable output is effective, device realizes normal logic state output (logical zero, logic 1), when enable input is invalid, at output
In high-impedance state, that is, it is equivalent to and is disconnected with connected circuit.
TX pins, that is, send pin.
RX pins, that is, receive pin.
The part innovative point of the application is illustrated below：
In order to solve the problem of submodule quantity is restricted in bus in hardware circuit communication, disclose one kind and use
The method that TTL bus communications extend to submodule.TTL serial bus communications are used between primary module and submodule so that main mould
The feedback signal independent parallel transmission that the request signal and submodule that block is sent are sent, will not produce and interfere with each other
In addition, the transmitting terminal in each module is provided with three state buffer as buffer circuit.Three state buffer is active device
Part, with three-state enable function, can increase the driving force of primary module, and realize the output feedback function of submodule.With master
The Enable Pin and input of the three state buffer of module connection connect the transmission pin of the primary module, and output end connects the first TTL
Bus.The Enable Pin and input for the three state buffer being connected with submodule connect the transmission pin of the submodule, and output end connects
The 2nd TTL buses are connect, the submodule output high level or low level responded can be through three state buffer synchronism output.
It is high-impedance state that other submodules not responded, which send pin, without interference with bus level.Therefore submodule can extend in bus
To sufficiently large quantity.
Further, although three state buffer uses three state buffer in above-mentioned connected mode, but actual defeated
Go out is low level or high-impedance state two states.When input and Enable Pin are low level, output end is identical with incoming level,
Low level is presented；When input and Enable Pin are high level, high-impedance state is presented in output end.
When submodule does not work, input and Enable Pin are high level, and output is in high-impedance state.Now due to second
TTL buses connect through resistance and are connected with power supply, and high level is presented in the 2nd TTL buses, so the reception pin of primary module is height
Level.
When submodule works, during the submodule output low level responded, the input and enable of three state buffer
Hold as low level, three state buffer conducting, output end is synchronously low level, now the 2nd TTL buses are pulled to low level, main
Module receives the low level signal of submodule transmission；
During the submodule output high level responded, the input and Enable Pin of three state buffer are high level, tri-state
Buffer exports high-impedance state, is now connected because the 2nd TTL buses connect through resistance with power supply, and the 2nd TTL buses present high
Level, so the reception pin of primary module is high level.
Therefore, the enable output function of three state buffer can be by the output level Complete Synchronization of the submodule responded
To the receiving terminal of primary module, and the circuit isolation to other submodules is realized, further realized to submodule quantity in bus
Extension.
To make the object, technical solutions and advantages of the present invention clearer, the implementation below in conjunction with accompanying drawing to the present invention
Mode is described in further detail.
Embodiments of the present invention are related to a kind of TTL communications submodule expanding unit.Fig. 1 is the structural representation of the system
Figure, including：First TTL buses and the 2nd TTL buses；Resistance；
Primary module, including send pin TX and receive pin RX, for sending request signal and receiving feedback signal；
Multiple submodule, respectively including sending pin TX and receiving pin RX, feeds back for receiving request signal and sending
Signal；
Wherein, the TX pins of primary module and the RX pins of all submodules are connected with the first TTL buses, the RX pipes of primary module
The TX pins of pin and all submodules are connected with the 2nd TTL buses；Set between the TX pins and the first TTL buses of primary module
There is three state buffer, the Enable Pin and input of three state buffer connect the TX pins of primary module, and it is total that input connects the first TTL
Line；Be respectively arranged with three state buffer between the TX pins and the 2nd TTL buses of each submodule, the Enable Pin of three state buffer and
Input connects the TX pins of each submodule, and output end connects the 2nd TTL buses；One end of resistance is connected with the 2nd TTL buses,
The other end connects power supply.
The request signal that primary module TX pins are sent is sent to the RX of each submodule through three state buffer and the first TTL buses
Pin, the wherein three state buffer have humidification to signal, and all submodules receive most only one of which submodules during the signal
Block can be responded.
When all submodules are not all responded to, high level is presented in the output pin of each submodule, so three state buffer
Input and Enable Pin be high level, output is in high-impedance state.Now due to the 2nd TTL buses connect through resistance with
Power supply is connected, and high level is presented in the 2nd TTL buses, so the reception pin of primary module is high level.
When one of respond, other submodule TX pins not responded are high level, slow through tri-state
Rush device and be output as high-impedance state.The TX pins of the submodule of the response can send a feedback signal：
During the submodule output low level responded, the input and Enable Pin of three state buffer are low level, tri-state
Buffer is turned on, and output end is synchronously low level, and now the 2nd TTL buses are pulled to low level, and primary module receives submodule
The low level signal of transmission；
During the submodule output high level responded, the input and Enable Pin of three state buffer are high level, tri-state
Buffer exports high-impedance state, is now connected because the 2nd TTL buses connect through resistance with power supply, and the 2nd TTL buses present high
Level, so the reception pin of primary module is high level.
Therefore, the enable output function of three state buffer can be by the output level Complete Synchronization of the submodule responded
To the receiving terminal of primary module, and the circuit isolation to other submodules is realized, further realized to submodule quantity in bus
Extension.
In one embodiment of the invention, the electrical schematic diagram of three state buffer is as shown in Fig. 2 the truth table such as institute of table 1
Show：
The menu of table 1
Wherein, when OE pin are high level, output Y shows high-impedance state；When OE pin are low level, output Y and input A
Level is identical.
In one embodiment of the invention, 2 submodule expanded circuits of TTL communication buses are as shown in Figure 3.In figure 3,
When submodule 1 and submodule 2 are sent without data, the TX pins of submodule 1 and submodule 2 are high level, slow by tri-state
Rush output after device and be presented high-impedance state, but now due to having connect 10K pull-up 5V resistance in RX buses, now bus is presented
High level state；
When submodule 1 has data to be sent to primary module:
First, when submodule 2 is sent without data, because the TX pins of submodule 2 are high level, by three state buffer
Afterwards, high-impedance state is presented in output, therefore, and the TX pins of submodule 2 will not produce interference to bus data.
Secondly, when the TX pins of submodule 1 are drawn high, although high-impedance state is presented by the output after three state buffer, but
It is due to pull-up resistor, bus level is also height；When the TX pins of submodule 1 are dragged down, three state buffer is enabled, Three-State
The output end of device and the TX pin level of submodule 1 are consistent, and are also pulled low, now, bus level is pulled low.Bus level
TX pin level with submodule 1 is completely the same, therefore data can be accurately sent to primary module by submodule 1.
Because increased Three-State is when OE inputs are high level, high-impedance state is presented in output, therefore submodule does not have
When responding, any interference will not be caused to bus.It is thereby achieved that in bus submodule quantity extension.
It should be noted that in the application documents of this patent, such as first and second or the like relational terms are only
For an entity or operation are made a distinction with another entity or operation, and not necessarily require or imply these entities
Or there is any this actual relation or order between operation.Moreover, term " comprising ", "comprising" or its any other
Variant is intended to including for nonexcludability, so that process, method, article or equipment including a series of key elements are not only
Including those key elements, but also other key elements including being not expressly set out, or also include being this process, method, thing
Product or the intrinsic key element of equipment.In the absence of more restrictions, the key element limited by sentence " including one ", not
Also there is other identical element in the process including the key element, method, article or equipment in exclusion.The application of this patent
In file, if it is mentioned that perform certain behavior according to certain key element, then refer to the meaning that the behavior is performed according at least to the key element, wherein
Include two kinds of situations：The behavior is performed according only to the key element and the behavior is performed according to the key element and other key elements.
All documents referred in the present invention are all incorporated as reference in this application, independent just as each document
It is incorporated as with reference to such.In addition, it is to be understood that after the above-mentioned instruction content of the present invention has been read, those skilled in the art can
To be made various changes or modifications to the present invention, these equivalent form of values equally fall within the application scope claimed.
Claims (6)
1. a kind of TTL communication buses submodule expanded circuit, it is characterised in that including：
First TTL buses and the 2nd TTL buses；
Primary module, including send pin and receive pin, for sending request signal and receiving feedback signal；
Multiple submodule, respectively including sending pin and receiving pin, for receiving request signal and sending feedback signal；
The transmission pin of the primary module and the reception pin of the multiple submodule are connected with the first TTL buses, described
The reception pin of primary module and the transmission pin of the multiple submodule are connected with the 2nd TTL buses；
Three state buffer is provided between the transmission pin of the primary module and the first TTL buses；
Three state buffer is respectively arranged between the transmission pin and the 2nd TTL buses of each submodule；
The primary module sends request signal, and three state buffer and the first TTL buses through being connected with the primary module are reached
The multiple submodule, the three state buffer has signal enhancing effect；Be up to one submodule is responded, and sends anti-
Feedback signal, three state buffer and the 2nd TTL buses through being connected with the submodule reach the primary module, and the tri-state is delayed
Rushing utensil has ternary output function.
2. TTL communication buses submodule expanded circuit according to claim 1, it is characterised in that the 2nd TTL buses
Resistance is provided between power supply.
3. the TTL communication bus submodule expanded circuits according to right wants 2, it is characterised in that the resistance be 5K Ω extremely
10KΩ。
4. the TTL communication bus submodule expanded circuits according to right wants 1, it is characterised in that be connected with the primary module
Three state buffer Enable Pin and input connect the transmission pin of the primary module, it is total that output end connects the first TTL
Line.
5. the TTL communication bus submodule expanded circuits according to right wants 1, it is characterised in that connect with each submodule module
The Enable Pin and input of the three state buffer connect connect the transmission pin of each submodule, output end connection described second
TTL buses.
6. the TTL communication bus submodule expanded circuits according to right wants 1, it is characterised in that the three state buffer
Output is low level or high-impedance state.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710475673.6A CN107229589B (en) | 2017-06-21 | 2017-06-21 | TTL communication bus sub-module expansion circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710475673.6A CN107229589B (en) | 2017-06-21 | 2017-06-21 | TTL communication bus sub-module expansion circuit |
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| Publication Number | Publication Date |
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| CN107229589A true CN107229589A (en) | 2017-10-03 |
| CN107229589B CN107229589B (en) | 2024-03-12 |
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| CN201710475673.6A Active CN107229589B (en) | 2017-06-21 | 2017-06-21 | TTL communication bus sub-module expansion circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110247704A (en) * | 2018-12-28 | 2019-09-17 | 合肥工业大学 | Photoelectric conversion expanding unit and method |
| CN115499032A (en) * | 2022-09-01 | 2022-12-20 | 上海盛本智能科技股份有限公司 | One-to-many UART communication method |
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| CN207051890U (en) * | 2017-06-21 | 2018-02-27 | 上海景格信息科技有限公司 | TTL communication bus submodule expanded circuits |
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| CN2358653Y (en) * | 1997-10-29 | 2000-01-12 | 福建省漳州市双成智能技术开发应用有限公司 | Civil water, electricity, gas three-purpose meter intelligence integrated metering installation |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110247704A (en) * | 2018-12-28 | 2019-09-17 | 合肥工业大学 | Photoelectric conversion expanding unit and method |
| CN115499032A (en) * | 2022-09-01 | 2022-12-20 | 上海盛本智能科技股份有限公司 | One-to-many UART communication method |
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| Publication number | Publication date |
|---|---|
| CN107229589B (en) | 2024-03-12 |
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