CN207051890U - TTL communication bus submodule expanded circuits - Google Patents
TTL communication bus submodule expanded circuits Download PDFInfo
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- CN207051890U CN207051890U CN201720726926.8U CN201720726926U CN207051890U CN 207051890 U CN207051890 U CN 207051890U CN 201720726926 U CN201720726926 U CN 201720726926U CN 207051890 U CN207051890 U CN 207051890U
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Abstract
Bus communication field is the utility model is related to, discloses a kind of TTL communication buses submodule expanded circuit, including：TTL buses；Three state buffer；Primary module, including send pin and receive pin, for sending request signal and receiving feedback signal；Multiple submodule, include sending pin respectively and receive pin, for receiving request signal and sending feedback signals.The transmission pin of primary module and the reception pin of all submodules are connected with the first TTL buses, and the reception pin of primary module and the transmission pin of all submodules are connected with the 2nd TTL buses；Three state buffer is provided between the transmission pin of primary module and the first TTL buses, three state buffer is respectively arranged between the transmission pin of each submodule and the 2nd TTL buses, extension of the output function realization to submodule on communication bus is acted on and enable by the signal enhancing of three state buffer.
Description
Technical field
It the utility model is related to bus communication field, more particularly to TTL bus communications submodule expansion technique.
Background technology
Traditional communication bus has TTL standards, rs-232 standard, 485 standards etc., but due to hardware circuit and in itself
The reason for transmission signal, there is very strict limitation for submodule quantity of the carry in bus, such as 485 standard theories are most
More can only 256 modules of carry, it is but actual due to a variety of inevitable circuit problems, be mounted to more than 100 and just occur
Various problems, and need to reduce speed.
It is using TTL bus connecting modes：The TX of primary module and the RX of submodule are connected in same bus, primary module
RX and the TX of submodule be connected in same bus.The problem of existing has：When primary module sends signal by TX, each height
The RX of module reception signals, but the submodule only specified can respond simultaneously.But when submodule is more, primary module TX
Driving force it is inadequate, signal is too weak to be insufficient to allow submodule to respond.In addition, the TX of submodule can not be realized, because TX exists
Off position is defaulted as high level, so whole bus is in high level state all the time, the signal at submodule TX ends can not be sent out
Send, the level of the bus can not drag down, or even burn out device when dragging down.
Utility model content
The purpose of this utility model is to provide a kind of TTL communication buses submodule expanded circuit, solved the most frequently used
Circuit disparate modules between communication modes.
Unresolved above-mentioned technical problem, embodiment of the present utility model disclose a kind of TTL communication buses submodule and expanded
Open up circuit, it is characterised in that including：First TTL buses and the 2nd TTL buses；
Primary module, including send pin and receive pin, for sending request signal and receiving feedback signal；
Multiple submodule, include sending pin respectively and receive pin, for receiving request signal and sending feedback signal；
The transmission pin of the primary module and the reception pin of the multiple submodule are connected with the first TTL buses,
The reception pin of the primary module and the transmission pin of the multiple submodule are connected with the 2nd TTL buses；
Three state buffer is provided between the transmission pin of the primary module and the first TTL buses；
Three state buffer is respectively arranged between the transmission pin of each submodule and the 2nd TTL buses；
The primary module sends request signal, three state buffer and the first TTL buses through being connected with the primary module
The multiple submodule is reached, the three state buffer has signal enhancing effect；Be up to a submodule responds, hair
Feedback signal is sent, three state buffer and the 2nd TTL buses arrival primary module through being connected with the submodule, described three
State buffer has ternary output function.
Of the present utility model in a preference, resistance is provided between the 2nd TTL buses and power supply, the resistance is
5K Ω to 10K Ω.
Of the present utility model in a preference, the Enable Pin and input of the three state buffer being connected with primary module
The transmission pin of the primary module is connected, output end connects the first TTL buses；The three state buffer being connected with each submodule module
Enable Pin connects the transmission pin of each submodule with input, and output end connects the 2nd TTL buses.
Of the present utility model in a preference, the output of three state buffer is low level or high-impedance state.
When input and Enable Pin are low level, output end is identical with incoming level, and low level is presented；When input and
When Enable Pin is high level, high-impedance state is presented in output end.
The utility model embodiment compared with prior art, at least with following difference and effect：
The utility model uses TTL serial bus communications, and request signal and feedback signal are separately in two circuits
Middle transmission, it will not interfere, transmission speed is fast.Three state buffer is set between primary module and the first TTL buses, has and increases
Strong signal function, request signal is set to send simultaneously to all submodules.Divide between all submodules and the 2nd TTL buses
Three state buffer is not set, there is ternary output function, the feedback signal that the submodule for enabling to respond is sent arrives completely
Up to primary module, and do not disturbed by other submodules.
Further, power supply and resistance are connected with the 2nd TTL buses, when no signal transmits, bus is in all the time
High level state.Only when the submodule fed back exports low level, bus level is pulled low, and signal is synchronized to primary module
Reception pin.Message transmission rate depends entirely on the response of triple gate in circuit, and the propagation delay time is short, circuit work speed
Rate is high, while triple gate is active device, can increase the driving of circuit.
It is appreciated that in the scope of the utility model, above-mentioned each technical characteristic of the present utility model and below (strictly according to the facts
Apply mode and example) in specifically describe each technical characteristic between can be combined with each other, so as to form new or preferable skill
Art scheme.As space is limited, no longer tire out one by one herein and state.
Brief description of the drawings
Fig. 1 is the structural representation of TTL communication buses submodule extension system；
Fig. 2 is the electrical schematic diagram of three state buffer；
Fig. 3 is 2 submodule expanded circuit figures of TTL communication buses.
Embodiment
In the following description, in order that reader more fully understands the application and proposes many ins and outs.But this
Even if the those of ordinary skill in field is appreciated that without these ins and outs and many variations based on following embodiment
And modification, the application technical scheme claimed can also be realized.
In the application documents of the application, part concept explanation and citing：
TTL refers to mainly by BJT (Bipolar Junction Transistor i.e. bipolar junction transistor), the pole of crystal three
Pipe and resistance are formed, and have fireballing feature.
First TTL buses, refer to the circuit that connection primary module sends pin and multiple submodule reception pin.
2nd TTL buses, refer to the circuit that connection primary module receives pin and multiple submodule transmission pin.
Three state buffer, also known as triple gate, three-state driver, its ternary output are controlled by enabled output end, when
When enabled output is effective, device realizes normal logic state output (logical zero, logic 1), when enabled input is invalid, at output
In high-impedance state, that is, it is equivalent to and is disconnected with connected circuit.
TX pins, that is, send pin.
RX pins, that is, receive pin.
The part innovative point of the application is illustrated below：
In order to solve the problems, such as that submodule quantity is restricted in bus in hardware circuit communication, discloses a kind of use
The method that TTL bus communications extend to submodule.TTL serial bus communications are used between primary module and submodule so that main mould
The feedback signal independent parallel transmission that the request signal and submodule that block is sent are sent, will not produce and interfere with each other.
In addition, the transmitting terminal in each module is provided with three state buffer as buffer circuit.Three state buffer is active device
Part, there is three-state enable function, the driving force of primary module can be increased, and realize the output feedback function of submodule.With master
The Enable Pin of the three state buffer of module connection connects the transmission pin of the primary module with input, and output end connects the first TTL
Bus.The Enable Pin and input for the three state buffer being connected with submodule connect the transmission pin of the submodule, and output end connects
The 2nd TTL buses are connect, the submodule output high level or low level responded can be through three state buffer synchronism output.
It is high-impedance state that other submodules not responded, which send pin, without interference with bus level.Therefore submodule can extend in bus
To sufficiently large quantity.
Further, in above-mentioned connected mode although three state buffer uses three state buffer, but reality is defeated
Go out is low level or high-impedance state two states.When input and Enable Pin are low level, output end is identical with incoming level,
Low level is presented；When input and Enable Pin are high level, high-impedance state is presented in output end.
When submodule does not work, input and Enable Pin are high level, and output is in high-impedance state.Now due to second
TTL buses connect through resistance and are connected with power supply, and high level is presented in the 2nd TTL buses, so the reception pin of primary module is height
Level.
When submodule works, during the submodule that responds output low level, the input of three state buffer and enabled
Hold and turned on for low level, three state buffer, it is low level that output end is synchronous, and now the 2nd TTL buses are pulled to low level, main
Module receives the low level signal of submodule transmission；
During the submodule output high level responded, the input and Enable Pin of three state buffer are high level, tri-state
Buffer exports high-impedance state, is now connected because the 2nd TTL buses connect through resistance with power supply, and the 2nd TTL buses present high
Level, so the reception pin of primary module is high level.
Therefore, the enabled output function of three state buffer can be by the output level Complete Synchronization of the submodule responded
To the receiving terminal of primary module, and realize and the circuit of other submodules is isolated, further realize to submodule quantity in bus
Extension.
It is new to this practicality below in conjunction with accompanying drawing to make the purpose of this utility model, technical scheme and advantage clearer
The embodiment of type is described in further detail.
Embodiment of the present utility model is related to a kind of TTL communications submodule expanding unit.Fig. 1 is that the structure of the system is shown
It is intended to, including：First TTL buses and the 2nd TTL buses；Resistance；
Primary module, including send pin TX and receive pin RX, for sending request signal and receiving feedback signal；
Multiple submodule, include sending pin TX respectively and receive pin RX, fed back for receiving request signal and sending
Signal；
Wherein, the TX pins of primary module and the RX pins of all submodules are connected with the first TTL buses, the RX pipes of primary module
The TX pins of pin and all submodules are connected with the 2nd TTL buses；Set between the TX pins of primary module and the first TTL buses
There is three state buffer, the Enable Pin of three state buffer connects the TX pins of primary module with input, and it is total that input connects the first TTL
Line；Be respectively arranged with three state buffer between the TX pins of each submodule and the 2nd TTL buses, the Enable Pin of three state buffer and
Input connects the TX pins of each submodule, and output end connects the 2nd TTL buses；One end of resistance is connected with the 2nd TTL buses,
The other end connects power supply.
The request signal that primary module TX pins are sent is sent to the RX of each submodule through three state buffer and the first TTL buses
Pin, the wherein three state buffer have humidification to signal, and all submodules at most only have a submodule when receiving the signal
Block can respond.
When all submodules all do not respond to, high level is presented in the output pin of each submodule, so three state buffer
Input and Enable Pin be high level, output is in high-impedance state.Now due to the 2nd TTL buses connect through resistance with
Power supply connects, and high level is presented in the 2nd TTL buses, so the reception pin of primary module is high level.
When one of respond, other submodule TX pins not responded are high level, are delayed through tri-state
It is high-impedance state to rush device output.The TX pins of the submodule of the response can send a feedback signal：
During the submodule output low level responded, the input and Enable Pin of three state buffer are low level, tri-state
Buffer turns on, and it is low level that output end is synchronous, and now the 2nd TTL buses are pulled to low level, and primary module receives submodule
The low level signal of transmission；
During the submodule output high level responded, the input and Enable Pin of three state buffer are high level, tri-state
Buffer exports high-impedance state, is now connected because the 2nd TTL buses connect through resistance with power supply, and the 2nd TTL buses present high
Level, so the reception pin of primary module is high level.
Therefore, the enabled output function of three state buffer can be by the output level Complete Synchronization of the submodule responded
To the receiving terminal of primary module, and realize and the circuit of other submodules is isolated, further realize to submodule quantity in bus
Extension.
In one embodiment of the present utility model, the electrical schematic diagram of three state buffer is as shown in Fig. 2 truth table such as table
Shown in 1：
The menu of table 1
Wherein, when OE pin are high level, output Y shows high-impedance state；When OE pin are low level, output Y and input A
Level is identical.
In one embodiment of the present utility model, 2 submodule expanded circuits of TTL communication buses are as shown in Figure 3.
In Fig. 3, when submodule 1 and submodule 2 are sent without data, the TX pins of submodule 1 and submodule 2 be high level, process
Export after three state buffer and high-impedance state is presented, but now due to having connect 10K pull-up 5V resistance in RX buses, now bus
High level state is presented；
When submodule 1 has data to be sent to primary module:
First, when submodule 2 is sent without data, because the TX pins of submodule 2 are high level, by three state buffer
Afterwards, high-impedance state is presented in output, and therefore, the TX pins of submodule 2 will not produce interference to bus data.
Secondly, when the TX pins of submodule 1 are drawn high, although high-impedance state is presented in the output after three state buffer,
It is due to pull-up resistor, bus level is also height；When the TX pins of submodule 1 drag down, three state buffer enables, Three-State
The output end of device and the TX pin level of submodule 1 are consistent, and are also pulled low, now, bus level is pulled low.Bus level
It is completely the same with the TX pin level of submodule 1, therefore data can be accurately sent to primary module by submodule 1.
Because increased Three-State is when OE inputs are high level, high-impedance state is presented in output, therefore submodule does not have
When responding, any interference will not be caused to bus.It is thereby achieved that in bus submodule quantity extension.
It should be noted that in the application documents of this patent, such as first and second or the like relational terms are only
For an entity or operation are made a distinction with another entity or operation, and not necessarily require or imply these entities
Or any this actual relation or order be present between operation.Moreover, term " comprising ", "comprising" or its any other
Variant is intended to including for nonexcludability, so that process, method, article or equipment including a series of elements are not only
Including those key elements, but also the other element including being not expressly set out, or also include for this process, method, thing
Product or the intrinsic key element of equipment.In the absence of more restrictions, the key element limited by sentence " including one ", not
Other identical element in the process including the key element, method, article or equipment also be present in exclusion.The application of this patent
In file, if it is mentioned that certain behavior is performed according to certain key element, then refers to the meaning that the behavior is performed according at least to the key element, wherein
Include two kinds of situations：The behavior is performed according only to the key element and the behavior is performed according to the key element and other key elements.
All it is incorporated as referring in this application in all documents that the utility model refers to, just as each document quilt
It is individually recited as with reference to such.In addition, it is to be understood that after above-mentioned instruction content of the present utility model has been read, this area skill
Art personnel can make various changes or modifications to the utility model, and it is claimed that these equivalent form of values equally fall within the application
Scope.
Claims (6)
- A kind of 1. TTL communication buses submodule expanded circuit, it is characterised in that including：First TTL buses and the 2nd TTL buses；Primary module, including send pin and receive pin, for sending request signal and receiving feedback signal；Multiple submodule, include sending pin respectively and receive pin, for receiving request signal and sending feedback signal；The transmission pin of the primary module and the reception pin of the multiple submodule are connected with the first TTL buses, described The reception pin of primary module and the transmission pin of the multiple submodule are connected with the 2nd TTL buses；Three state buffer is provided between the transmission pin of the primary module and the first TTL buses；Three state buffer is respectively arranged between the transmission pin of each submodule and the 2nd TTL buses；The primary module sends request signal, and three state buffer and the first TTL buses through being connected with the primary module reach The multiple submodule, the three state buffer have signal enhancing effect；Be up to a submodule responds, and sends anti- Feedback signal, three state buffer and the 2nd TTL buses through being connected with the submodule reach the primary module, and the tri-state is delayed Rushing utensil has ternary output function.
- 2. TTL communication buses submodule expanded circuit according to claim 1, it is characterised in that the 2nd TTL buses Resistance is provided between power supply.
- 3. TTL communication buses submodule expanded circuit according to claim 2, it is characterised in that the resistance is 5K Ω To 10K Ω.
- 4. TTL communication buses submodule expanded circuit according to claim 1, it is characterised in that connect with the primary module The Enable Pin of the three state buffer connect connects the transmission pin of the primary module with input, and output end connects the first TTL Bus.
- 5. TTL communication buses submodule expanded circuit according to claim 1, it is characterised in that with each submodule module The Enable Pin of the three state buffer of connection connects the transmission pin of each submodule, output end connection described second with input TTL buses.
- 6. TTL communication buses submodule expanded circuit according to claim 1, it is characterised in that the three state buffer Output be low level or high-impedance state.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201720726926.8U CN207051890U (en) | 2017-06-21 | 2017-06-21 | TTL communication bus submodule expanded circuits |
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| CN201720726926.8U CN207051890U (en) | 2017-06-21 | 2017-06-21 | TTL communication bus submodule expanded circuits |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107229589A (en) * | 2017-06-21 | 2017-10-03 | 上海景格信息科技有限公司 | TTL communication bus submodule expanded circuits |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107229589A (en) * | 2017-06-21 | 2017-10-03 | 上海景格信息科技有限公司 | TTL communication bus submodule expanded circuits |
| CN107229589B (en) * | 2017-06-21 | 2024-03-12 | 上海景格信息科技有限公司 | TTL communication bus sub-module expansion circuit |
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