JPS62174667A - Flip-flop circuit - Google Patents

Abstract

PURPOSE:To easily diagnose all circuits in a cell by providing gates to output terminals of a master latch circuit and a slave latch circuit and connecting those output terminals to the same scan-out data pin. CONSTITUTION:This circuit consists of a master-slave side latch circuit LAT1, slave-side LAT2, and gate circuits 1-3 which control the outputs of the circuits LAT1 and LAT2 according to the value of a test control pin 20. The outputs of the circuits LAT1 and LAT2 are outputted to the scan-out data pin 21 through the gates 1 and 3. Consequently, data outputted from the circuit LAT1 is outputted through the gate 1 and data outputted from the circuit LAT2 is outputted to the same pin 21 through the gate 3. Therefore, the LAT2 and gate 3, and LAT1 and gate 1 are diagnosed by confirming which of '0' or '1' scanned in from the pin 21 is outputted. Thus, all circuits in the cell are easily diagnosed.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to signal control/techniques, and also to techniques that are particularly effective when applied to control data output of flip-flop circuits. The present invention relates to a technique that is effective for use in flip-flop circuits forming a diagnostic circuit provided inside an LSI for diagnosing an integrated circuit (integrated circuit).

[Prior Art] There is a method of diagnosing a large-scale integrated circuit by dividing it into small-scale combinational circuits using internal flip-flop circuits. That is, a master-slave type flip-flop circuit is used as the flip-flop circuit.

[Problems to be Solved by the Invention] In this case, if the master-slave type flip-flop is configured to pass through both the master latch circuit and the slave latch circuit even during normal operation, the data propagation speed will be slow. Become.

Therefore, the inventor studied a circuit as shown in FIG. The circuit in the figure includes a mask-side latch circuit LAT1, a slave-side latch circuit LAT2, and a gate 1 constituting a control circuit.
It consists of ~3.

In the same figure, for example, the test control pin is “0”.
" is the time of diagnosis, and "1" is the time of normal operation.

Here, when the test control pin is 0'', that is, during diagnosis, the data input from the data input pin to the master latch circuit LATI and latched is once supplied to the slave latch circuit LAT2 without passing through gate 1 and latched. is output from the output terminal Q to the data output pin and the scan-out data pin.If a scan-out data pin is provided for each latch circuit,
As mentioned above, there is a circuit (gate 1 in FIG. 3) through which a signal does not pass, although it is used during normal operation, during diagnosis. That is, during diagnosis, the output of the master latch circuit LATI is output from the first scan out bin, the output of the slave latch circuit LAT2 is output from the second scan out data pin, and the output of the slave latch circuit LAT2 is output from the second scan out data pin.
does not pass through. Therefore, there was an inconvenience that gate 1 could not be diagnosed. Furthermore, when there are two scan-out data pins, when automatic wiring is performed by treating a flip-flop as described above as one cell, there is a problem that the number of cell terminals is large and layout is difficult.

An object of the present invention is to enable easy diagnosis of all circuits in a cell, including a master-slave type flip-flop circuit and peripheral control circuits.

Another object of the present invention is to facilitate the layout of a logic LSI having a master-slave type flip-flop circuit.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

In other words, a master-slave type flip-flop,
to the output terminals of the master latch circuit and slave latch circuit that make up the flip-flop.

Each gate is provided with a gate to control its output. and,
By connecting the output terminal of the gate to the same scan-out data pin, data is output from the master latch circuit and the slave latch circuit in response to a control signal supplied from the outside. are also output via the same scanout data pin.

[Operation] According to the above means, it is possible to easily diagnose all the circuits in the cell, and to achieve the above object of reducing the number of terminals of the cell to facilitate layout.

[Embodiment] FIG. 1 shows a schematic configuration of a logic LSI such as a gate array to which the present invention is applied. In the figure, although not particularly limited, each circuit surrounded by a two-dot chain line A is formed on one semiconductor chip such as a single crystal silicon substrate.

It is more efficient to diagnose a logic LSI by dividing it into small-scale combinational circuits. Therefore, in this embodiment, each block of the combinational circuit 11 surrounded by the flip-flop FFI and the flip-flop FF2, and the combinational circuit 12 surrounded by the flip-flop FF3 and the flip-flop FF4, as shown by the two-dot chain lines B and C. A diagnosis is made. The combinational circuits 13 and 14 are similarly diagnosed. Each of the flip-flops FF1 to FF4 is a master-slave type flip-flop consisting of a master latch circuit and a slave latch circuit.

Individual combinational circuits 11, 12 . The diagnosis of ... is carried out as follows. First, a test pattern is scanned into the flip-flops FFI and FF3 on the input side of the combinational circuit. Next, the output side flip-flop FF2. FF
4 clock CLK is sent and data is taken in. Then, the output side flip-flop FF2. The data taken in from FF4 is outputted from the scan alitopin and compared with the data obtained in advance.

Such processing is performed for all test patterns for all combinational circuits divided into small scales. This makes it possible to diagnose the logic LSI.

In addition, in the above embodiment, in order to be able to diagnose each combinational circuit, an address is allocated to each combinational circuit in advance, and the address is decoded by the scan operation circuit 2o to specify a desired combinational circuit. It is now possible to diagnose.

FIG. 2 shows master-slave type flip-flop circuits FFI, FF2 . . . . is a circuit diagram showing the configuration of.

The flip-flop circuit FF in the same figure is a master latch circuit LATI, a slave side LAT2, and a master latch circuit LAT according to the value of the test control pin.
It is composed of gate circuits 1 to 3 for controlling the output of the slave latch circuit LAT2 and the output of the slave latch circuit LAT2.

Only one scan-out data pin is provided, and the output of the master latch circuit LAT1 can be output to the scan-out data pin via the gate 1, and the output of the slave latch circuit LAT2 can be output to the scan-out data pin via the gate circuit 3. .

In the above flip-flop circuit FF, the test control pin is fixed at "1" during normal operation of the LSI. Then, gate 1 is opened and data input from the data input pin to the latch circuit LATI passes through the gate. Sent to the data output pin and the subsequent combinational circuit (see Figure 1)
supplied to

In other words, since the data does not pass through the latch circuit LAT2,
The data transmission delay time is correspondingly shortened.

In addition, the flip-flop circuit FF fixes the test control pin to "0", and in this state clock CL
At KI, test data is taken into the master latch circuit LATI and transferred to the slave latch circuit LAT2 in synchronization with the clock pulse CLK2. As a result, the test patterns “0” and “1” are applied to the slave latch circuit LAT.
Scanned in to 2. Slave latch circuit LAT2
The output of is outputted to the scanout data pin through gate 3, which is opened by the signal on the test control pin. Therefore, the slave latch circuit LAT2 and gate 3 are diagnosed by checking whether or not the scanned-in "0" and '1' are output from the scan-out pin.

Next, the test control pin is fixed at u I II, and in this state, test buttons "0" and "1" are scanned into the input terminal of the master latch circuit LATI in synchronization with the clock pulse CL K t.

Then, since the gate 1 is opened by the signal from the test control pin, the output of the master latch circuit LAT2 passes through the gate 3 and is output to the scan out pin. Therefore, the master latch LA
Diagnosis of T1 and gate 1 becomes possible. Clock pulses CLK and CLK are substantially opposite phase signals, which cause master latch LAT1 and slave latch LAT
Lacing in 2 is prevented.

In this embodiment, the output terminals of gates 1 and 3, which are provided to control the outputs of master latch circuit LATI and slave latch circuit LAT2, are connected to the same scan-out data pin, so that all the circuits in the cell can be easily diagnosed. Also.

Since the number of scan-out data pins in the cell is reduced to one, the number of terminals in the cell is reduced accordingly, making layout easier.

[Effects of the Invention] (1) The output terminals of the master latch circuit and the slave latch circuit constituting a master-slave type flip-flop circuit are provided with first and second gates for controlling their outputs, respectively. Since the outputs of these gates are connected to the same scan-out data pin, the data output from the master latch circuit is output through the first gate, and the data output from the slave latch circuit is output through the first gate. is output to the same scan-out data pin through the second gate, which has the effect that all the circuits in the cell can be easily diagnosed.

(2) The output terminals of the master latch and slave latch constituting the master-slave type flip-flop circuit are each provided with a gate for controlling their output. Since the output terminal of that gate is connected to the same scanout data pin, the number of terminals in the cell is reduced.
The effect is that the layout of the logic LSI becomes easier.

Although the invention made in accordance with the present invention has been specifically explained based on examples, it goes without saying that the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Nor.

In the above explanation, the invention made by the inventor of the present invention was mainly applied to a flip-flop circuit that constitutes a diagnostic circuit provided inside an LSI, which is the field of application in which the invention was made, but the invention is not limited thereto. For example, circuits with master-slave flip-flops are commonly available.

[Brief explanation of drawings]

FIG. 1 is a block diagram schematically showing a logic LSI such as a gate array to which the present invention is applied. FIG. 2 is a circuit diagram showing the configuration of the master-slave flip-flop circuits FFI, FF2, etc. in FIG. 1, and FIG. 3 is a master-slave flip-flop circuit proposed by the applicant prior to the present invention. FIG. 1-3 Self-gate circuit, LATI...master latch circuit, LAT2...slave latch circuit, FFI
~FF4...Master-slave type flip-flop circuit, 11-14...Combination circuit, 20...Scan operation circuit. Agent Patent Attorney Katsuo Ogawa ＼、

Claims (1)

[Claims] 1. A flip-flop circuit with a master-slave configuration, in which the output terminals of the master latch circuit and the slave latch circuit are each provided with a gate for controlling the output, and the output terminals of the gates are connected to the same scan-out data pin, In response to a control signal supplied from the outside, data is output through the same scan-out data pin both when the master latch circuit and the slave latch circuit output data. A flip-flop circuit characterized by: