JP2002277515A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of efficiently and accurately detecting a fault in a delaying property. SOLUTION: A plurality of paths from data feeding flip-flops 11- 0, 11- 1, 11- 2, 11- 3, and 11- 4 to data receiving flip-flops 11- 5, 11- 6, 11- 7, 11- 8, and 11- 9 are equipped with buffers 13- 1, 13- 2, 13- 3, 13- 4, 13- 5, 13- 6, 13- 7, 13- 8, 13- 9, 13- 10, 13- 11, and 13- 12 in order that they all have the same delay time that may vary within a range allowing the detection of a fault in the delaying property.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor integrated circuit in which a test circuit having a plurality of flip-flops is incorporated.

[0002]

2. Description of the Related Art Conventionally, as a part of a test of a manufactured semiconductor integrated circuit, a transition time from a "H" level to an "L" level and a "L" level of a signal output from a cell constituting the semiconductor integrated circuit are considered. A delay failure detection test is performed to determine whether the transition time from the 'level' to the 'H' level is longer than a predetermined delay time. Although there are several methods for the delay defect detection test, a method called a scan path test method is generally employed. In the scan test method, a flip-flop, which is a sequential circuit provided in a semiconductor integrated circuit, is replaced with a scannable flip-flop to form a shift register, and parts other than the shift register are treated as a combinational circuit to control the shift register. Thus, a combination circuit (internal circuit) is tested. In this scan test method, the following ATPG (Automatic) is used to automatically generate a test pattern.
A Test Pattern Generator tool is used. (1) Transition Fault_ATPG tool A software tool that automatically generates a test pattern for the purpose of assuming a delay failure for all nodes in an internal circuit of a semiconductor integrated circuit and transitioning all the nodes. (2) PathDelayFault_ATPG tool Data transmission path specified from outside (abbreviated as path)
Software tool that automatically generates test patterns to activate the software. Usually, a designer specifies a critical path (a path where a maximum delay time is expected), and automatically generates a test pattern for activating only the critical path. Its main purpose is to verify chip performance due to process fluctuations.

The manner in which a semiconductor integrated circuit is tested for delay defects by the scan test method using such an ATPG tool will be described below with reference to FIG.

FIG. 2 is a diagram showing a configuration of a conventional semiconductor integrated circuit.

In the semiconductor integrated circuit 100 shown in FIG. 2, flip-flops 11_0, 11_1, 11_2, 11_3, 1 for data transmission constituting a scan path chain are provided.
1_4 and data receiving flip-flop 11_
5, 11_6, 11_7, 11_8, 11_9 and their flip-flops 11_0, 11_1, 11_2, 1
1_3, 11_4 and flip-flops 11_5, 11_
6, 11_7, 11_8, 11_9 and an internal circuit (a circuit to be tested)
_0,12_1,12_2,12_3 and buffer 1
3_0. Here, the AND gate 12
_0, 12_1, 12_2, and 12_3 each have a delay time of 5 ns, the buffer 13_0 has a delay time of 20 ns,
Flip-flops 11_0, 11_1, 1 for data transmission
The data of 11_2, 11_3, and 11_4 are flip-flops 11_5, 11_6, 11_7, 1 for data reception.
The operation cycle (cycle of the clock CK) until the data is taken in 1_8 and 11_9 will be described as 20 ns.

First, test data D0, D1, D2, D3, D4 based on an automatically generated test pattern
Are flip-flops 11_0, 11_
1, 11_2, 11_3, and 11_4 are input to the data terminals. Next, the flip-flops 11_0,1
The clock CK is input to clock terminals 1_1, 11_2, 11_3, and 11_4. Then, the flip-flops 11_0, 11_1, 11_2, 11_3, 11_4
Output data D0, D1, D2, D3, and D4. Output data D0, D1, D2, D3, D4
Receives the next clock CK (20) via the AND gates 12_0, 12_1, 12_3 and the buffer 13_0.
ns), the flip-flops 11_5, 11_6, 11_7,
11_8 and 11_9. Here, the delay time in the critical path from the flip-flop 11_4 to the flip-flop 11_5 (the AND gate 12
_0,12_1,12_2,12_3 total delay time)
Is less than or equal to 20 ns, and the flip-flop 11_4
The delay time (the delay time of the buffer 13_0) in the critical path from the memory to the flip-flop 11_9 is also 2
If it is 0 ns or less, the semiconductor integrated circuit 100 is determined to be non-defective.

[0007]

Here, for example, the AND gate 1 constituting the manufactured semiconductor integrated circuit 100 is described.
2_1 is 6 ns, that is, AND gate 1
When a delay time of 6 ns (a delay increase of 1 ns) occurs at the output side node Y with respect to the transition of the signal at the nodes A and B on the input side of 2_1, the delay on the critical path from the flip-flop 11_4 to the flip-flop 11_5 The time is 21 ns. In this case, although the semiconductor integrated circuit 100 is actually defective,
In the following cases, a problem of being determined as a non-defective product occurs. (1) When the Transition Fault_ATPG Tool is Used The test pattern generated by the Transition Fault_ATPG tool is for transitioning all nodes, and therefore does not necessarily activate the critical path. When a test pattern is generated for the path leading to the flip-flop 11_6, the delay time in that path is a 6 ns delay time due to the AND gate 12_1, so that the operation cycle of 20 ns is satisfied. Despite the presence, it will be determined as a good product. (2) When PathDelayFalt_ATPG Tool is Used In this tool, the designer uses STA (Static Ti
For each cell, all critical paths, which are the maximum delay paths passing through the cells, are extracted by using “Ming Analysis”, and PathD is determined based on all the extracted critical paths (excluding overlapping paths).
By automatically generating a test pattern with the elayFault_ATPG tool, it is possible to detect all delay defects. However, since the test pattern becomes enormous, in reality, a test pattern generated based on the critical path selectively extracted by the designer is used. If the critical path from the flip-flop 11_4 to the flip-flop 11_9 is specified without specifying the critical path from the flip-flop 11_4 to the flip-flop 11_5, the operation cycle of 20 ns is satisfied, and the product is also determined to be non-defective. Becomes

In recent years, as the degree of integration of semiconductor integrated circuits increases, the number of test steps for determining the quality of manufactured semiconductor integrated circuits also tends to increase. Therefore, the quality of semiconductor integrated circuits is efficiently tested. Technology is becoming more important.

SUMMARY OF THE INVENTION In view of the above circumstances, it is an object of the present invention to provide a semiconductor integrated circuit capable of detecting a delay defect efficiently and accurately.

[0010]

A semiconductor integrated circuit according to the present invention, which achieves the above object, sets a plurality of test data in a plurality of data sending flip-flops, sends the set data to an internal circuit, and sends the data through the internal circuit. A semiconductor integrated circuit which incorporates a test circuit for taking in the plurality of data obtained by the plurality of data receiving flip-flops and sending the data to the outside, and capable of determining whether or not the internal circuit is defective based on the data sent to the outside; All of the plurality of data transmission paths from the data sending flip-flop to the plurality of data receiving flip-flops have the same delay time due to an error within the detectable range of the delay failure by the test circuit. It is characterized by.

In a conventional semiconductor integrated circuit, when detecting a delay failure, a transition fault_AT
When the PG tool is used, the generated test pattern does not necessarily activate the critical path, and thus may be determined to be good even though it is actually defective. Also, PathDelayF
When the "ult_ATPG" tool is used, it is difficult to specify an appropriate test pattern from an enormous number of test patterns, and therefore, it may be determined as a non-defective product even though it is a defective product.

According to the semiconductor integrated circuit of the present invention, all of a plurality of data transmission paths from a plurality of data transmitting flip-flops to a plurality of data receiving flip-flops have the same delay due to an error within a detectable range of delay failure. Since the configuration has time, the critical paths in all of the plurality of data transmission paths can be easily activated using a relatively simple test pattern. Therefore, it is possible to efficiently and accurately detect the delay failure.

[0013]

Embodiments of the present invention will be described below.

FIG. 1 is a diagram showing a configuration of a semiconductor integrated circuit according to one embodiment of the present invention.

The semiconductor integrated circuit 1 shown in FIG.
The same components as those of 00 are denoted by the same reference numerals and described.

The semiconductor integrated circuit 10 shown in FIG. 1 is different from the semiconductor integrated circuit 100 shown in FIG. 2 in that a delay time of, for example, 5 ns is provided on a path from the data sending flip-flop 11_0 to the data receiving flip-flop 11_5. Buffers 13_1, 13_2, and 13_3 are inserted. In addition, the data transfer flip-flop 11_1
Buffer 13_4,1 having a delay time of 5 ns also on the path from
3_5 and 13_6 are inserted. Further, buffers 13_7, 13_8, and 13_9 having a delay time of 5 ns are inserted in the path from the data sending flip-flop 11_2 to the data receiving flip-flop 11_7. Further, the data transmission flip-flop 11
_3 to the data receiving flip-flop 11_8 also have a buffer 13_1 having a delay time of 5 ns.
0, 13_11 and 13_12 are inserted.

The semiconductor integrated circuit 10 of the present embodiment has flip-flops 11_0, 11_1, and 11_ for data transmission.
Data flip-flops 11_5, 11_6, 11_7, 11_8, 11_ from 2, 11_3, 11_4
,..., 13_12 so as to have the same delay time with an error within the detectable range of the delay failure (within 1 ns if the delay increment due to the delay failure is 1 ns) with respect to all of the plurality of paths to 9. Has been inserted. That is, the flip-flop 11_4 to the flip-flop 1
Buffers 13_1,..., 13_1 have a delay time approximately equal to the delay time (20 ns) in the critical path from 1_5 and the critical path from flip-flop 11_4 to flip-flop 11_9.
2 has been inserted. Therefore, for example, when the delay time of the AND gate 12_1 is 6 ns, the delay time in the path from the flip-flop 11_1 to the flip-flop 11_6 is 21 ns, and the transit is performed.
The delay failure can be detected using a relatively simple test pattern generated by the onFault_ATPG tool. Therefore, even a delay failure of about 1 ns can be detected using a relatively simple test pattern.

The buffers 13_1,..., 13_1
2 is inserted at the design stage in the semiconductor integrated circuit 100 shown in FIG. 2 in the data transfer flip-flops 11_0, 11_1, 1 constituting the scan path chain.
1_2, 11_3, 11_4 and data receiving flip-flops 11_5, 11_6, 11_7, 11_8, 11
_9, the delay time in the critical path is simulated and measured, and the buffers 13_1,..., 13_12 are inserted to correct the circuit so that all paths have the same delay time. Fit together.

As means for adjusting the delay time,
For example, there are the following two means.

The first means is a STA (Static T).
This is a means for employing the result of the “imaging analysis”, extracting a critical path by the STA, measuring only the delay time in the path after the branch for a part of the cell output that is branched, and delaying the path having a small delay time to the path having a small delay time. A buffer (cell) is added to adjust the delay time in the path after the branch to the delay time in the critical path.

The second means adds logic (cells) to all paths so as to match the number of logic stages (number of cells) of the critical path. If it is clear that the increase in delay is large, that is, if it is within the range in which the delay failure can be detected by the test circuit, there is no need to strictly adjust the delay time. The delay time may be adjusted by using.

[0022]

As described above, according to the semiconductor integrated circuit of the present invention, a commercially available TransitionFoul is used.
Even with the function of the t_ATPG tool, it is possible to detect a delay defect sufficiently and efficiently and accurately.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a conventional semiconductor integrated circuit.

[Explanation of symbols]

10, 100 Semiconductor integrated circuit 11_0, 11_1, 11_2, 11_3, 11_4
11_5, 11_6, 11_7, 11_8, 11_9
Flip-flop 12_0, 12_1, 12_2, 12_3 AND gate 13_0, 13_1, 13_2, 13_3, 13_4
13_5, 13_6, 13_7, 13_8, 13_9,
13_10, 13_11, 13_12 Buffer

Claims (1)

[Claims] 1. A plurality of test data is set in a plurality of data sending flip-flops and sent to an internal circuit, and a plurality of data passed through the internal circuit is taken in a plurality of data receiving flip-flops and externally set. In a semiconductor integrated circuit in which a test circuit for sending out to the plurality of data receiving flip-flops can be determined based on data sent out to the outside, the plurality of data sending flip-flops are connected to the plurality of data receiving flip-flops. A semiconductor integrated circuit, wherein a plurality of data transmission paths leading to the test circuit all have the same delay time with an error within a detectable range of the delay failure by the test circuit.