JP4559321B2 - Defect detection apparatus, defect detection method, and electronic device - Google Patents

Description

  The present invention relates to a defect detection apparatus, a defect detection method, and an electronic device. In particular, the present invention relates to a defect detection device for detecting a defect in a wiring for inputting a first output signal output from a preceding logic element to a succeeding logic element in an electronic device having a preceding logic element and a following logic element. The present invention also relates to a defect detection method, and an electronic device to which the defect detection apparatus and the defect detection method are applied.

  In recent years, multilayer metal wiring and copper wiring processes are frequently used for the purpose of speeding up and high integration of electronic devices such as LSI. Along with this, the rate of occurrence of open failures in wiring between logic elements has increased (see Non-Patent Documents 1 to 3). Open failures cause problems such as a reduction in noise margin of electronic devices, a reduction in signal reliability, and a reduction in operating frequency.

In a conventional logic test such as a stuck-at fault test, in order to detect an open fault, it is expected that an error logic value is generated at the fault location when the fault becomes obvious (from Non-Patent Document 4). 8). An n-time detection test in which n different test vectors are applied to detect and propagate one fault has been proposed as effective (Non-Patent Document 9).
J. Figueras, "Test Challenges in Nanometric World", Invited Talk, 2nd IEEE Latin American Test Workshop, 2001. R. Rodriguez-Montanes and two others, "Resistance Characterization for Weak Open Defects", IEEE Design & Test Computers, vol.19, no.5, pp.18-26, 2002. J. Segura and three others, "Parametric Failures in CMOS Ics-A Defect-Based Analysis", Proc. Int. Test Conf., Pp. 90-99, 2002. M. Renovell et al., "Optimal Conditions for Boolean and Current Detection of Floating Gate Faults", Proc. Int. Test Conf., Pp.477-486, 1999. VH Champac and 1 other, "Detectability Conditions for Interconnection Open Defect", Proc. VLSI test Symp., Pp.305-311, 2000. B. Kruseman, "Comparison of Defect Detection Capabilities of Current-based and Voltage-based Test Methods", Proc. European Test Workshop, pp.175-180, 2000. JC-M. Li and two others, "Testing for Resistive Opens and Stuck Opens", Proc. Int. Test Conf., Pp.1049-1058, 2001. Y. Sato et al., "An Evaluation of Defect-Oriented Test: Well-controlled Low Voltage Test", Proc. Int. Test Conf., Pp.358-366, 2001. C.-W. Tseng et al., "Multiple-Output Propagation Transition Fault Test", Proc. Int. Test Conf., Pp.358-366, 2001. S. Ghosh et al., "Estimating Detection Probability of Interconnect Opens using Stuck-at Tests", Proc. Great Lakes Symp. VLSI, pp.254-259, 2004. JM Rabaey, "Digital Integrated Circuits: A Design Perspective", Prentice-Hall, NJ, 1996. Z. Li and 4 others, "A Circuit Level Fault Model for Resistive Opens and Bridges", Proc. VLSI Test Symp., Pp.379-384, 2003.

  The internal state in the vicinity of the open failure location, that is, the logical value output by each nearby logic element depends on the test vector to be applied. For this reason, the probability that an open failure can be detected as a logical value error is low even by the conventional n-th detection test, and it is difficult to reliably detect an open failure (Non-Patent Document 10).

  Accordingly, an object of the present invention is to provide a defect detection apparatus, a defect detection method, and an electronic device that can solve the above-described problems. This object is achieved by a combination of features described in the independent claims. The dependent claims define further advantageous specific examples of the present invention.

  According to the first aspect of the present invention, in the electronic device having the preceding stage logic element and the succeeding stage logic element, the wiring for inputting the first output signal output from the preceding stage logic element to the following stage logic element A failure detection apparatus for detecting a failure in the electronic device, wherein an initialization unit that sets a power supply voltage supplied to the electronic device to an initial voltage value smaller than a threshold voltage of a logic element included in the electronic device; A booster that boosts the power supply voltage from the initial voltage value to the operating voltage of the logic element at a speed at which the logic value of the second output signal output from the element does not change; An inversion operation unit for inverting the logic value of the first output signal output from the preceding logic element in a state where the voltage is boosted to a voltage, and the second output signal after the first output signal is inverted Based on the delay time until the rolling, to provide a fault detection apparatus and a defect detecting section for detecting a connection failure between the front logic element and the downstream logic device.

  The initialization unit may set the power supply voltage to the initial voltage value of substantially 0V. The boosting unit may boost the power supply voltage with a ramp waveform having an inclination that does not change the logic value of the second output signal output from the subsequent logic element.

  When the signal input terminal of the electronic device is set to the H level so that the logic value of the first output signal is set to a predetermined expected value after the power supply voltage is boosted and before the first output signal is inverted. The unit may input substantially the same voltage as the power supply voltage to the signal input terminal of the electronic device after starting the boosting of the power supply voltage.

  When the signal input terminal of the electronic device is set to L level so that the logic value of the first output signal is set to a predetermined expected value after the power supply voltage is boosted and before the first output signal is inverted. The unit may input a voltage having substantially the same value as the initial voltage value to the signal input terminal of the electronic device after starting the boosting of the power supply voltage.

  Further comprising an acquisition unit that acquires the second output signal when a preset reference delay time elapses after inverting the first output signal, wherein the defect detection unit is configured to acquire the second output acquired by the acquisition unit. On the condition that the signal is not inverted, a connection failure between the preceding logic element and the succeeding logic element may be detected.

  On the condition that the logic value of the second output signal has changed while the boosting unit boosts the power supply voltage from the initial voltage value to the operating voltage, the initialization unit sets the power supply voltage to The initial voltage value may be set again, and the booster may boost the power supply voltage at a slower rate than the previous time.

  The electronic device includes a plurality of sets of front-stage logic elements and back-stage logic elements, and when the wiring unit between the front-stage logic elements and the back-stage logic elements is sequentially detected, the initialization unit includes: After testing for the presence or absence of a connection failure between the preceding stage logic element and one of the subsequent stage logic elements, before testing for the presence or absence of a connection failure between the other preceding stage logic element and the other following stage logic element, The voltage may be set to the initial voltage value.

  A test signal supply unit that supplies a test signal to the electronic device; and a determination unit that determines whether the logical operation of the electronic device is good or not based on a signal output from the electronic device according to the test signal. The initialization unit, after testing the electronic device logic operation test by the test signal supply unit and the determination unit, before testing whether there is a connection failure between the front-stage logic element and the rear-stage logic element, The power supply voltage may be set to the initial voltage value.

  The electronic device includes a plurality of flip-flops that are operated by a second power supply voltage different from the first power supply voltage supplied to the front-stage logic element and the rear-stage logic element, and the plurality of flip-flops connected in cascade. A scan path for setting the scan pattern string in the plurality of flip-flops by sequentially propagating a scan pattern string sequentially input from the scan input terminal of the electronic device from the first flip-flop to the succeeding flip-flop; The initialization unit sets the first power supply voltage to the initial voltage value in a state where the second power supply voltage is the operating voltage of the flip-flop. While the booster boosts the first power supply voltage from the initial voltage value to the operating voltage of the logic element The type of scan pattern sequence to the scan input terminal may further include a scan pattern supply unit for setting the plurality of flip-flops.

  The inversion operation unit may invert the first output signal by causing the at least one flip-flop to output a signal based on a scan pattern.

  The negative input of the first power supply voltage and the negative input of the second power supply voltage are electrically separated, and the first output signal is inverted after the power supply voltage is boosted and before the first output signal is inverted. When the input from one flip-flop to the logic circuit having the preceding logic element and the succeeding logic element is set to H level so that the logic value of the output signal becomes a predetermined expected value, the initialization unit With the connection between the flip-flop and the logic circuit disconnected, the negative input of the second power supply voltage is set to the ground potential, the positive input is set to the power supply potential, and the positive side of the first power supply voltage is set. An input and a negative side input are power supply potentials, and the boosting unit boosts the first power supply voltage by lowering the negative input potential of the first power supply voltage from the power supply potential to the ground potential. Do it It may be.

  According to the second aspect of the present invention, there is provided an electronic device having a function of detecting a defect in wiring between logic elements by a defect detection device, the first stage output from the preceding stage logic element and the preceding stage logic element. A logic circuit having a subsequent logic element for inputting a signal, and a plurality of flip-flops operated by a second power supply voltage different from the first power supply voltage supplied to the preceding logic element and the subsequent logic element; A plurality of flip-flops are connected in cascade, and a scan pattern sequence sequentially input from a scan input terminal of the electronic device is sequentially propagated from the leading flip-flop to the succeeding flip-flop, thereby scanning the plurality of flip-flops. A scan path for setting a pattern row and each of the plurality of flip-flops are set correspondingly. The signal output from the flip-flop or at least one of the positive potential and the negative potential of the first power supply voltage input to the electronic device is input to the logic element in the logic circuit. Provided is an electronic device including a plurality of selection units that respectively select whether to supply signals.

  In the scan-in period in which a scan pattern string is input from the scan input terminal to the plurality of flip-flops, the selection unit sets at least one of a positive potential and a negative potential of the first power supply voltage. You may supply as an input signal of the logic element in the said logic circuit.

  The selection unit is provided between the corresponding flip-flop and the logic circuit, and in a test mode in which a scan pattern string is input to the scan input terminal, the logic circuit side has a high impedance regardless of the output of the flip-flop. A first gate for supplying the output of the flip-flop to the logic circuit in a normal mode other than the test mode, a wiring between the first gate and the logic circuit, and a positive potential of the first power supply voltage. Or a second gate that is provided between at least one of the negative potentials, supplies the potential to the wiring in the test mode, and sets the wiring to high impedance in the normal mode. .

  The first flip-flop and the first substrate of the FET on the scan path and the second substrate of the FET in the logic circuit are electrically separated, and the first gate and the second gate The FET substrate may be electrically connected to the first substrate.

  According to a third aspect of the present invention, in an electronic device having a preceding-stage logic element and a preceding-stage logic element, a wiring for inputting a first output signal output from the preceding-stage logic element to the following-stage logic element A failure detection method for detecting a failure of the electronic device, wherein an initialization step of setting a power supply voltage supplied to the electronic device to an initial voltage value smaller than a threshold voltage of a logic element included in the electronic device; A boosting step of boosting the power supply voltage from the initial voltage value to the operating voltage of the logic element at a speed at which the logic value of the second output signal output by the element does not change; An inversion operation step of inverting the logic value of the first output signal output from the preceding logic element in a state where the voltage is boosted to a voltage, and the second output after inverting the first output signal No. is based on the delay time until the inverted, it provides a defect detecting method and a defect detection step of detecting a connection failure between the front logic element and the downstream logic device.

  The above summary of the invention does not enumerate all the necessary features of the present invention, and sub-combinations of these feature groups can also be the invention.

  Hereinafter, the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the invention according to the scope of claims, and all combinations of features described in the embodiments are included. It is not necessarily essential for the solution of the invention.

  FIG. 1 shows an example of a logic circuit 10 included in an electronic device to be tested (DUT: Device Under Test) according to the present embodiment. The logic circuit 10 illustrated in FIG. 1A includes logic elements 100, 110, 120, and 130. In this example, paying attention to a connection failure between the logic element 110 and the logic element 120, an output signal (hereinafter referred to as a “first output signal”) output from the preceding logic element 110 is input to the succeeding logic element 120. A case where a defect of the wiring 150 is detected will be described. Here, the preceding logic element 110 may be expressed as a driving logic element, and the succeeding logic element 120 may be expressed as a driven logic element.

  In this embodiment, for the sake of convenience of explanation, the connection failure of the wiring 150 between NOT logic elements is shown. However, the preceding logic element 110 and the succeeding logic element 120 are AND, NAND, OR, NOR, XOR, a buffer, and the like. The various logic elements may be used.

  The wiring 150 between the logic element 110 and the logic element 120 includes an f1 open failure (gate signal line open failure) in which both gate terminals of the nMOS FET 124 and the pMOS FET 122 in the logic element 120 are in an open state, nMOS F2 open failure (transistor signal line open failure) with only the gate terminal of the FET 124 open, and f3 open failure (transistor signal line open failure) with only the gate terminal of the pMOS FET 122 open. Yes.

  An open failure of the signal line that may occur in f1, f2, or f3 in FIG. 1A can be modeled as a failure model 15 of the RC circuit shown in FIG. 1B (from Non-Patent Document 11). 12). The fault resistance 160 represents a resistance due to an open fault. When the resistance value Rf of the fault resistor 160 is very large or infinite, the signal line open fault between the contacts N1 and N2 is called a floating gate fault. On the other hand, when the resistance value Rf is relatively small compared to the floating gate failure, it is called a resistive open failure.

ここで、Ｃｗ（ｌｉｎｅ）は信号線ｓとＶＤＤ電位またはＶＳＳ電位の信号線間の配線容量を示す。 The wiring capacitance 170 and the wiring capacitance 180 indicate the capacitance between the signal line having the open failure and the signal line having the potential of the positive side power supply voltage VDD and the negative side (ground side) power supply voltage VSS. The values of the wiring capacitance 170 and the wiring capacitance 180 are attributed to the design process and the circuit layout.
When the test vector ν is applied to the circuit, the capacitances Cw1 and Cw2 for the signal line s are given by the following equations.

Here, Cw (line) indicates a wiring capacitance between the signal line s and a signal line of VDD potential or VSS potential.

  In order to detect the above open failure by a logical test, a predetermined logical value must be set at the failure location by a test vector. However, the potential of the signal line in the vicinity of the failure location depends on the test vector to be applied, and the potential at the failure location depends on the balance of the capacitances of Cw1 and Cw2. Here, it is impossible to know in advance which wiring capacity is present between which signal line and what values are the capacitance values of the wiring capacity 170 and the wiring capacity 180. Therefore, a predetermined logical value cannot be reliably set at a failure location by a conventional logic test, and it is very difficult to reliably detect an open failure.

  FIG. 2 shows the configuration of the defect detection apparatus 30 according to this embodiment together with the DUT 20. The defect detection device 30 according to the present embodiment can efficiently test whether there is an open failure by operating the pre-stage logic element 110 after reliably setting the potential of the wiring 150 where the open failure exists.

  The defect detection device 30 includes a control device 200, a test signal supply unit 210, a scan pattern supply unit 220, a determination unit 230, a power supply control unit 240, an inversion operation unit 250, an acquisition unit 260, and a defect detection unit. 270. The control device 200 controls each part of the defect detection device 30. The test signal supply unit 210 is used for testing the logical operation of the DUT 20 and supplies a test signal to the DUT 20. The test signal supply unit 210 includes, for example, a sequential pattern generator (SQPG) that executes an instruction sequence included in a test sequence designated by the user and outputs a test pattern associated with each instruction. A test signal based on the test pattern output by may be supplied to the DUT 20. Instead, the test signal supply unit 210 includes an algorithmic pattern generator (ALPG) that updates a test pattern based on a preset arithmetic algorithm, and sends a test signal based on the test pattern output by the ALPG to the DUT 20. You may supply.

  The scan pattern supply unit 220 supplies a scan pattern sequence to the scan input terminal of the DUT 20. The determination unit 230 determines whether the logical operation of the DUT 20 is good based on the test signal supplied by the test signal supply unit 210 and / or the signal output by the DUT 20 according to the scan pattern sequence supplied by the scan pattern supply unit 220. judge. More specifically, the determination unit 230 compares the signal output from the DUT 20 with an expected value, and detects a failure when there is a mismatch.

  The power supply control unit 240 includes an initialization unit 242 and a boosting unit 244, and controls the power supply voltage of the DUT 20. The initialization unit 242 sets the power supply voltage supplied to the DUT 20 to an initial voltage value smaller than the threshold voltage of the logic element included in the DUT 20 in the connection failure test for detecting a failure of the wiring 150. As an example, the initialization unit 242 may set the power supply voltage to an initial voltage value of substantially 0V. Accordingly, the initialization unit 242 can set the voltage of the wiring 150 to be tested to a value between the initial voltage value and VSS.

  The boosting unit 244 changes the power supply voltage from the initial voltage value to the operating voltage of the logic element at a speed at which the logic value of the output signal (hereinafter referred to as “second output signal”) output from the subsequent-stage logic element 120 does not change. Increase the pressure. Thereby, the boosting unit 244 can set the power supply voltage of the DUT 20 as the operating voltage at the time of the test while maintaining the logical value of the wiring 150 at a predetermined expected value.

  The inversion operation unit 250 inverts the logic value of the first output signal output from the preceding logic element 110 in a state where the power supply voltage of the DUT 20 is boosted to the operation voltage. The acquisition unit 260 acquires the second output signal output from the subsequent logic element 120. The defect detection unit 270 receives the value of the second output signal from the acquisition unit 260 and based on the delay time from when the first output signal is inverted to when the second output signal is inverted, the pre-stage logic element 110 and the post-stage logic A connection failure between the elements 120 is detected.

  FIG. 3 shows an operation flow of the defect detection apparatus 30 according to the present embodiment. FIG. 4 shows a test performed by the failure detection device 30 when a connection failure of the wiring 150 is detected based on a change in the second output signal when the first output signal output from the logic element 110 is changed from the L level to the H level. Shows the timing. FIG. 5 shows a test performed by the failure detection device 30 when a connection failure of the wiring 150 is detected based on a change in the second output signal when the first output signal output from the logic element 110 is changed from the H level to the L level. The deformation | transformation part of this timing is shown. The operation flow of FIG. 3 will be described below in association with the timings of FIGS.

  The defect detection apparatus 30 performs the processing from S310 to S360 for each wiring to be tested (S300, S370). In the test of each wiring, the initialization unit 242 sets the power supply voltage supplied to the DUT 20 to an initial voltage value for a predetermined period (S310, times t0 to t1 in FIGS. 4 and 5). In the present embodiment, the case where the initial voltage value is 0V will be described as an example.

Next, the boosting unit 244 boosts the power supply voltage from the initial voltage value to the operating voltage of the logic element 110 and the logic element 120 (S320, times t1 to t2 in FIGS. 4 and 5). Here, the value of the power supply voltage is determined by the difference obtained by subtracting the negative power supply potential from the positive power supply potential. Boosting the power supply voltage means increasing the difference obtained by subtracting the negative power supply potential from the positive power supply potential. The positive power supply potential is relatively increased with respect to the negative power supply potential. It means that Therefore, the booster 244 may increase the positive power supply potential while keeping the negative power supply potential at the reference potential (eg, 0 V), and keep the positive power supply potential at the reference potential (eg, VDD or 0 V). However, the negative power supply potential may be lowered. Further, the booster 244 may change both the positive power supply potential and the negative power supply potential to increase the difference between the positive power supply potential and the negative power supply potential.
In the present embodiment, the booster 244 boosts the power supply voltage with a ramp waveform having a slope set so that the logic value of the second output signal output from the subsequent logic element 120 does not change.

  Here, the booster 244 does not change the logic value of the second output signal, so that the logic value of the wiring 150 input to the logic element 120 is set to a predetermined expected value (L level in FIG. 4, Is maintained at H level. In order to realize this, the booster 244 causes the logic element 110 to output the first output signal of the expected value during the initialization period (time t0 to t3 in FIGS. 4 and 5). For example, when the logical value of the first output signal output from the logic element 110 changes according to the input to the signal input terminal of the DUT 20, the booster 244 increases the power supply voltage before the inversion of the first output signal. The following processing is performed to set the logical value of one output signal to a predetermined expected value.

When the signal input terminal of the DUT 20 is set to the H level so that the logic value of the first output signal becomes the expected value, the booster 244 starts the boosting of the power supply voltage, and then the power And input the same voltage. As an example, as illustrated in FIG. 5, the initialization unit 242 sets the positive input, the negative input, and each signal input terminal of the power supply voltage of the DUT 20 to the ground potential 0V. Then, the boosting unit 244 sets the negative input of the power supply voltage to the negative potential −VDD while keeping the positive input of the power supply input of the DUT 20 and each signal input terminal at the ground potential 0V. As a result, the power supply control unit 240 can boost the power supply voltage of the DUT 20 and each signal input terminal to a voltage higher than the negative input of the power supply voltage by the voltage VDD. According to this method, by changing the potential of the negative input of the power supply voltage of the DUT 20, the voltage of the positive input and each signal input terminal is boosted while maintaining the potential of the positive input and each signal input terminal. Can do.
Instead of this, the boosting unit 244 may boost the voltage supplied to the positive side input of the power supply voltage and the potential of each signal input terminal.

  On the other hand, when the signal input terminal of the DUT 20 is set to L level so that the logic value of the first output signal is the expected value, the booster 244 starts boosting the power supply voltage, and then the signal input terminal of the DUT 20 And input a voltage substantially the same as the initial voltage value. As an example, as illustrated in FIG. 4, the initialization unit 242 sets the positive input, the negative input, and each signal input terminal of the power supply voltage of the DUT 20 to the ground potential 0V. Then, the boosting unit 244 sets the positive input of the power supply voltage to the positive potential VDD while keeping the negative input of the power supply input of the DUT 20 and each signal input terminal at the ground potential 0V. Thereby, the power supply control unit 240 can boost the power supply voltage of the DUT 20 to a voltage higher than the negative input of the power supply voltage and each signal input terminal by the voltage VDD. According to this method, by changing the positive-side input potential of the power supply voltage of the DUT 20, the positive-side input voltage can be boosted while maintaining the negative-side input and the potentials of the signal input terminals.

In the signal line open failure shown in the failure model 15, when the power supply voltage is boosted while the first output signal is kept at 0 V (FIG. 4), VDD connected to Cw1 is set to the positive side and the contact N1 is set to the negative side. It can be modeled by an equivalent circuit in which a voltage source Vi (t) is provided and VSS connected to Cw2 and the contact N1 are connected to the ground potential. In this case, if Vi (t) is the ramp voltage kt (k is the slope of the voltage) and Vi (0) = 0, the voltage VN2 at the contact N2 is expressed by the following equation.

When Vi (t) is a step voltage having an initial voltage value V0, the voltage VN2 at the contact N2 is expressed by the following equation.

In order to keep the logical value of the contact N2 input to the logic element 120 at the L level, the booster 244 supplies the power supply voltage at a speed at which the maximum value of VN2 is less than the threshold voltage _VthH on the positive side of the logic element 120. It is desirable to boost the voltage. When VN2 becomes equal to or higher than the voltage V _thH , the positive-side FET 122 in the logic element 120 is turned on and VDD is connected to the output of the logic element 120. As a result, the logic value of the second output signal changes. is there.

Preferably, the booster 244 may boost the power supply voltage at a speed such that the maximum value Vfmax of VN2 does not exceed 1/2 of the operating voltage. Further, the booster 244 sets the maximum voltage value Vfmax of VN2 to the negative threshold voltage in order to set the logical value of the first output signal to the expected value L level immediately before the inversion of the first output signal (time t3). Even when V _thL is exceeded, the power supply voltage may be boosted so that the voltage value Vfmin of VN2 immediately before the inversion of the first output signal is less than the threshold voltage V _thL .
Here, if the Rf, Cw1, and Cw2 of the signal line open failure to be tested and the maximum value Vfmax of VN2 are determined, the slope k of the lamp voltage can be obtained from Equation (3).

Similarly, in the signal line open failure shown in the failure model 15, when the power supply voltage is boosted by lowering the negative power supply potential while maintaining the first output signal and the positive power supply potential at the ground potential ( FIG. 5), an equivalent circuit provided with a voltage source Vi (t) in which VDD connected to Cw1 and the contact N1 are connected to the ground potential, VSS connected to Cw2 is the negative side, and the ground potential is the positive side. Can be In this case, in order to keep the logic value of the contact N2 input to the logic element 120 at the H level, the boosting unit 244 has a speed at which the minimum value of VN2 becomes larger than the negative threshold voltage V _{thL of the} logic element 120. It is desirable to boost the power supply voltage. When VN2 is equal to or lower than the voltage V _thL , the negative-side FET 124 in the logic element 120 is turned on and VSS is connected to the output of the logic element 120, resulting in a change in the logic value of the second output signal. is there.

Preferably, the booster 244 may boost the power supply voltage at such a speed that the maximum value of VN2 does not become less than ½ of the operating voltage. Further, the booster 244 sets the minimum voltage value of VN2 to the positive threshold voltage V V in order to set the logical value of the first output signal to the expected value H level immediately before the inversion of the first output signal (time t3). _Even if it is less than _thH , the power supply voltage may be boosted so that the voltage value of VN2 immediately before the inversion of the first output signal exceeds the threshold voltage _VthH .

  The acquisition unit 260 detects whether the logical value of the second output signal has changed while the booster 244 boosts the power supply voltage from the initial voltage value to the operating voltage (S330). For example, the acquisition unit 260 may detect a change in the logical value of the second output signal by directly observing the second output signal via the signal output terminal of the DUT 20. In addition, the acquisition unit 260 may detect a change in the logical value of the second output signal by indirectly observing the second output signal via other logic such as the logic element 130. Further, the acquisition unit 260 acquires the second output signal directly or indirectly at a predetermined timing after the power supply voltage is boosted and before the inversion of the first output signal, and whether or not the logical value of the second output signal has changed. May be detected. The acquisition unit 260 may acquire the second output signal via the signal output terminal of the DUT 20, or may acquire the second output signal by a scan flip-flop provided in the DUT 20 and output the second output signal by scan-out. Good.

  On condition that the logical value of the second output signal has changed while the booster 244 boosts the power supply voltage from the initial voltage value to the operating voltage (S330: Yes), the initialization unit 242 initializes the power supply voltage. The voltage value is set again (S310), and the booster 244 boosts the power supply voltage at a slower speed than the previous time (S320). Thereby, the power supply control unit 240 can adjust the boosting speed so as to boost the power supply voltage at a speed at which the logic value of the second output signal output from the subsequent logic element 120 does not change.

After the voltage stabilization period after boosting the power supply voltage at a speed at which the logic value of the second output signal does not change, the inversion operation unit 250 inverts the logic value of the first output signal output from the preceding-stage logic element 110 ( S330). During this voltage stabilization period, the voltage input to the subsequent logic element 120 is less than the threshold voltage V _thL (expected value L level) of the FET 124 or exceeds the threshold voltage V _thH of the _{FET 122} (expected value H level). ).

  For example, when the logic value of the pre-stage logic element 110 changes according to the input to the signal input terminal, the inversion operation unit 250 inverts the logic value of the signal input to the signal input terminal, thereby The logic value may be inverted. When the input of the logic element 110 is directly or indirectly connected to the scan flip-flop, the inversion operation unit 250 causes the scan pattern supply unit 220 to scan in the next scan pattern to the DUT 20. The scan pattern sequence may be shifted and the logic value of the signal input to the logic element 110 may be inverted.

Next, the acquiring unit 260 acquires the second output signal when a preset reference delay time has elapsed after inverting the first output signal (S350). Here, the acquisition unit 260 may acquire the second output signal in the same manner as in S330. The acquisition unit 260 uses the maximum value of the time from when the first output signal is inverted to when the second output signal is inverted in the wiring 150 that is not defective as the reference delay time. This reference delay time is set to a time shorter than the output cycle period of the second output signal.
4 and 5, the acquisition unit 260 outputs the inverted value of the second output signal by the logic element 130 at time t4 when the reference delay time has elapsed from time t3 when the first output signal is inverted. Get through the terminal.

  Next, the failure detection unit 270 detects a connection failure between the pre-stage logic element 110 and the post-stage logic element 120 on the condition that the second output signal acquired by the acquisition unit 260 at time t4 has not been inverted. (S360). That is, when the second output signal is not inverted at time t4, the elapsed time tpd from the inversion of the first output signal to the inversion of the second output signal is longer than the reference delay time. Therefore, the failure detection unit 270 detects a connection failure on the assumption that the signal line open failure shown in the failure model 15 exists on the wiring 150.

  The defect detection apparatus 30 repeats the above-described processing from S310 to S360 for each wiring to be tested (S370).

  As described above, according to the defect detection device 30 according to the present embodiment, after the logic value of the signal input to the subsequent logic element 120 is reliably set to a predetermined expected value, the former logic element 110 is operated. By doing so, it is possible to efficiently test whether there is a signal line open failure. Here, in the case of sequentially detecting a wiring defect between a set of a plurality of front-stage logic elements and subsequent-stage logic elements included in the DUT 20, the initialization unit 242 performs a process between one front-stage logic element and one subsequent-stage logic element. After testing for the presence or absence of a connection failure, the power supply voltage may be set to the initial voltage value before testing for the presence or absence of a connection failure between other preceding-stage logic elements and other subsequent-stage logic elements (S310). Thereby, the defect detection apparatus 30 can set the voltage of the wiring within the range of 0 V from the initial voltage value before the test of each wiring.

  Further, when testing a connection failure after completion of the logical operation test of the DUT 20 by the test signal supply unit 210 and the determination unit 230, the boosting unit 244 connects the pre-stage logic element and the post-stage logic element after the completion of the logic operation test. Before testing for the presence or absence of defects, the power supply voltage may be set to an initial voltage value (S310). Thereby, the defect detection device 30 can set the voltage of each wiring within the range of 0 V from the initial voltage value, regardless of the final internal state of the DUT 20 by the logic operation.

  FIG. 6 shows an example of the configuration of the DUT 20 according to the present embodiment. The DUT 20 according to the present embodiment has a function of causing the defect detection device 30 to detect a defect in wiring between logic elements. As a result, the DUT 20 can efficiently test a connection failure between logic elements, and improves testability. The DUT 20 includes a logic circuit 600, a plurality of FFs 610 (610a, b), a scan path 615, a plurality of multiplexers 620 (620a, b), and a plurality of gates 630 (examples of second gates according to the present invention). 630a, b).

  The logic circuit 600 includes a previous-stage logic element to be tested for connection failure, a subsequent-stage logic element that inputs a first output signal output from the previous-stage logic element, and a wiring between them. Here, the logic circuit 600 may be a combinational logic circuit as an example. The logic circuit 600 according to the present embodiment operates with the first power supply voltage.

  The plurality of FFs 610 (flip-flops) operate with a second power supply voltage different from the first power supply voltage supplied to the preceding-stage logic element and the subsequent-stage logic element. The scan path 615 is connected to a plurality of FFs 610 in cascade, and a scan pattern sequence sequentially input from the scan input terminal (Scan-in) of the DUT 20 is sequentially propagated from the first FF 610 a to the subsequent FF 610 to scan to the plurality of FFs 610. Set the pattern column. The scan path 615 scans by sequentially propagating logical values input from the logic circuit 600 to the plurality of FFs 610 from each FF 610 to the subsequent FFs 610 as a result of the operation of the DUT 20 with the scan pattern string set. Outputs sequentially from the output terminal (Scan-out).

  Each multiplexer 620 is provided corresponding to each FF 610, and a signal from the logic circuit 600 and a signal output from the immediately preceding FF 610 in the scan path 615 (a signal input from the scan input terminal for the first multiplexer 620). Which of these is input to the FF 610 is selected. Each multiplexer 620 inputs a signal output from the immediately preceding FF 610 to the FF 610 in a test mode (TE = 1, TEB = 0) in which a scan pattern string is input to the scan input terminal. On the other hand, in a normal operation mode (TE = 0, TEB = 1) other than the test mode, a signal output from the logic circuit 600 to the FF 610 is input to the FF 610.

  The plurality of gates 630 are provided corresponding to the plurality of FFs 610, and are arranged between the wirings between the corresponding FFs 610 and the logic circuit 600 and at least one of the positive side potential and the negative side potential of the first power supply voltage. Connected. Each gate 630 is, for example, a transmission gate or the like, supplies the potential to the wiring in the test mode, and sets the wiring to high impedance in the normal mode.

  FIG. 7 shows an example of the configuration of the FF 610a according to this embodiment together with the multiplexer 620a. Since the FF 610b has the same configuration as the FF 610a, the description thereof will be omitted except for the following differences. The FF 610a includes an FF main body 700a and a buffer 710a which is an example of a first gate according to the present invention. The FF main body 700a takes in the signal input through the multiplexer 620a in accordance with the clock signal CL and the inverted clock signal CLB, and outputs it as the inverted output signal QB of the input signal Fx-in. The buffer 710a is, for example, a tristate inverter, and is provided between the corresponding FF main body 700a and the logic circuit 600. The buffer 710a sets the logic circuit 600 side to high impedance regardless of the output of the FF body 700a in the test mode, and supplies the signal Q obtained by inverting the output of the FF body 700a to the logic circuit 600 in the normal mode.

  A set of a plurality of buffers 710 and gates 630 is provided corresponding to the plurality of FF main bodies 700 and functions as a plurality of selection units according to the present invention. Each selection unit outputs either the signal output from the FF main body 700 or at least one of the positive potential and the negative potential of the first power supply voltage input to the DUT 20 as the logic element in the logic circuit 600. Select whether to supply as an input signal. More specifically, the selection unit is configured to output at least one of a positive potential and a negative potential of the first power supply voltage in a scan-in period in which a scan pattern string is input from the scan input terminal to the plurality of FFs 610. Is supplied as an input signal of a logic element in the logic circuit 600.

  FIG. 8 shows a second modification of the test timing by the defect detection apparatus 30 according to the present embodiment. This figure shows the timing when testing the DUT 20 shown in FIG. 6 and FIG. 6 and 7 includes a negative input of a first power supply voltage supplied to the logic circuit 600, and a negative input of a second power supply voltage supplied to the FF 610, the scan path 615, and the multiplexer 620. Are electrically separated. Thereby, the defect detection device 30 can boost the power supply voltage of the logic circuit 600 while operating each FF 610 and each multiplexer 620 in the DUT 20 to perform scan-in.

  The initialization unit 242 according to the present embodiment sets the first power supply voltage to the initial voltage value in the state where the second power supply voltage is the operating voltage of the FF 610 and the multiplexer 620 in S310 of FIG. Thereby, the initialization unit 242 can set the potential of the wiring to be tested in the logic circuit 600 within the range of 0 V from the initial voltage value while enabling scan-in.

  Next, the booster 244 according to the present embodiment boosts the first power supply voltage from the initial voltage value to the operating voltage of the logic element. While boosting the first power supply voltage, the scan pattern supply unit 220 sets the DUT 20 in the test mode, inputs the scan pattern string to the scan input terminal, and sets the FF 610 to the plurality of FFs 610. Thereby, the defect detection device 30 can perform the scan-in operation and the boosting of the first power supply voltage in parallel.

  Next, the inverting operation unit 250 according to the present embodiment inverts the first output signal by outputting a signal based on the scan pattern from at least one FF 610 in S340 of FIG.

  As described above, according to the DUT 20 shown in FIG. 6, the first power supply voltage supplied to the logic circuit 600 can be boosted in parallel with the scan-in operation.

  FIG. 9 shows an example of the power supply voltage supplied to the DUT 20 according to the present embodiment. In the DUT 20 according to the present embodiment, the FET substrate (first substrate) included in the logic elements on the plurality of FFs 610 and the scan path 615 and the FET substrate (second substrate) included in the logic elements in the logic circuit 600. It is electrically separated from (straight). The FET substrate in the buffer 710 illustrated in FIG. 7 and the gate 630 illustrated in FIG. 6 is electrically connected to the substrate included in the logic element on the scan path 615, and the logic element in the logic circuit 600 Is electrically isolated from the FET substrate. As a result, the defect detection device 30 can independently control the negative potential of the first power supply voltage and the negative potential of the second power supply voltage, and is independent of the negative potential of the first power supply voltage. The on / off state of the buffer 710 and the gate 630 can be controlled.

  FIG. 9A shows a state where the logic value of the first output signal is set to a predetermined expected value after the first power supply voltage is boosted and before the inversion of the first output signal. An example of the first power supply voltage supplied to the logic circuit 600 side and the second power supply voltage supplied to the scan path 615 side when the input to the logic circuit 600 having elements is set to the L level is shown.

  In this case, the initialization unit 242 sets the DUT 20 as the test mode and disconnects the connection between the FF 610 and the logic circuit 600 by the buffer 710, and sets the negative input VSS2 of the second power supply voltage to the ground potential and the positive side. The input VDD2 is the power supply potential, and the positive input VDD1 and the negative input VSS1 of the first power supply voltage are the ground potential. Next, the booster 244 boosts the first power supply voltage by increasing the potential of the positive input VDD1 of the first power supply voltage from the ground potential to the power supply potential. The scan pattern supply unit 220 inverts the logic value of the first output signal by connecting the FF 610 and the logic circuit 600 with the DUT 20 in the normal mode and inverting the output of the FF 610.

  FIG. 9B shows a case where the logic value of the first output signal is set to a predetermined expected value after the first power supply voltage is increased and before the inversion of the first output signal. An example of the first power supply voltage supplied to the logic circuit 600 side and the second power supply voltage supplied to the scan path 615 side when the input to the logic circuit 600 having elements is set to the H level is shown.

  In this case, the initialization unit 242 sets the DUT 20 in the test mode and disconnects the connection between the FF 610 and the logic circuit 600 by the buffer 710, and sets the negative input VSS2 of the second power supply voltage to the ground potential and the positive side. The input VDD2 is a power supply potential, and the positive input VDD1 and the negative input VSS1 of the first power supply voltage are power supply potentials. Next, the booster 244 boosts the first power supply voltage by lowering the potential of the negative input VSS1 of the first power supply voltage from the power supply potential to the ground potential. The scan pattern supply unit 220 inverts the logic value of the first output signal by connecting the FF 610 and the logic circuit 600 with the DUT 20 in the normal mode and inverting the output of the FF 610.

  According to the DUT 20 described above, the power supply voltage of the logic circuit 600 can be boosted while operating each FF 610 and each multiplexer 620 in the DUT 20 to perform scan-in. Therefore, the test time can be shortened in parallel with the scan-in and the boosting that require a certain amount of time.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

1 shows an example of a logic circuit 10 to be tested according to an embodiment of the present invention. The structure of the defect detection apparatus 30 which concerns on embodiment of this invention is shown. The operation | movement flow of the defect detection apparatus 30 which concerns on embodiment of this invention is shown. The timing of the test by the defect detection apparatus 30 which concerns on embodiment of this invention is shown. The 1st modification of the timing of the test by the defect detection apparatus 30 which concerns on embodiment of this invention is shown. 2 shows an exemplary configuration of a DUT 20 according to an embodiment of the present invention. An example of a structure of FF610a which concerns on embodiment of this invention is shown. The 2nd modification of the timing of the test by the defect detection apparatus 30 which concerns on embodiment of this invention is shown. An example of the power supply voltage supplied to DUT20 which concerns on embodiment of this invention is shown.

Explanation of symbols

10 logic circuit 15 failure model 20 DUT
30 Defect Detection Device 100 Logic Element 110 Logic Element 120 Logic Element 122 FET
124 FET
130 logic element 150 wiring 160 fault resistance 170 wiring capacity 180 wiring capacity 200 control device 210 test signal supply unit 220 scan pattern supply unit 230 determination unit 240 power supply control unit 242 initialization unit 244 boosting unit 250 inversion operation unit 260 acquisition unit 270 failure Detection unit 600 logic circuits 610a-b FF
615 Scan campus 620a-b Multiplexer 630a-b Gate 700a-b FF body 710a-b Buffer

Claims (17)

An electronic device having a logic element at a preceding stage and a logic element at a subsequent stage of the preceding logic element, a defect detection device that detects a defect in a wiring that inputs a first output signal output from the preceding logic element to the subsequent logic element. And
An initialization unit for setting a power supply voltage supplied to the electronic device to an initial voltage value smaller than a threshold voltage of a logic element included in the electronic device;
A boosting unit that boosts the power supply voltage from the initial voltage value to the operating voltage of the logic element at a speed at which the logic value of the second output signal output from the subsequent logic element does not change;
An inverting operation unit for inverting the logic value of the first output signal output by the preceding logic element in a state where the power supply voltage is boosted to the operating voltage;
A defect detection unit that detects a connection failure between the preceding logic element and the succeeding logic element based on a delay time from when the first output signal is inverted to when the second output signal is inverted. Detection device.   The defect detection apparatus according to claim 1, wherein the initialization unit sets the power supply voltage to the initial voltage value of substantially 0V.   2. The defect detection device according to claim 1, wherein the boosting unit boosts the power supply voltage with a ramp waveform having an inclination that does not change a logical value of the second output signal output from the subsequent logic element.   When the signal input terminal of the electronic device is set to the H level so that the logic value of the first output signal is set to a predetermined expected value after the power supply voltage is boosted and before the first output signal is inverted. 2. The defect detection apparatus according to claim 1, wherein the unit inputs a voltage substantially equal to the power supply voltage to a signal input terminal of the electronic device after starting the boosting of the power supply voltage.   When the signal input terminal of the electronic device is set to L level so that the logic value of the first output signal is set to a predetermined expected value after the power supply voltage is boosted and before the first output signal is inverted. The failure detection apparatus according to claim 1, wherein the unit inputs a voltage having substantially the same value as the initial voltage value to a signal input terminal of the electronic device after starting the boosting of the power supply voltage. An acquisition unit for acquiring the second output signal when a preset reference delay time elapses after inverting the first output signal;
The defect detection unit detects a connection failure between the front-stage logic element and the rear-stage logic element on the condition that the second output signal acquired by the acquisition unit has not been inverted. Defect detection device. On the condition that the logic value of the second output signal has changed while the boosting unit boosts the power supply voltage from the initial voltage value to the operating voltage, the initialization unit sets the power supply voltage to The defect detection device according to claim 1, wherein the initial voltage value is set again, and the boosting unit boosts the power supply voltage at a slower speed than the previous time. The electronic device has a plurality of sets of preceding logic elements and succeeding logic elements,
In the case of sequentially detecting a defect in wiring between each of the preceding logic element and the succeeding logic element,
The initialization unit tests whether or not there is a connection failure between one of the preceding logic elements and one of the subsequent logic elements, and then determines whether or not there is a connection failure between the other preceding logic elements and the other following logic elements. The defect detection device according to claim 1, wherein the power supply voltage is set to the initial voltage value before testing. A test signal supply unit for supplying a test signal to the electronic device;
A determination unit that determines whether the logical operation of the electronic device is good or not based on a signal output from the electronic device in response to the test signal;
The initialization unit is configured to test the presence or absence of a connection failure between the front-stage logic element and the rear-stage logic element after the logic operation test of the electronic device by the test signal supply unit and the determination unit is completed. The defect detection device according to claim 1, wherein a power supply voltage is set to the initial voltage value. The electronic device is
A plurality of flip-flops operated by a second power supply voltage different from the first power supply voltage supplied to the preceding logic element and the subsequent logic element;
The plurality of flip-flops are connected in cascade, and a scan pattern sequence sequentially input from a scan input terminal of the electronic device is sequentially propagated from the leading flip-flop to the succeeding flip-flop, to the plurality of flip-flops. A scan path for setting a scan pattern sequence, and
The initialization unit sets the first power supply voltage to the initial voltage value in a state where the second power supply voltage is the operating voltage of the flip-flop.
The defect detection device is configured to input a scan pattern string to the scan input terminal while the boosting unit boosts the first power supply voltage from the initial voltage value to the operating voltage of the logic element. The defect detection device according to claim 1, further comprising: a scan pattern supply unit configured to be set in the flip-flop.   The defect detection device according to claim 10, wherein the inversion operation unit inverts the first output signal by outputting a signal based on a scan pattern from at least one of the flip-flops. The negative input of the first power supply voltage and the negative input of the second power supply voltage are electrically separated,
The first-stage logic element and the second-stage logic element are provided from one flip-flop so that the logic value of the first output signal is set to a predetermined expected value after the power supply voltage is boosted and before the first output signal is inverted. When the input to the logic circuit is set to H level,
In the state where the connection between the flip-flop and the logic circuit is disconnected, the initialization unit uses the negative input of the second power supply voltage as a ground potential and the positive input as a power supply potential. The power supply voltage positive input and negative input are the power supply potential.
The defect according to claim 10, wherein the boosting unit boosts the first power supply voltage by lowering the negative input potential of the first power supply voltage from the power supply potential to the ground potential. Detection device. An electronic device having a function of causing a defect detection device to detect a defect in wiring between logic elements,
A logic circuit having a logic element in the previous stage, and a logic element in the subsequent stage that inputs the first output signal output from the preceding logic element;
A plurality of flip-flops that operate with a second power supply voltage different from the first power supply voltage supplied to the preceding-stage logic element and the subsequent-stage logic element;
The plurality of flip-flops are connected in cascade, and a scan pattern sequence sequentially input from the scan input terminal of the electronic device is sequentially propagated from the leading flip-flop to the succeeding flip-flop, to the plurality of flip-flops. A scan path for setting a scan pattern row, and
A signal provided corresponding to each of the plurality of flip-flops and output from the flip-flop, or at least one of a positive potential and a negative potential of the first power supply voltage input to the electronic device An electronic device comprising: a plurality of selection units that respectively select which of the signals to be supplied as input signals to the logic elements in the logic circuit.   In the scan-in period in which a scan pattern string is input from the scan input terminal to the plurality of flip-flops, the selection unit sets at least one of a positive potential and a negative potential of the first power supply voltage. The electronic device according to claim 13, wherein the electronic device is supplied as an input signal of a logic element in the logic circuit. The selection unit includes:
The test circuit is provided between the corresponding flip-flop and the logic circuit, and in the test mode in which a scan pattern string is input to the scan input terminal, the logic circuit side is set to high impedance regardless of the output of the flip-flop, and the test mode A first gate for supplying the output of the flip-flop to the logic circuit in a normal mode other than
Provided between a wiring between the first gate and the logic circuit and at least one of a positive potential and a negative potential of the first power supply voltage, and the potential is applied to the wiring in the test mode. The electronic device according to claim 14, further comprising: a second gate that supplies and sets the wiring to high impedance in the normal mode. A first substrate of FETs on the plurality of flip-flops and the scan path and a second substrate of FETs in the logic circuit are electrically separated;
The electronic device according to claim 15, wherein a substrate of the FET in the first gate and the second gate is electrically connected to the first substrate. In an electronic device having a preceding-stage logic element and a following-stage logic element, a defect detection method for detecting a defect in a wiring that inputs a first output signal output from the preceding-stage logic element to the following-stage logic element. And
An initialization step of setting a power supply voltage supplied to the electronic device to an initial voltage value smaller than a threshold voltage of a logic element included in the electronic device;
A boosting step of boosting the power supply voltage from the initial voltage value to the operating voltage of the logic element at a speed at which the logic value of the second output signal output from the subsequent logic element does not change;
An inversion operation step of inverting the logic value of the first output signal output from the preceding logic element in a state where the power supply voltage is boosted to the operation voltage;
A defect detecting step of detecting a connection defect between the preceding logic element and the succeeding logic element based on a delay time from inverting the first output signal to inverting the second output signal. Detection method.

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