JP2004264109A - Scan test circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To detect a failure of a scan chain without using an LSI tester. <P>SOLUTION: The circuit comprises: a pulse generator 1100 for inputting a one pulse signal into a first stage of the scan chain, first; counter circuits 1750-1950 for counting by clock signals; comparators for verifying one pulse signal output from a last stage of the scan chain when the counter circuits 1750-1950 count for the number of steps of the scan chains; a chain failure determination circuit 1400 for determination whether output verification for all scan chains by the comparators 1740-1940 is successful or not; and a disconnection circuit 1500 for disconnecting a source fuse 1600 for semiconductor LSI, when the output verification is not successful in any scan chain. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a scan test design technique for detecting a stuck-at fault in an internal logic element of a semiconductor integrated circuit device, and more particularly, to a scan test circuit capable of detecting a scan chain fault without using a tester device. .
[0002]
[Prior art]
2. Description of the Related Art A scan test technique for a semiconductor integrated circuit is a technique for detecting a stuck-at fault in all logic elements and wirings constituting a circuit. A scan test is generally performed in which a scan chain in which flip-flops are configured in the form of a shift register is constructed, and a screening for a stuck-at fault of a logic element and a wiring is performed by patterning from outside the semiconductor element at the time of shipping inspection. Is a scan test circuit.
[0003]
FIG. 2 is a block diagram showing a configuration of a conventional scan test circuit. In FIG. 2, a semiconductor integrated circuit includes a first scan chain including a plurality of flip-flops 2730, 2731, and 2732, and a second scan including a plurality of flip-flops 2830, 2831, and 2832. A chain includes an n-th scan chain including a plurality of flip-flops 2930, 2931, and 2932.
[0004]
Each scan chain includes scan-in terminals 2710, 2810, 2910 for inputting signals to the first-stage flip-flop, and scan-out terminals 2760, 2860, 2960 for outputting signals of the last-stage flip-flop. Further, the semiconductor integrated circuit includes a clock terminal 2200 for inputting a clock and a reset terminal 2300 for resetting all flip-flops.
[0005]
In the scan test, data from the scan-in terminals 2710, 2810, and 2910 are input to a plurality of flip-flops constituting the first to n-th scan chains while repeating the shift operation, and then, the normal operation is performed in the capture operation. The operation is executed, the response of the logic circuit is taken into the flip-flop, and the state of the plurality of flip-flops constituting each scan chain is sequentially output from the respective scan-out terminals while repeating the shift operation again.
[0006]
By comparing this output with the state of the model in which the semiconductor integrated circuit has no stuck-at fault, the stuck-at fault of the semiconductor integrated circuit is detected. The above series of operations are repeated by changing the pattern input from the scan-in terminal, and the pattern output from the scan-out terminal is repeatedly determined by a semiconductor integrated circuit inspection device (hereinafter, referred to as an LSI tester). A stuck-at fault inspection of elements and wiring existing in the circuit is performed.
[0007]
In recent years, a scan chain has been used to apply stress to a semiconductor integrated circuit in a burn-in test. Further, a BIST method of incorporating a pattern generator in a semiconductor integrated circuit and performing a self test has been widely adopted. In some cases, the efficiency of a semiconductor integrated circuit test is improved by enabling a BIST test to be performed during a burn-in test (for example, see Patent Document 1).
[0008]
[Patent Document 1]
Japanese Patent Application Laid-Open No. 09-55411
[Problems to be solved by the invention]
In recent years, as semiconductor integrated circuits have become finer and larger, failures in scan chains and scan flip-flops mounted for implementing scan tests have become obstacles to inspection. As a countermeasure, in an inspection process, it is common to first inspect a scan chain circuit for a failure with an LSI tester, and then execute a scan test.
[0010]
However, in the above-described conventional technology, it is necessary to first test the mounted scan test circuit itself by using the LSI tester before testing the stuck-at fault of the semiconductor integrated circuit by using the LSI tester, which increases the test cost. There is.
[0011]
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a scan test circuit capable of detecting a scan chain failure without using an LSI tester in a scan test design technique for a semiconductor integrated circuit. I do.
[0012]
[Means for Solving the Problems]
A scan test circuit according to a first aspect of the present invention is a scan test circuit including a scan chain in which flip-flops are formed in a shift register shape, and inputs a one-pulse signal to a first-stage flip-flop of the scan chain at the start of input of a clock signal. Pulse generating means, counter means for counting by a clock signal, and when the counter means counts the number of flip-flops constituting the scan chain, the output of the last flip-flop of the scan chain outputs a one-pulse signal And a scan chain failure determination unit that determines whether output verification by the comparison unit has been successful for all scan chains.
[0013]
According to the above configuration, the output of the flip-flop at the last stage of the scan chain is verified using the counter unit that counts the number of stages of the flip-flops constituting the scan chain, so that the scan chain is functioning normally. Can be determined, the failure of the scan test means can be detected without using an LSI tester.
[0014]
The scan test circuit according to claim 2 is the scan test circuit according to claim 1, wherein, when the output verification by the comparison unit does not succeed for any of the scan chains in the determination result of the scan chain failure determination unit. And a fuse cutting means for cutting a power supply fuse of the semiconductor integrated circuit.
[0015]
According to the above configuration, when it is determined that there is a failure in the scan chain, the power supply fuse of the semiconductor integrated circuit on which the scan test circuit is mounted can be blown. Defective products can be easily screened by performing a power supply contact test during inspection.
[0016]
A scan test circuit according to a third aspect is the scan test circuit according to the first aspect, further comprising storage means for storing a determination result of the scan chain failure determination means.
[0017]
According to the above configuration, when it is determined that there is a failure in the scan chain, the determination result can be stored in the storage unit. The defective product can be easily screened by checking the determination result stored in the storage device.
[0018]
A semiconductor integrated circuit device according to a fourth aspect includes the scan test circuit according to any one of the first to third aspects.
[0019]
A semiconductor wafer according to a fifth aspect of the present invention includes a semiconductor integrated circuit device having the scan test circuit according to the first aspect, and a fuse cutting means according to the second aspect mounted outside the semiconductor integrated circuit device.
[0020]
According to the above configuration, the chip size of the semiconductor integrated circuit device finally packaged as a product can be reduced by mounting the fuse cutting circuit outside the semiconductor integrated circuit device.
[0021]
A semiconductor wafer according to a sixth aspect of the present invention includes a semiconductor integrated circuit device having the scan test circuit according to the first aspect, and the storage means according to the third aspect mounted outside the semiconductor integrated circuit device.
[0022]
According to the above configuration, by mounting the storage element outside the semiconductor integrated circuit device, the chip size of the semiconductor integrated circuit device finally packaged as a product can be reduced.
[0023]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing a configuration of a scan test circuit according to one embodiment of the present invention. In FIG. 1, a semiconductor integrated circuit includes a first scan chain including a plurality of flip-flops 1730, 1731, and 1732, and a second scan including a plurality of flip-flops 1830, 1831, and 1832. A chain includes an n-th scan chain including flip-flops 1930, 1931, and 1932.
[0024]
The semiconductor integrated circuit includes scan-in terminals 1710, 1810, and 1910 for inputting signals to each scan chain, a scan-out terminal (not shown) for outputting a signal of a flip-flop at the last stage of each scan chain, A clock terminal 1200 for inputting a clock and a reset terminal 1300 for resetting all flip-flops are provided.
[0025]
Further, the semiconductor integrated circuit includes a one-pulse generator 1100, selectors 1720, 1820, 1920, counters 1750, 1850, 1850, comparators 1740, 1840, 1940, a scan chain failure determination circuit 1400, a fuse cutting circuit 1500, and a power fuse 1600. Prepare.
[0026]
One-pulse generator 1100 generates a one-pulse having a reset signal input from reset terminal 1300 as a start edge of a pulse and a clock signal input from clock terminal 1200 as an end edge of the pulse.
[0027]
The selectors 1720, 1820, and 1920 switch the input of each of the first to n-th scan chains, input the signal of the one-pulse generator 1100 to each scan chain when a failure of the scan test circuit is detected, and input each scan-in signal during the scan test. The signal from the terminal is input to each scan chain.
[0028]
The counters 1750, 1850, and 1850 respectively correspond to the first to n-th scan chains, are reset by a reset signal, count clock signals by the number of stages of each scan flip, and count values by the number of stages of each scan flip. When it reaches, it outputs a signal indicating this.
[0029]
Comparators 1740, 1840, and 1940 correspond to the first to n-th scan chains, respectively, and compare the output of the last-stage flip-flop of each scan chain with the output of counters 1750, 1850, and 1850, respectively. Output match detection.
[0030]
The scan chain failure determination circuit 1400 calculates the logical product of the outputs of all the comparators 1740, 1840, and 1940. The fuse cutting circuit 1500 receives the output of the scan chain failure determination circuit 1400 and controls cutting or non-cutting of the fuse. The power fuse 1600 cuts the fuse in response to a cut signal from the fuse cutting circuit 1500.
[0031]
If the number of flip-flops in each scan chain is different, the coincidence detection outputs of the comparators 1740, 1840, and 1940 are temporarily held at the time when the outputs of the counters 1750, 1850, and 1850 are obtained. When the outputs of 1750, 1850, and 1850 are obtained, the scan chain failure determination circuit 1400 is configured to calculate the logical product of the temporarily held match detection outputs.
[0032]
The operation at the time of the scan test is the same as that of the conventional circuit. In the selectors 1720, 1820, and 1920, a signal from each scan-in terminal is selected. First, data from the scan-in terminals 1710, 1810, and 1910 are input to a plurality of flip-flops constituting the first to n-th scan chains while repeating the shift operation, and then the normal operation is performed by the capture operation. Then, the response of the logic circuit is taken into the flip-flop, and the states of the flip-flops of a plurality of stages constituting each scan chain are sequentially output from the respective scan-out terminals while repeating the shift operation again.
[0033]
By comparing this output with the state of the model in which the semiconductor integrated circuit has no stuck-at fault, the stuck-at fault of the semiconductor integrated circuit is detected. The above series of operations is repeated by changing the pattern input from the scan-in terminal, and the pattern output from the scan-out terminal is repeatedly determined by an LSI tester. Is carried out.
[0034]
Next, an operation for detecting a failure of the scan test circuit will be described. After the power of the semiconductor integrated circuit is turned on, first, a reset signal is input once from a reset terminal 1300, and then a clock signal is input from a clock terminal 1200. Thus, the one-pulse generator 1100 generates a one-pulse signal having the reset signal as the start edge of the pulse and the clock signal as the end edge of the pulse.
[0035]
When detecting a failure in the scan test circuit, the selectors 1720, 1820, and 1920 select the signal of the one-pulse generator 1100 and input the signal to each scan chain. The one-pulse signal that has reached each scan chain repeats the shift operation on the scan chain by the clock signal, and reaches the final-stage scan flip-flop.
[0036]
At this time, since the counters 1750, 1850, and 1850 are counting clock signals, the count value of the counter corresponding to the scan chain in which the one-pulse signal has reached the final-stage scan flip-flop has reached the number of scan flip-stages. , A signal indicating this is output from the counter.
[0037]
As a result, the output of the counter coincides with the one-pulse signal that reaches the flip-flop of the last stage. Therefore, the comparators 1740, 1840, and 1940 detect the coincidence of both, and the scan chain failure determination circuit 1400 detects the coincidence of the comparators By taking the logical product of the outputs, it is possible to determine that the scan chain is functioning properly and that there is no failure in the scan test circuit.
[0038]
On the other hand, when a flip-flop has failed in any of the scan chains, a one-pulse signal is output from the last flip-flop of the corresponding scan chain at the timing when the counters 1750, 1850, and 1850 have counted the number of stages of the scan flip. It is not output, and it is not matched by the match detection by the comparator.
[0039]
As a result, it is possible to determine that a scan test circuit has a failure in any of the scan chains by taking the logical product of the coincidence detection outputs of the comparators in the scan chain failure determination circuit 1400. The scan chain failure determination circuit 1400 transmits this to the fuse cutting circuit 1500, and the fuse cutting circuit 1500 transmits a cutting signal to the power supply fuse 1600 to cut the fuse.
[0040]
A semiconductor integrated circuit with a blown power supply fuse can be easily screened by performing a power supply contact test when performing inspection using an LSI tester in the next step, such as inspection after assembly. . According to this method, it is possible to easily realize non-defective and defective scan test circuits without using an LSI tester.
[0041]
In this embodiment, the non-defective product and the defective product are described using the fuse cutting circuit and the power supply fuse. However, instead of the fuse cutting circuit and the power supply fuse, a storage element that stores a failure determination result of the scan test circuit is used. Even when the inspection is performed using the LSI tester in the next step, the same result can be obtained by checking the judgment result stored in the storage element.
[0042]
Furthermore, in the above-described embodiment, the memory element for storing the failure determination result of the fuse cutting circuit and the power supply fuse or the scan test circuit is provided inside the semiconductor integrated circuit. However, these are provided outside the semiconductor integrated circuit, for example, on the semiconductor wafer. The same effect can be obtained even if it is provided on a scribe lane.
[0043]
【The invention's effect】
As described above, according to the present invention, the scan test circuit itself can determine whether or not the scan chain is functioning normally. Therefore, the failure detection of the scan test circuit can be performed without using an LSI tester. It can be carried out. Further, when a failure of the scan test circuit is detected, the power supply fuse of the semiconductor integrated circuit is blown, so that efficient screening of defective products in the next step can be performed, and the inspection cost can be reduced. it can.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a scan test circuit according to one embodiment of the present invention.
FIG. 2 is a block diagram showing a configuration of a conventional scan test circuit.
[Explanation of symbols]
1100 One pulse generator 1200 Clock terminal 1300 Reset terminal 1400 Scan chain failure determination circuit 1500 Fuse cutting circuit 1600 Power supply fuse 1710, 1810, 1910 Scan-in terminal 1720, 1820, 1920 Selector 1730, 1731, 1732, 1830, 1831, 1832, 1930 , 1931, 1932 Scan flip-flops 1740, 1840, 1940 Comparator 1750, 1850, 1950 Counter 2200 Clock terminal 2300 Reset terminal 2710, 2810, 2910 Scan-in terminal 2730, 2731, 2732, 2830, 2831, 2832, 2930, 2931, 2932 scan flip-flop 2760, 2860, 2960 scan-out terminal

Claims (6)

A scan test circuit including a scan chain in which flip-flops are configured in a shift register shape,
Pulse generation means for inputting a one-pulse signal to a first-stage flip-flop of a scan chain at the start of input of a clock signal;
Counter means for counting by a clock signal;
Comparing means for verifying that the output of the last-stage flip-flop of the scan chain outputs a one-pulse signal when the counter counts the number of flip-flops constituting the scan chain;
Scan chain failure determination means for determining whether output verification by the comparator has succeeded for all scan chains,
Scan test circuit comprising: 2. A fuse cutting unit according to claim 1, further comprising: a fuse cutting unit that cuts a power supply fuse of the semiconductor integrated circuit when the output verification by the comparison unit does not succeed for any of the scan chains in the determination result of the scan chain failure determination unit. Scan test circuit. 2. The scan test circuit according to claim 1, further comprising storage means for storing a determination result of said scan chain failure determination circuit. A semiconductor integrated circuit device comprising the scan test circuit according to claim 1. A semiconductor integrated circuit device comprising the scan test circuit according to claim 1, and a semiconductor wafer on which the fuse cutting means according to claim 2 is mounted outside the semiconductor integrated circuit device. A semiconductor wafer comprising the semiconductor integrated circuit device provided with the scan test circuit according to claim 1 and the storage means according to claim 3 mounted outside the semiconductor integrated circuit device.

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