JP2017063442A - Reset circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To control a reset signal to a low level with certainty, upon power activation.SOLUTION: In a reset circuit, a series connection of a first MOS transistor and a diode-connected second MOS transistor that has the same channel type as the first MOS transistor, and a third MOS transistor that has a different channel type from the first MOS transistor and that is connected in series to the second MOS transistor, are connected between an application end side of a power supply voltage and a ground end side. An input signal is input to gates of the first MOS transistor and the third MOS transistor, and an output signal is output from a connection point between the second MOS transistor and the third MOS transistor.SELECTED DRAWING: Figure 62

Description

  The present invention relates to a reset circuit.

  As a data holding device used for a sequential circuit such as a latch circuit, for example, a circuit in which two inverter circuits are connected in series in a loop shape is known. However, such a data holding device normally can hold data only in a volatile manner, so that data is lost when the power is turned off. That is, even if the power is turned on again, the data before the power is turned off cannot be restored.

  Therefore, when the sequence processing using the latch circuit having such a data holding device is interrupted for some reason, the power must be kept on in order to hold the data. Consume. In addition, when the sequence process is interrupted due to a power failure or the like, the process must be restarted from the beginning, resulting in a large time loss.

  In order to solve such a problem, Patent Document 1 by the present applicant discloses and proposes a data holding device that holds data in a nonvolatile manner using a ferroelectric capacitor.

  FIG. 71 is a circuit diagram showing a conventional example of a data holding device.

  The data holding device of this figure is a signal line in a memory element having a loop structure part (a part surrounded by a broken line in the figure) composed of inverters INVx and INVy (thick line part in the figure in which the held data appears as a voltage signal). A ferroelectric element CL is connected to the top.

  When the power is shut off, data is written to the ferroelectric element CL by setting the residual polarization state of the ferroelectric element CL using the voltage value on the signal line. Such a write operation makes it possible to retain data in a nonvolatile manner even after the power is shut off.

  On the other hand, when reading data written in the ferroelectric element CL, a voltage pulse is applied from the plate line PL to one end of the ferroelectric element CL in a state where the node N is left floating after the power is turned on. A voltage signal corresponding to the remanent polarization state of the body element CL is generated at the node N. The voltage signal generated at the node N is subjected to data determination (0/1 determination) according to the threshold value of the inverter INVx.

  Moreover, as another prior art relevant to this invention, patent document 2 by the present applicant can be mentioned.

Japanese Patent No. 3737472 JP 2009-206942 A

  Certainly, the conventional data holding device is advantageous because it can hold data even when the power is cut off.

  However, in the conventional data holding device, since the ferroelectric element CL in the storage element becomes a huge load capacity existing on the signal line during normal operation, the speed of the storage element and the increase in power consumption may occur. there were.

  In the conventional data holding device, when reading data, it is necessary to make the node N floating so that charges corresponding to the residual polarization state of the ferroelectric element CL do not escape to the power supply line or the ground line (pass switch). SWx and SWy must be turned off. Therefore, in the conventional data holding device, four types of clock signals (CKA, / CKA, CKB, / CKB) are required as drive clock signals for the path switches SWx and SWy, which may increase power consumption. there were.

  Further, in the conventional data holding device, as shown in FIGS. 71 and 72, the residual of the ferroelectric element CL is obtained by using capacitive coupling between the ferroelectric element CL and the gate capacitance of the transistor constituting the inverter INVx. The voltage signal Vout corresponding to the polarization state has been read out. However, compared with the case where the capacitance of the ferroelectric element CL (upward solid line in FIG. 72) is large (several hundreds [F]), the gate capacitance of the transistor constituting the inverter INVx (in FIG. 72). Since the lower right solid line) has a small capacity (several [F]), the voltage signal Vout appearing at the node N is as small as about 10 to 100 [mV], and the threshold value of the inverter INVx is set and read accordingly. It was difficult to perform 0/1 judgment of data from the viewpoint of device variation.

  In the case of a conventional CMOS circuit, when the power supply voltage is lowered to 0.6 [V], the data in the data holding device changes due to the fluctuation of the power supply voltage generated when the circuit block is turned on / off. That is, the problem that the margin for fluctuation of the power supply voltage disappears is remarkable.

  In addition, since a non-volatile data holding device incorporating a ferroelectric element does not require a power supply voltage for the data holding operation itself, the problem of data corruption associated with fluctuations in the power supply voltage can be solved. Due to the characteristics of the body element, it was difficult to drive the ferroelectric element using a power supply voltage of 0.6 [V] and write data into the ferroelectric element. That is, when the CMOS circuit is driven with a power supply voltage of 0.6 [V], it is difficult to drive the ferroelectric element using the same power supply voltage.

  Conversely, when the CMOS circuit is driven with a power supply voltage of 3.3 [V], driving the ferroelectric element using the same power supply voltage results in unnecessarily large power consumption. .

  In the above conventional data holding device, the stored data of the ferroelectric element may be destroyed when the power is turned on / off, and the clock input to the loop structure portion is performed when the data is saved / restored to the ferroelectric element. There are many problems to be considered when putting the data holding device into practical use, such as the necessity of stopping and the fact that the analog characteristics of the ferroelectric element cannot be evaluated after the data holding device is incorporated into the system.

  In addition, the conventional data holding device has a built-in control circuit for controlling data backup (backup) / restore. This control circuit always monitors an external signal for requesting data backup / restore. Therefore, it is necessary to provide a clock supply source that constantly generates a clock signal for operation of the control circuit outside the control circuit, which causes an increase in the number of parts in the set and an increase in cost. Further, in the conventional data holding device, since the control circuit always operates, there is a problem that the power consumption of the control circuit (and thus the power consumption of the entire set) increases.

  In view of the above problems, an object of the present invention is to provide a control circuit capable of realizing a reduction in the number of components in a set and a reduction in power consumption, and a data holding device using the control circuit.

  In order to achieve the above object, the control circuit according to the present invention starts generating an internal clock signal necessary for the operation of the control unit when a specific signal pattern appears in the trigger signal, and at least the control unit performs predetermined processing. An internal clock generation unit that stops generating the internal clock signal after the generation of the internal clock signal is continued until the process is completed; a control unit that executes the predetermined process using the internal clock signal; It is set as the structure (1st structure) which has.

  In the control circuit having the first configuration, the control unit may be configured to execute different processing for each of a plurality of signal patterns appearing in the trigger signal (second configuration).

  Further, in the control circuit having the first or second configuration, the control unit is configured to operate even using an external clock signal input from the outside in addition to the internal clock signal (third configuration). Good.

  In the control circuit having any one of the first to third configurations, the control unit includes an operation mode for outputting a control signal having a constant value to the control target circuit regardless of the internal state. (Fourth configuration) is preferable.

  Further, in the control circuit having any one of the first to fourth configurations, the internal clock generation unit is configured to use a multi-stage connection structure of logic elements (fifth configuration) when generating the internal clock signal. Good.

  In the control circuit having any one of the first to fifth configurations, the internal clock generation unit may be configured to use a loop structure of a logic element (sixth configuration) when generating the internal clock signal. .

  Further, in the control circuit having any one of the first to sixth configurations, the internal clock generation unit has a configuration (seventh configuration) including a filter that removes a specific frequency component superimposed on the trigger signal. Good.

  In the control circuit having the seventh configuration, the filter may include a capacitor (eighth configuration).

  In the control circuit having the eighth configuration, the capacitor may be a ferroelectric capacitor (9th configuration).

  In the control circuit having the eighth or ninth configuration, the filter may have a configuration (tenth configuration) including a discharge circuit that discharges the capacitor in response to a reset signal.

  Further, in the control circuit having any one of the first to tenth configurations, the internal clock generation unit includes a signal propagation control circuit that performs propagation control of the trigger signal within itself (eleventh configuration). It is good to.

  In the control circuit having the eleventh configuration, the signal propagation control circuit may be a latch circuit (a twelfth configuration).

  In the control circuit having the eleventh configuration, the signal propagation control circuit may be configured as a logical sum calculator (thirteenth configuration).

  The control circuit having any one of the first to thirteenth configurations further includes a reset unit that monitors a power supply voltage and generates an internal reset signal for initializing the control unit and the internal clock generation unit. A configuration (fourteenth configuration) is preferable.

  In the control circuit having the fourteenth configuration, the reset unit outputs the internal reset signal during a period from when the power supply voltage reaches an operable voltage of the CMOS circuit until a predetermined low-level output period elapses. It is preferable to adopt a configuration (fifteenth configuration) held at a low level.

  In the control circuit having the fifteenth configuration, the reset unit includes a P-channel field effect transistor having a source connected to a power supply voltage application terminal and a gate connected to an input signal input terminal; A diode connected to the drain of the P-channel field transistor, a cathode connected to the output terminal of the internal reset signal, or a diode-connected transistor; a source connected to the ground terminal, and a gate connected to the input terminal of the input signal And an N-channel field effect transistor having a drain connected to the output terminal of the internal reset signal (a sixteenth configuration).

  In the control circuit having the sixteenth configuration, the reset unit is inserted between both gates of the P-channel field effect transistor and the N-channel field effect transistor and an input terminal of the input signal. A configuration further including an inverter (a seventeenth configuration) may be employed.

  Further, in the control circuit having the sixteenth or seventeenth configuration, the reset unit further includes a capacitor (18th configuration) connected between an output terminal of the internal reset signal and a ground terminal. Good.

  In addition, the data holding device according to the present invention is held in the loop structure unit using a plurality of logic gates connected in a loop shape to hold data and the hysteresis characteristic of the ferroelectric element. In addition to a nonvolatile storage unit that stores data in a nonvolatile manner, and a circuit separation unit that electrically isolates the loop structure unit and the nonvolatile storage unit, the loop structure unit and the nonvolatile storage unit As a means for generating a control signal for the circuit separation unit, the control circuit has any one of the first to eighteenth configurations (19th configuration).

  In the data holding device having the nineteenth configuration, the nonvolatile storage unit includes a switch element that short-circuits both ends of the ferroelectric element to a ground terminal when the data holding device is turned on / off ( The twentieth configuration is preferable.

  The data holding device having the twentieth configuration may further include a protection signal generation circuit (a twenty-first configuration) that generates a protection signal for turning on the switch element when the power supply is turned on / off. Good.

  In the data holding device having the twenty-first configuration, the switch element is an N-channel field effect transistor, and the protection signal generation circuit is configured to wait until the power supply voltage reaches at least the operable voltage of the CMOS circuit. The protection signal may be held at a high level (22nd configuration).

  In the data holding device having the twenty-second configuration, the protection signal generation circuit has a source connected to a power supply voltage application terminal, a gate connected to an input signal input terminal, and a drain output of the protection signal. A P-channel field effect transistor connected to the end; an N-channel field effect having a source connected to the ground end, a gate connected to the input end of the input signal, and a drain connected to the output end of the protection signal The P-channel field effect transistor may be configured to have a smaller on-resistance value than the N-channel field effect transistor (a twenty-third configuration).

  According to the present invention, it is possible to provide a control circuit capable of realizing a reduction in the number of components in a set and a reduction in power consumption, and a data holding device using the control circuit.

1 is a circuit diagram showing an embodiment of a data holding device according to the present invention. A circuit diagram showing a configuration example of an inverter INV6 having the level shift function (the same applies to the inverter INV7) Timing chart for explaining an operation example of the data holding device according to the present invention Circuit diagram showing signal path during normal operation Circuit diagram showing signal path during data write operation Circuit diagram showing signal path during data read operation The circuit diagram which shows the 1st modification of the data holding device which concerns on this invention A circuit diagram showing a configuration example of a three-state inverter INV6 'having the level shift function (the same applies to the inverter INV7') Timing chart for explaining another example of operation of the data holding device according to the present invention Diagram for explaining the characteristics of ferroelectric elements A diagram for explaining a data reading method using capacitive coupling between ferroelectric elements The circuit diagram which shows the 2nd modification of the data holding device which concerns on this invention The circuit diagram which shows the 3rd modification of the data holding device based on this invention Circuit diagram showing application to D flip-flop Circuit diagram showing signal path during normal operation Circuit diagram showing signal path during data write operation Circuit diagram showing signal path during data read operation The circuit diagram which shows the 4th modification of the data holding device based on this invention Timing chart for explaining an operation example of the data holding device according to the present invention Timing chart for explaining another example of operation of the data holding device according to the present invention Schematic diagram showing an example of processing switching operation by data exchange Schematic diagram showing a first layout example of a cell pattern Schematic diagram showing a second layout example of a cell pattern Schematic diagram showing a third layout example of a cell pattern Schematic diagram showing a fourth layout example of a cell pattern The circuit diagram which shows the 5th modification of the data holding device which concerns on this invention The block diagram which showed the signal pin used with the data holding device of a 5th modification Functional description table of signal pins used in the data holding device of the fifth modified example Circuit diagram showing one configuration example of sense amplifier SA Circuit diagram showing the operating state of each part of the device during normal operation Circuit diagram showing the operating state of each part of the device during data write operation Circuit diagram showing the operating state of each part of the device during data read operation Circuit diagram showing the operating state of each part of the device during test operation Timing chart for explaining analog characteristic evaluation operation of ferroelectric element Schematic diagram showing the relationship between the reference voltage signal Vref and the output signal Q Block diagram for explaining the test operation of the data holding device using the scan path Flow chart showing an example of test operation using scan campus Flow chart showing another example of test operation using scan campus The circuit diagram which shows the 6th modification of the data holding device which concerns on this invention The circuit diagram which shows the 7th modification of the data holding device which concerns on this invention The circuit diagram which shows the operation state of each part of the apparatus at the time of normal operation | movement of a 7th modification The circuit diagram which shows the operation state of each part of the apparatus at the time of the data write operation of a 7th modification The circuit diagram which shows the operation state of each part of the apparatus at the time of the data read-out operation | movement of a 7th modification The circuit diagram which shows the operation state of each part of the apparatus at the time of test operation of a 7th modification Timing chart for explaining data destruction prevention function at power on / off The figure which shows an example of inverter INV6, INV7 used when 2nd power supply voltage VDD2 is lower voltage than 1st power supply voltage VDD1 Block diagram showing one configuration example of control circuit Timing chart showing an example of basic operation by internal clock signal Timing chart showing an example of basic operation using an external clock signal Timing chart showing an example of test operation using an external clock signal The block diagram which shows the example of 1 structure of the internal clock generation part 12. Timing chart showing an example of internal clock generation operation Timing chart showing another example of internal clock generation operation Circuit diagram showing a first configuration example of the low-pass filter 121 Circuit diagram showing a second configuration example of the low-pass filter 121 Circuit diagram showing a third configuration example of the low-pass filter 121 Circuit diagram showing a fourth configuration example of the low-pass filter 121 The block diagram which shows one structural example of the pulse generation part 123 Timing chart showing an example of pulse generation operation The block diagram which shows the 1st structural example of the clock generation part 124. The block diagram which shows the 2nd structural example of the clock generation part 124. Timing chart showing clock generation operation in second configuration example The block diagram which shows the 3rd structural example of the clock generation part 124. FIG. Timing chart showing clock generation operation in third configuration example Circuit diagram showing a configuration example of a POLH circuit The figure for demonstrating the 1st application example of the POLH circuit 30. The figure for demonstrating the 2nd application example of the POLH circuit 30. The figure for demonstrating the 3rd application example of the POLH circuit 30. The figure for demonstrating the 4th example of application of the POLH circuit 30. The circuit diagram which shows the 8th modification of the data holding device based on this invention Circuit diagram showing one configuration example of the POHH circuit 40 Characteristics diagram of current Ip, In Waveform diagram showing the correlation between the power supply voltage VDD and the protection signal LRSTNL Circuit diagram showing a conventional example of a data holding device A diagram for explaining a conventional data reading method

<Data holding device>
FIG. 1 is a circuit diagram showing an embodiment of a data holding device according to the present invention.

  As shown in the figure, the data holding device of this embodiment includes inverters INV1 to INV7, pass switches SW1 to SW4, multiplexers MUX1 and MUX2, N-channel field effect transistors Q1a, Q1b, Q2a, and Q2b, The latch circuit includes dielectric elements (ferroelectric capacitors) CL1a, CL1b, CL2a, and CL2b.

  The input end of the inverter INV1 is connected to the application end of the data signal (D). The output terminal of the inverter INV1 is connected to the input terminal of the inverter INV2. The output terminal of the inverter INV2 is connected to the first input terminal (1) of the multiplexer MUX1 via the pass switch SW1. The output terminal of the multiplexer MUX1 is connected to the input terminal of the inverter INV3. The output terminal of the inverter INV3 is connected to the input terminal of the inverter INV5. The output end of the inverter INV5 is connected to the output end of the output signal (Q). The first input terminal (1) of the multiplexer MUX2 is connected to the output terminal of the inverter INV3. The output terminal of the multiplexer MUX2 is connected to the input terminal of the inverter INV4. The output terminal of the inverter INV4 is connected to the first input terminal (1) of the multiplexer MUX1 via the pass switch SW2.

  As described above, the data holding device according to the present embodiment uses the two logic gates connected in a loop (inverters INV3 and INV4 in FIG. 1) to provide a loop structure unit LOOP that holds the input data signal D. Have.

  The loop structure portion LOOP is driven by receiving a first power supply voltage VDD1 (for example, 0.6 [V]).

  The input terminal of the inverter INV6 is connected to the first input terminal (1) of the multiplexer MUX1. The output terminal of the inverter INV6 is connected to the second input terminal (0) of the multiplexer MUX2 via the pass switch SW3. The input terminal of the inverter INV7 is connected to the first input terminal (1) of the multiplexer MUX2. The output terminal of the inverter INV7 is connected to the second input terminal (0) of the multiplexer MUX1 via the pass switch SW4.

  The positive electrode end of the ferroelectric element CL1a is connected to the first plate line PL1. The negative end of the ferroelectric element CL1a is connected to the second input end (0) of the multiplexer MUX2. A transistor Q1a is connected between both ends of the ferroelectric element CL1a. The gate of the transistor Q1a is connected to the application terminal of the F reset signal FRST.

  The positive terminal of the ferroelectric element CL1b is connected to the second input terminal (0) of the multiplexer MUX2. The negative electrode end of the ferroelectric element CL1b is connected to the second plate line PL2. A transistor Q1b is connected between both ends of the ferroelectric element CL1b. The gate of the transistor Q1b is connected to the application terminal of the F reset signal FRST.

  The positive electrode end of the ferroelectric element CL2a is connected to the first plate line PL1. The negative end of the ferroelectric element CL2a is connected to the second input end (0) of the multiplexer MUX1. A transistor Q2a is connected between both ends of the ferroelectric element CL2a. The gate of the transistor Q2a is connected to the application terminal of the F reset signal FRST.

  The positive terminal of the ferroelectric element CL2b is connected to the second input terminal (0) of the multiplexer MUX1. The negative electrode end of the ferroelectric element CL2b is connected to the second plate line PL2. A transistor Q2b is connected between both ends of the ferroelectric element CL2b. The gate of the transistor Q2b is connected to the application terminal of the F reset signal FRST.

  As described above, the data holding device of this embodiment is a nonvolatile memory that stores the data D held in the loop structure portion LOOP in a nonvolatile manner using the hysteresis characteristics of the ferroelectric elements (CL1a, CL1b, CL2a, CL2b). It has a storage unit NVM.

  The nonvolatile memory unit NVM is driven by receiving a second power supply voltage VDD2 (for example, 1.2 [V]) higher than the first power supply voltage VDD1.

  Among the above-described components, the path switch SW1 is turned on / off in response to the clock signal CLK, and the path switch SW2 is turned on / off in response to the inverted clock signal CLKB (logic inverted signal of the clock signal CLK). The That is, the path switch SW1 and the path switch SW2 are turned on / off exclusively (complementarily) to each other.

  On the other hand, the path switches SW3 and SW4 are both turned on / off according to the control signal E1. Further, the signal paths of the multiplexers MUX1 and MUX2 are switched according to the control signal E2. That is, in the data holding device of this embodiment, the multiplexers MUX1 and MUX2, the inverters INV6 and INV7, and the path switches SW3 and SW4 are circuit separation units that electrically separate the loop structure unit LOOP and the nonvolatile storage unit NVM. Functions as SEP.

  Of the circuit elements forming the circuit separation unit SEP, the multiplexers MUX1 and MUX2 included in the loop structure unit LOOP are driven by the supply of the first power supply voltage VDD1, and the nonvolatile memory unit NVM The included path switches SW3 and SW4 are driven by the supply of the second power supply voltage VDD2.

  The inverters INV6 and INV7 are driven by the supply of both the first power supply voltage VDD1 and the second power supply voltage VDD2, and are exchanged between the loop structure portion LOOP and the nonvolatile storage portion NVM. It has a function as a level shifter for converting the voltage level of D.

  FIG. 2 is a circuit diagram showing a configuration example of an inverter INV6 (the same applies to the inverter INV7) having a level shift function.

  As shown in FIG. 2, the inverter INV6 (INV7) includes P-channel MOS field effect transistors P1 to P3 and N-channel MOS field effect transistors N1 to N3. The gate of the transistor N1 is connected to the input terminal IN. The source of the transistor N1 is connected to the ground terminal. The drain of the transistor N1 is connected to the drain of the transistor P1, and is also connected to the output terminal OUT. The sources of the transistors P1 and P2 are both connected to the application terminal for the second power supply voltage VDD2. The gate of the transistor P1 is connected to the drain of the transistor P2. The gate of the transistor P2 is connected to the drain of the transistor P1. The drain of the transistor P2 is connected to the drain of the transistor N2. The source of the transistor N2 is connected to the ground terminal. The gates of the transistors P3 and N3 are both connected to the input terminal IN. The source of the transistor P3 is connected to the application terminal of the first power supply voltage VDD1. The drain of the transistor P3 is connected to the drain of the transistor N3, and is also connected to the gate of the transistor N2. The source of the transistor N3 is connected to the ground terminal.

  In the inverter INV6 (INV7) configured as described above, when a high level (first power supply voltage VDD1) logic signal is input to the input terminal IN, the transistors N1 and P2 are turned on and the transistors N2 and P1 are turned off. Therefore, a low level (ground voltage GND) logic signal is output from the output terminal OUT. Conversely, when a logic signal of low level (ground voltage GND) is input to the input terminal IN, the transistors N1 and P2 are turned off and the transistors N2 and P1 are turned on. A logic signal of (second power supply voltage VDD2) is output. That is, the inverter INV6 (INV7) inverts the logic of the logic signal input to the input terminal IN, and further raises and outputs the high level potential from the first power supply voltage VDD1 to the second power supply voltage VDD2.

  Next, the operation of the data holding device configured as described above will be described in detail. In the following description, the voltage appearing at the connection node of the ferroelectric elements CL1a and CL1b is V1, the voltage appearing at the connection node of the ferroelectric elements CL2a and CL2b is V2, and the voltage appearing at the input terminal of the inverter INV4 is V3. The voltage appearing at the output terminal of the inverter INV4 is denoted by V4, the voltage appearing at the input terminal of the inverter INV3 is denoted by V5, and the voltage appearing at the output terminal of the inverter INV3 is denoted by V6.

  FIG. 3 is a timing chart for explaining an operation example of the data holding device according to the present invention. In order from the top, the power supply voltage (VDD1, VDD2), the clock signal CLK, the data signal D, the control signal E1, The voltage waveforms of the control signal E2, the F reset signal FRST, the applied voltage of the first plate line PL1, the applied voltage of the second plate line PL2, the node voltage V1, the node voltage V2, and the output signal Q are shown.

  First, the normal operation of the data holding device will be described.

  Until the time point W1, the F reset signal FRST is “1 (high level: VDD2)”, the transistors Q1a, Q1b, Q2a, Q2b are turned on, and the ferroelectric elements CL1a, CL1b, CL2a, CL2b are turned on. Since both ends are short-circuited, no voltage is applied to these ferroelectric elements CL1a, CL1b, CL2a, CL2b. The first plate line PL1 and the second plate line PL2 are both “0 (low level: GND)”.

  Further, until the time point W1, the control signal E1 is “0 (GND)”, and the path switch SW3 and the path switch SW4 are turned off. Therefore, the data write drivers (inverters INV6 and INV7 in the example of FIG. 1). ) Are all invalid.

  Further, until the time point W1, the control signal E2 is “1 (VDD1)”, and the first input terminal (1) of the multiplexer MUX1 and the multiplexer MUX2 is selected. Is formed.

  Therefore, during the high level period of the clock signal CLK, the pass switch SW1 is turned on and the pass switch SW2 is turned off, so that the data signal D is directly passed as the output signal Q. On the other hand, since the pass switch SW1 is turned off and the pass switch SW2 is turned on during the low level period of the clock signal CLK, the data signal D is latched at the falling edge of the clock signal CLK.

  FIG. 4 is a circuit diagram showing a signal path (depicted as a thick line in the drawing) during the normal operation described above.

  Next, a data write operation to the ferroelectric element will be described.

  At time points W1 to W3, the clock signal CLK is set to “0 (GND)”, and the inverted clock signal CLKB is set to “1 (VDD1)”. Accordingly, the first path switch SW1 is turned off and the second path switch is turned on. As described above, by fixing the logic of the clock signal CLK and the inverted clock signal CLKB in advance, it is possible to improve the stability of the data write operation with respect to the ferroelectric element.

  At time points W1 to W3, the F reset signal FRST is set to “0 (GND)”, the transistors Q1a, Q1b, Q2a, and Q2b are turned off, and voltage application to the ferroelectric elements CL1a, CL1b, CL2a, and CL2b is performed. Possible state.

  Further, at time points W1 to W3, the control signal E1 is set to “1 (VDD2)”, and the path switch SW3 and the path switch SW4 are turned on. Accordingly, the data write drivers (inverters INV6 and INV7 in the example of FIG. 1) are all valid.

  At the time points W1 to W3, the control signal E2 is “1 (VDD1)” and the first input terminals (1) of the multiplexer MUX1 and the multiplexer MUX2 are selected as before, so that the loop structure A normal loop is formed at the part LOOP.

  Further, at the time points W1 to W2, the first plate line PL1 and the second plate line PL2 are set to “0 (GND)”, and at the time points W2 to W3, the first plate line PL1 and the second plate line PL2 are set to “1 ( VDD2) ". That is, the same pulse voltage is applied to the first plate line PL1 and the second plate line PL2. By applying such a pulse voltage, the remanent polarization state inside the ferroelectric element is set to either the inversion state or the non-inversion state.

  More specifically, referring to the example of FIG. 3, since the output signal Q is “1 (VDD1)” at the time point W1, the node voltage V1 becomes “0 (GND)” and the node voltage V2 becomes “1”. (VDD2) ". Therefore, at time points W1 to W2, while the first plate line PL1 and the second plate line PL2 are set to “0 (GND)”, no voltage is applied across the ferroelectric elements CL1a and CL1b. Thus, a negative voltage is applied between both ends of the ferroelectric element CL2a, and a positive voltage is applied between both ends of the ferroelectric element CL2b. On the other hand, at time points W2 to W3, while the first plate line PL1 and the second plate line PL2 are set to “1 (VDD2)”, no voltage is applied across the ferroelectric elements CL2a and CL2b. Thus, a positive voltage is applied across the ferroelectric element CL1a, and a negative voltage is applied across the ferroelectric element CL1b.

  As described above, by applying the pulse voltage to the first plate line PL1 and the second plate line PL2, the remanent polarization state inside the ferroelectric element is set to either the inversion state or the non-inversion state. . Note that the remanent polarization state is reversed between the ferroelectric elements CL1a and CL1b and between the ferroelectric elements CL2a and CL2b. Further, the remanent polarization state is also reversed between the ferroelectric elements CL1a and CL2a and between the ferroelectric elements CL1b and CL2b.

  At the time point W3, the F reset signal FRST is again set to “1 (VDD2)”, so that the transistors Q1a, Q1b, Q2a, and Q2b are turned on, and between both ends of the ferroelectric elements CL1a, CL1b, CL2a, and CL2b. Since both are short-circuited, no voltage is applied to these ferroelectric elements CL1a, CL1b, CL2a, CL2b. At this time, both the first plate line PL1 and the second plate line PL2 are set to “0 (GND)”.

  At the time point W3, the control signal E1 is again set to “0 (GND)”, and the pass switch SW3 and the pass switch SW4 are turned off, so that the data write drivers (inverters INV6 and INV7 in the example of FIG. 1) Is also invalidated. Note that the control signal E2 is not questioned, but is “0 (GND)” in the example of FIG.

  At time point W4, the supply of the first power supply voltage VDD1 to the loop structure unit LOOP and the supply of the second power supply voltage VDD2 to the nonvolatile memory unit NVM are both cut off. At this time, the F reset signal FRST is maintained at “1 (VDD2)” from the time point W3, the transistors Q1a, Q1b, Q2a, Q2b are turned on, and both ends of the ferroelectric elements CL1a, CL1b, CL2a, CL2b. Both are short-circuited. Therefore, since no voltage is applied to the ferroelectric elements CL1a, CL1b, CL2a, and CL2b, even if a voltage fluctuation occurs when the power is shut off, the ferroelectric elements CL1a, CL1b, CL2a, An unintended voltage is not applied to CL2b, and garbled data can be avoided.

  FIG. 5 is a circuit diagram showing a signal path (depicted as a thick line in the drawing) during the above-described data write operation (particularly, time points W1 to W3).

  Next, a data read operation from the ferroelectric element will be described.

  At time points R1 to R5, the clock signal CLK is “0 (GND)”, and the inverted clock signal CLKB is “1 (VDD1)”. Accordingly, the first path switch SW1 is turned off and the second path switch is turned on. As described above, by fixing the logic of the clock signal CLK and the inverted clock signal CLKB in advance, it is possible to improve the stability of the data reading operation from the ferroelectric element.

  At the time point R1, the F reset signal FRST is first set to “1 (VDD1)”, the transistors Q1a, Q1b, Q2a, Q2b are turned on, and both ends of the ferroelectric elements CL1a, CL1b, CL2a, CL2b Both are short-circuited. Accordingly, since no voltage is applied to the ferroelectric elements CL1a, CL1b, CL2a, and CL2b, even if voltage fluctuation occurs when the power is turned on, the ferroelectric elements CL1a, CL1b, CL2a, and CL2b An unintended voltage is not applied, and garbled data can be avoided.

  At the time point R1, the first plate line PL1 and the second plate line PL2 are both “0 (low level: GND)”.

  At the time point R2, the control signals E1 and E2 are both set to “0 (GND)” (that is, the data write driver is invalidated, and the normal loop is invalidated in the loop structure section LOOP). In this state, the first power supply voltage VDD1 for the loop structure portion LOOP and the second power supply voltage VDD2 for the nonvolatile memory portion NVM are turned on. At this time, the signal line depicted by the thick line in FIG. 6 is floating.

  At the subsequent time point R3, the F reset signal FRST is set to “0 (GND)”, the transistors Q1a, Q1b, Q2a, Q2b are turned off, and a voltage can be applied to the ferroelectric elements CL1a, CL1b, CL2a, CL2b. On the other hand, the first plate line PL1 is set to “1 (VDD2)” while the second plate line PL2 is maintained at “0 (GND)”. By applying such a pulse voltage, voltage signals corresponding to the remanent polarization state in the ferroelectric element appear as the node voltage V1 and the node voltage V2.

  Specifically, referring to the example of FIG. 3, a relatively low voltage signal (hereinafter, the logic is referred to as WL [Weak Low]) appears as the node voltage V1, and the node voltage V2 is relatively low. A high voltage signal (hereinafter, its logic is called WH [Weak Hi]) appears. That is, a voltage difference is generated between the node voltage V1 and the node voltage V2 according to the difference in the remanent polarization state in the ferroelectric element.

  At this time, at the time point R3 to R4, the control signal E2 is set to “0 (VDD1)” and the second input terminal (0) of the multiplexer MUX1 and the multiplexer MUX2 is selected, so the logic of the node voltage V3 becomes WL, The logic of the node voltage V4 is WH. The logic of the node voltage V5 is WH, and the logic of the node voltage V6 is WL. As described above, at the time points R3 to R4, the node voltages V1 to V6 of each part of the device are still in an unstable state (the logic inversion in the inverter INV3 and the inverter INV4 is not completely performed, and the output logic is surely “0 (GND ) ”/“ 1 (VDD1) ”).

  At the subsequent time point R4, the control signal E2 is set to “1 (VDD1)”, and the multiplexer MUX1 and the first input terminal (1) of the multiplexer MUX2 are selected, so that a normal loop is formed in the loop structure section LOOP. . With such switching of the signal path, the output terminal (logic: WH) of the inverter INV4 and the input terminal (logic: WH) of the inverter INV3 are connected, and the output terminal (logic: WL) of the inverter INV3 and the input of the inverter INV4 The end (logic: WL) is connected. Therefore, no mismatch occurs in the signal logic (WH / WL) of each node, and the inverter INV3 receives the input of the logic WL and outputs the output while the normal loop is formed in the loop structure section LOOP. The inverter INV4 tries to raise the logic to “1 (VDD1)”, and receives the input of the logic WH, and tries to lower its output logic to “0 (GND)”. As a result, the output logic of the inverter INV3 is determined from the unstable logic WL to “0 (GND)”, and the output logic of the inverter INV4 is determined from the unstable logic WH to “1 (VDD1)”.

  As described above, at the time point R4, the signal (potential difference between the node voltage V1 and the node voltage V2) read from the ferroelectric element is generated in the loop structure portion LOOP when the loop structure portion LOOP is changed to the normal loop. As a result, the output data Q is restored as the output signal Q before the power is shut off (“1 (VDD1)” in the example of FIG. 2).

  After that, at the time point R5, the F reset signal FRST is again set to “1 (VDD2)”, the transistors Q1a, Q1b, Q2a, Q2b are turned on, and both ends of the ferroelectric elements CL1a, CL1b, CL2a, CL2b are connected. Since both are short-circuited, no voltage is applied to these ferroelectric elements CL1a, CL1b, CL2a, CL2b. At this time, both the first plate line PL1 and the second plate line PL2 are set to “0 (GND)”. Therefore, the data holding device is returned to the same state as before the time point W1, that is, the normal operation state.

  FIG. 6 is a circuit diagram showing a signal path (depicted as a thick line in the drawing) during the above-described data reading operation (particularly, at time points R3 to R4).

  As described above, the data holding device of this embodiment includes the loop structure portion LOOP that holds data using logic gates connected in a loop (inverters INV3 and INV4 in FIG. 1), and the ferroelectric element. A nonvolatile storage unit NVM (CL1a, CL1b, CL2a, CL2b, Q1a, Q1b, Q2a, Q2b) that stores data held in the loop structure unit LOOP in a nonvolatile manner using the hysteresis characteristics of the loop structure unit LOOP; A circuit separation unit SEP (MUX1, MUX2, INV6, INV7, SW3, SW4) for electrically separating the nonvolatile memory unit NVM, and the circuit separation unit SEP is in a normal operation of the data holding device In this configuration, the loop structure LOOP is electrically operated while keeping the voltage applied to the ferroelectric element constant. There.

  In this manner, the ferroelectric elements CL1a, CL1b, CL2a, and CL2b are not directly driven from the signal line of the loop structure portion LOOP, but the signal lines of the loop structure portion LOOP and the ferroelectric elements CL1a, CL1b, CL2a, and CL2b. Are provided with data write drivers (inverters INV6 and INV7 in FIG. 1) that also function as buffers, so that the ferroelectric elements CL1a, CL1b, CL2a, and CL2b do not serve as load capacitances in the loop structure portion LOOP. It becomes possible to do so.

  Further, if the path switches SW3 and SW4 are connected to the output terminals of the data write drivers (inverters INV6 and INV7), and the path switches SW3 and SW4 are turned on only when data is written according to the control signal E1, During normal operation, the ferroelectric elements CL1a, CL1b, CL2a, and CL2b can be prevented from being driven.

  When data is read, the logic gates (inverters INV3 and INV4 in FIG. 1) and the ferroelectrics in the loop structure unit LOOP are switched by switching the input / output paths of the multiplexers MUX1 and MUX2 according to the control signal E2. It is possible to control conduction / cutoff with the elements CL1a, CL1b, CL2a, and CL2b. Therefore, it is not necessary to add a large load clock line in order to place the specific node in a floating state, so that it is possible to avoid an increase in power consumption.

  In the data holding device according to the present embodiment, control signals E1 and E2 are newly required. However, these signals are not driven at all during normal times, unlike the clock signal that is always driven. It has little effect on power.

  Further, in the data holding device of the present embodiment, a data write driver (inverters INV6 and INV7) and multiplexers MUX1 and MUX2 are newly required, but the data holding device in an arithmetic circuit such as a CPU [Central Processing Unit]. In many cases, the area occupied by this is only a few percent, and it can be said that there is almost no influence of the area increase on the entire arithmetic circuit.

  As described above, in the data holding device of the present embodiment, the ferroelectric element is not driven wastefully during normal operation, so that the speed is increased to the same level as that of the volatile data holding device, and Low power consumption can be achieved.

  In other words, since it can be handled in the same way as a volatile data holding device, the memory element part of the existing circuit is replaced with the data holding device of the present invention without redesigning the timing design or power consumption design. Is possible. Therefore, since the existing circuit can be easily made non-volatile, for example, it is possible to realize a CPU or the like that can shut down the power without erasing data during standby or can immediately resume the operation after the power is turned on. Become.

  In the data holding device of the present embodiment, the loop structure portion LOOP and the nonvolatile memory portion NVM are driven by separately receiving the first and second power supply voltages VDD1 and VDD2 that are different from each other. The separation unit SEP has level shifters (inverters INV6 and INV7 having a level shift function in the example of FIG. 1) for converting the voltage level of data D exchanged between the loop structure unit LOOP and the nonvolatile storage unit NVM. It consists of

  With this configuration, the loop structure unit LOOP is driven at a low voltage by using the first power supply voltage VDD1, and the nonvolatile memory unit NVM (by using the second power supply voltage VDD2 higher than the first power supply voltage VDD1. More specifically, the ferroelectric elements CL1a, CL1b, CL2a, and CL2b) included in the ferroelectric elements can be appropriately driven. Therefore, the ferroelectric elements CL1a, CL1b, CL2a, and CL2b can be suitably incorporated in a low-voltage driving device (such as an ultra-low voltage processor). It is possible to provide a possible data holding device.

<First Modification>
In the above embodiment, the description has been given by taking as an example the combination of the inverter INV6 and the pass switch SW3, and the inverter INV7 and the pass switch SW4, but the configuration of the present invention is limited to this. Instead, as shown in FIG. 7, the pass switches SW3 and SW4 are omitted by using the three-state inverters INV6 ′ and INV7 ′ whose output state can be set to high impedance according to the control signal E1. It doesn't matter. In this case, the configuration of the inverter INV6 ′ (the same applies to the inverter INV7 ′) is as shown in FIG.

  FIG. 8 is a circuit diagram showing a configuration example of a three-state inverter INV6 'having the level shift function (the same applies to the inverter INV7').

  As shown in FIG. 8, the three-state inverter INV6 ′ (INV7 ′) having the level shift function can be easily realized by slightly modifying the previous inverter INV6 (INV7). . More specifically, the three-state inverter INV6 ′ (INV7 ′) includes, in addition to the configuration of FIG. 2, P-channel MOS field effect transistors P4 and P5, N-channel MOS field effect transistors N4 and N5, In addition, a configuration in which an output stage including the above is separately provided and an output signal is extracted from the output stage may be used instead of a configuration in which the output signal is extracted from the drain of the transistor P1.

  The source of the transistor P4 that forms the output stage is connected to the application terminal of the second power supply voltage VDD2. The gate of the transistor P4 is connected to the application terminal of the inversion control signal E1 bar. The drain of the transistor P4 is connected to the source of the transistor P5. The drain of the transistor P5 is connected to the drain of the transistor N4, and is also connected to the output terminal OUT. The gates of the transistors P5 and N4 are both connected to the drain of the transistor P2. The source of the transistor N4 is connected to the drain of the transistor N5. The source of the transistor N5 is connected to the ground terminal. The gate of the transistor N5 is connected to the application end of the control signal E1.

  In the three-state inverter INV6 ′ (INV7 ′) having the above configuration, when the control signal E1 is at the high level (second power supply voltage VDD2), the logic of the high level (first power supply voltage VDD1) at the input terminal IN. When a signal is input, a low level (ground voltage GND) logic signal is output from the output terminal OUT. Conversely, when a low level (ground voltage GND) logic signal is input to the input terminal IN, the output terminal OUT A logic signal of a high level (second power supply voltage VDD2) is output from OUT. That is, when the control signal E1 is at a high level, the inverter INV6 ′ (INV7 ′) inverts the logic of the logic signal input to the input terminal IN, and further converts the high level potential to the first power supply. The voltage VDD1 is raised to the second power supply voltage VDD2 and output. On the other hand, when the control signal E1 is at the low level (GND), the transistors P4 and N5 are both turned off, so that the output terminal OUT is in a high impedance state. That is, when the control signal E1 is at the low level (GND), the inverter INV6 ′ (INV7 ′) may set the output terminal OUT to the high impedance state regardless of the logic signal input to the input terminal IN. it can. Therefore, if the three-state inverters INV6 'and INV7' are used, the pass switches SW3 and SW4 shown in FIG. 2 can be omitted.

  Next, a modification of the data read operation from the ferroelectric element will be described in detail with reference to FIG. FIG. 9 is a timing chart for explaining another example of the operation of the data holding device according to the present invention. In order from the top, the power supply voltage (VDD1, VDD2), the clock signal CLK, the data signal D, the control signal E1, The voltage waveforms of the control signal E2, the F reset signal FRST, the applied voltage of the first plate line PL1, the applied voltage of the second plate line PL2, the node voltage V1, the node voltage V2, and the output signal Q are shown.

  At time points R1 to R5, the clock signal CLK is “0 (GND)”, and the inverted clock signal CLKB is “1 (VDD1)”. Accordingly, the first path switch SW1 is turned off and the second path switch is turned on. As described above, by fixing the logic of the clock signal CLK and the inverted clock signal CLKB in advance, it is possible to improve the stability of the data reading operation from the ferroelectric element.

  At the time point R1, the F reset signal FRST is set to “1 (VDD2)” first, the transistors Q1a, Q1b, Q2a, Q2b are turned on, and both ends of the ferroelectric elements CL1a, CL1b, CL2a, CL2b. Both are short-circuited. Accordingly, since no voltage is applied to the ferroelectric elements CL1a, CL1b, CL2a, and CL2b, even if voltage fluctuation occurs when the power is turned on, the ferroelectric elements CL1a, CL1b, CL2a, and CL2b An unintended voltage is not applied, and garbled data can be avoided.

  At the time point R1, the first plate line PL1 and the second plate line PL2 are both “0 (low level: GND)”.

  At the time point R2, the F reset signal FRST is set to “0 (GND)” and the transistors Q1a, Q1b, Q2a, and Q2b are turned off, so that a voltage can be applied to the ferroelectric elements CL1a, CL1b, CL2a, and CL2b. On the other hand, the first plate line PL1 is set to “1 (VDD2)” while the second plate line PL2 is maintained at “0 (GND)”. By applying such a pulse voltage, voltage signals corresponding to the remanent polarization state in the ferroelectric element appear as the node voltage V1 and the node voltage V2.

  More specifically, referring to the example of FIG. 9, WL appears as the logic of the node voltage V1, and WH appears as the logic of the node voltage V2. That is, a voltage difference is generated between the node voltage V1 and the node voltage V2 according to the difference in the remanent polarization state in the ferroelectric element.

  However, since the power supply voltage VDD is not yet applied at the time points R2 to R3, the node voltages V3 to V6 of each part of the loop structure portion LOOP are all “0 (GND)”, and as a result, the output signal Q is “0 (GND)”.

  At the subsequent time point R3, the control signals E1 and E2 are both set to “0 (GND)” (that is, the data write driver is invalidated, and the normal loop is invalidated in the loop structure section LOOP). In the state), the first power supply voltage VDD1 for the loop structure portion LOOP and the second power supply voltage VDD2 for the nonvolatile memory portion NVM are input. At this time, the signal line depicted by the thick line in FIG. 6 is floating.

  At time points R3 to R4, the control signal E2 is set to “0 (GND)”, and the multiplexer MUX1 and the second input terminal (0) of the multiplexer MUX2 are selected. Therefore, the logic of the node voltage V3 is WL, The logic of the node voltage V4 is WH. The logic of the node voltage V5 is WH, and the logic of the node voltage V6 is WL. As described above, at the time points R3 to R4, the node voltages V1 to V6 of each part of the device are still unstable (the logic inversion in the inverter INV3 and the inverter INV4 is not completely performed, and the output logic is surely “0 (GND ) ”/“ 1 (VDD1) ”).

  At the subsequent time point R4, the control signal E2 is set to “1 (VDD1)”, and the multiplexer MUX1 and the first input terminal (1) of the multiplexer MUX2 are selected, so that a normal loop is formed in the loop structure section LOOP. . With such switching of the signal path, the output terminal (logic: WH) of the inverter INV4 and the input terminal (logic: WH) of the inverter INV3 are connected, and the output terminal (logic: WL) of the inverter INV3 and the input of the inverter INV4 The end (logic: WL) is connected. Therefore, no mismatch occurs in the signal logic (WH / WL) of each node, and the inverter INV3 receives the input of the logic WL and outputs the output while the normal loop is formed in the loop structure section LOOP. The inverter INV4 tries to raise the logic to “1 (VDD1)”, and receives the input of the logic WH, and tries to lower its output logic to “0 (GND)”. As a result, the output logic of the inverter INV3 is determined from the unstable logic WL to “0 (GND)”, and the output logic of the inverter INV4 is determined from the unstable logic WH to “1 (VDD1)”.

  As described above, at the time point R4, the signal (potential difference between the node voltage V1 and the node voltage V2) read from the ferroelectric element is generated in the loop structure portion LOOP when the loop structure portion LOOP is changed to the normal loop. As a result, the output data Q is restored as the output signal Q before the power is shut off (“1 (VDD1)” in the example of FIG. 9).

  After that, at the time point R5, the F reset signal FRST is again set to “1 (VDD2)”, the transistors Q1a, Q1b, Q2a, Q2b are turned on, and both ends of the ferroelectric elements CL1a, CL1b, CL2a, CL2b are connected. Since both are short-circuited, no voltage is applied to these ferroelectric elements CL1a, CL1b, CL2a, CL2b. At this time, both the first plate line PL1 and the second plate line PL2 are set to “0 (GND)”. Therefore, the data holding device is returned to the same state as before the time point W1, that is, the normal operation state.

  As described above, unlike the data read operation of FIG. 3, the data read operation of FIG. 9 corresponds to the residual polarization state in the ferroelectric element before the first power supply voltage VDD1 and the second power supply voltage VDD2 are turned on. The drawing operation of the voltage signals (node voltages V1, V2) is started. With this configuration, the number of operation steps after both the first power supply voltage VDD1 and the second power supply voltage VDD2 are input is reduced (in the operation example of FIG. 3, three steps (time points R3, R4, and R5)). On the other hand, in the operation example of FIG. 9, two steps (only time points R4 and R5) are required, and the time required to return to the normal operation can be shortened.

<Ferroelectric element>
Next, the characteristics of the ferroelectric element used in the data holding device of this embodiment will be described in detail.

  FIG. 10 is a diagram for explaining the characteristics of the ferroelectric element. In the upper part of FIG. 10, a state in which the voltage Vs is applied to the ferroelectric element Cs is schematically depicted. Further, the hysteresis characteristic of the ferroelectric element Cs is shown on the lower left side of FIG. 10, and the capacitance characteristic of the ferroelectric element Cs is shown on the lower right side.

  As shown in the figure, the capacitance characteristics of the ferroelectric element Cs change according to the remanent polarization state when the voltage Vs is applied between both ends thereof. More specifically, when a positive voltage Vs is applied across the ferroelectric element Cs to place the ferroelectric element Cs in a non-inverted state (S = 0), the capacitance value is small. Become. Conversely, when a negative voltage Vs is applied across the ferroelectric element Cs to place the ferroelectric element Cs in an inverted state (S = 1), the capacitance value increases. Therefore, when reading data stored in the ferroelectric element Cs, it is necessary to convert the above-described difference in capacitance value into a voltage value.

  Therefore, when reading data from the nonvolatile memory unit NVM, the data holding device according to the present embodiment includes a ferroelectric element in a non-inverted state (S = 0) and a ferroelectric element in an inverted state (S = 1). The capacitive coupling is used.

  FIG. 11 is a diagram for explaining a data read system using capacitive coupling between ferroelectric elements. In the upper part of FIG. 11, the ferroelectric element CL1a (ferroelectric element CL2a) is in an inverted state (S = 1), and the ferroelectric element CL1b (ferroelectric element CL2b) is in a non-inverted state (S = 0). 11 shows the capacitance characteristic when the ferroelectric element CL1a (ferroelectric element CL2a) is in a non-inverted state (S = 0), and the lower part of FIG. The capacitance characteristic when CL1b (ferroelectric element CL2b) is in the inversion state (S = 1) is shown.

  As described above, when data is written to the ferroelectric element, the remanent polarization state is reversed between the ferroelectric elements CL1a and CL1b and between the ferroelectric elements CL2a and CL2b. Therefore, the capacity characteristic is such that the larger one capacitance value is, the smaller the other capacitance value is.

  Therefore, when the two ferroelectric elements CL1a and CL1b whose remanent polarization states are opposite to each other and the ferroelectric elements CL2a and CLK2b are connected in series and a pulse voltage is applied to one end thereof, the connection between the two elements If the node voltages V1 and V2 appearing at the node (voltage values determined by the ratio of the capacitance values and expressed as the read voltage Vout in FIG. 11) are detected, the amplitude value of the read voltage Vout is reduced to around 1 [V]. Thus, it is possible to significantly improve the read margin.

  Further, the data holding device of this embodiment compares the node voltage V1 corresponding to the capacitance ratio of the ferroelectric elements CL1a and CL1b with the node voltage Vb corresponding to the capacitance ratio of the ferroelectric elements CL2a and CL2b. Since the data read from the nonvolatile storage unit NVM is determined to be 0/1, it is not necessary to set the inverter threshold value strictly.

<Second and third modified examples>
As described above, in the data holding device of this embodiment, the data reading method using the capacitive coupling between the ferroelectric elements is adopted, but the configuration of the present invention is not limited to this, and FIG. As shown in (second modification), data is read from the nonvolatile memory unit NVM by using capacitive coupling between the ferroelectric elements CL1a and CL2a and the gate capacitances of the transistors constituting the inverters INV3 and INV4. The configuration (in other words, the configuration in which the ferroelectric elements CL1b and CL2b and the transistors Q1b and C2b are excluded from the configuration in FIG. 1) may be used, or as shown in FIG. 13 (third modification). A configuration in which data is read from the nonvolatile storage unit NVM by using capacitive coupling between the dielectric elements CL1a and CL1b and the other capacitive elements C1 and C2. And it may be.

<Application example to D flip-flop>
FIG. 14 is a circuit diagram showing an application example to a D flip-flop (register) having a set / reset function.

  As shown in this figure, when a D flip-flop is configured, the latch circuit is connected in series in a two-stage set (master and slave), but it is not necessary to make both the master and slave nonvolatile, the slave side It is sufficient to apply the present invention only to the latch circuit.

  The normal operation, the data write operation to the ferroelectric element, and the data read operation from the ferroelectric element are the same as described above except that the master side latch circuit is connected. As for signal paths at the time, as shown in FIG. 15 to FIG.

  However, in the D flip-flop shown in this figure, in order to realize the set / reset function, not logical inverters NAND1 to NAND4 are used as logic gates forming the loop structure, instead of inverters. If the set signal SN input to the NAND operator NAND1 and NAND3 is “0 (GND)”, the output signal Q is forcibly set to “1 (VDD1)”, and the NAND operator NAND2, When the reset signal RN input to the NAND 4 is “0 (GND)”, the output signal Q is forcibly set to “0 (GND)”. Therefore, it is necessary to set the set signal SN and the reset signal RN to “1 (VDD1)” at the time of data write operation or data read operation.

<Fourth Modification>
Next, a fourth modification of the data holding device according to the present invention will be described in detail with reference to FIG. FIG. 18 is a circuit diagram showing a fourth modification of the data holding device according to the present invention.

  The data holding device shown in this figure includes inverters INV1 to INV7, path switches SW1 to SW4, multiplexers MUX1 to MUX4, demultiplexers DeMUX1, DeMUX2, and N-channel field effect transistors Q11a to Q1ma, Q11b to Q1mb, This is a latch circuit having Q21a to Q2ma, Q21b to Q2mb, and ferroelectric elements (ferroelectric capacitors) CL11a to CL1ma, CL11b to CL1mb, CL21a to CL2ma, and CL21b to CL2mb.

  The input end of the inverter INV1 is connected to the application end of the data signal (D). The output terminal of the inverter INV1 is connected to the input terminal of the inverter INV2. The output terminal of the inverter INV2 is connected to the first input terminal (1) of the multiplexer MUX1 via the pass switch SW1. The output terminal of the multiplexer MUX1 is connected to the input terminal of the inverter INV3. The output terminal of the inverter INV3 is connected to the input terminal of the inverter INV5. The output end of the inverter INV5 is connected to the output end of the output signal (Q). The first input terminal (1) of the multiplexer MUX2 is connected to the output terminal of the inverter INV3. The output terminal of the multiplexer MUX2 is connected to the input terminal of the inverter INV4. The output terminal of the inverter INV4 is connected to the first input terminal (1) of the multiplexer MUX1 via the pass switch SW2.

  As described above, the data holding device of the present embodiment uses the two logic gates connected in a loop (inverters INV3 and INV4 in FIG. 18) to provide a loop structure unit LOOP that holds the input data signal D. Have.

  The loop structure portion LOOP is driven by receiving a first power supply voltage VDD1 (for example, 0.6 [V]).

  The input terminal of the inverter INV6 is connected to the first input terminal (1) of the multiplexer MUX1. The output terminal of the inverter INV6 is connected to the input terminal of the demultiplexer DeMUX1 via the pass switch SW3. The first to m-th output terminals of the demultiplexer DeMUX1 are connected to the first to m-th input terminals of the multiplexer MUX4, respectively. The output terminal of the multiplexer MUX4 is connected to the second input terminal (0) of the multiplexer MUX2.

  The input terminal of the inverter INV7 is connected to the first input terminal (1) of the multiplexer MUX2. The output terminal of the inverter INV7 is connected to the input terminal of the demultiplexer DeMUX2 via the path switch SW4. The first to m-th output terminals of the demultiplexer DeMUX2 are connected to the first to m-th input terminals of the multiplexer MUX3, respectively. The output terminal of the multiplexer MUX3 is connected to the second input terminal (0) of the multiplexer MUX1.

  The positive ends of the ferroelectric elements CL11a to CL1ma are connected to plate lines PL11 to PL1m, respectively. The negative ends of the ferroelectric elements CL11a to CL1ma are connected to the first output end to the mth output end of the demultiplexer DeMUX1, respectively. Transistors Q11a to Q1ma are connected between both ends of the ferroelectric elements CL11a to 1ma, respectively. The gates of the transistors Q11a to Q1ma are connected to the application terminals of the F reset signals FRST1 to FRSTm, respectively.

  The positive ends of the ferroelectric elements CL11b to CL1mb are connected to the first output end to the mth output end of the demultiplexer DeMUX1, respectively. The negative ends of the ferroelectric elements CL11b to CL1mb are connected to plate lines PL21 to PL2m, respectively. Transistors Q11b to Q1mb are connected between both ends of the ferroelectric elements CL11b to CL1mb, respectively. The gates of the transistors Q11b to Q1mb are connected to application terminals of the F reset signals FRST1 to FRSTm, respectively.

  The positive ends of the ferroelectric elements CL21a to CL2ma are connected to plate lines PL11 to PL1m, respectively. The negative ends of the ferroelectric elements CL21a to CL2ma are respectively connected to the first output end to the mth output end of the demultiplexer DeMUX2. Transistors Q21a to Q2ma are connected between both ends of the ferroelectric elements CL21a to CL2ma, respectively. The gates of the transistors Q21a to Q2ma are connected to the application terminals of the F reset signals FRST1 to FRSTm, respectively.

  The positive ends of the ferroelectric elements CL21b to CL2mb are connected to the first output end to the mth output end of the demultiplexer DeMUX2, respectively. The negative ends of the ferroelectric elements CL21b to CL2mb are connected to plate lines PL21 to PL2m, respectively. Transistors Q21b to Q2mb are connected between both ends of the ferroelectric elements CL21b to CL2mb, respectively. The gates of the transistors Q21b to Q2mb are connected to the application terminals of the F reset signals FRST1 to FRSTm, respectively.

  As described above, the data holding device of the present embodiment uses the hysteresis characteristics of the ferroelectric elements (CL11a to CL1ma, CL11b to CL1mb, CL21a to CL2ma, CL21b to CL2mb) to hold the data held in the loop structure portion LOOP. It has a non-volatile storage unit NVM that stores D in a non-volatile manner.

  The nonvolatile memory unit NVM is driven by receiving a second power supply voltage VDD2 (for example, 1.2 [V]) higher than the first power supply voltage VDD1.

  Among the above-described components, the path switch SW1 is turned on / off in response to the clock signal CLK, and the path switch SW2 is turned on / off in response to the inverted clock signal CLKB (logic inverted signal of the clock signal CLK). The That is, the path switch SW1 and the path switch SW2 are turned on / off exclusively (complementarily) to each other.

  On the other hand, the path switches SW3 and SW4 are both turned on / off according to the control signal E1. Further, the signal paths of the multiplexers MUX1 and MUX2 are switched according to the control signal E2. Also, the signal paths of the multiplexers MUX3 and MUX4 and the demultiplexers DeMUX1 and DeMUX2 are switched according to the control signals SEL1 to SELm. That is, in the data holding device of this embodiment, the multiplexers MUX1 to MUX4, the demultiplexers DeMUX1 and DeMUX2, the inverters INV6 and INV7, and the path switches SW3 and SW4 electrically connect the loop structure unit LOOP and the nonvolatile storage unit NVM. It functions as a circuit separation unit SEP that separates automatically.

  Of the circuit elements forming the circuit separation unit SEP, the multiplexers MUX1 to MUX4 included in the loop structure unit LOOP are driven by the supply of the first power supply voltage VDD1, and the nonvolatile memory unit NVM The included demultiplexers DeMUX1 and DeMUX2 and the pass switches SW3 and SW4 are driven by the supply of the second power supply voltage VDD2.

  The inverters INV6 and INV7 are driven by the supply of both the first power supply voltage VDD1 and the second power supply voltage VDD2, and are exchanged between the loop structure portion LOOP and the nonvolatile storage portion NVM. It has a function as a level shifter for converting the voltage level of D. Since the circuit configurations of the inverters INV6 and INV7 have already been described, redundant description is omitted. Further, as shown in FIG. 7, the three-state inverters INV6 'and INV7' may be used instead of the inverter INV6 and the pass switch SW3, and the inverter INV7 and the pass switch SW4.

  As described above, the data holding device configured as described above is a further extension of the configuration shown in FIG. 1 in order to store the data D by m bits (m ≧ 2), and corresponds to the control signals SEL1 to SELm. The first storage area to the m-th storage area can be selected. 18, the x-th storage area (1 ≦ x ≦ m) is determined by the ferroelectric elements CL1xa, CL1xb, CL2xa, CL2xb and transistors Q1xa, Q1xb, Q2xa, Q2xb. Is formed. However, the configuration of the present invention is not limited to this, and modifications similar to those shown in FIGS. 12 and 13 can be made.

  Next, the operation of the data holding device configured as described above will be described in detail. In the following description, the voltages appearing at the first output terminal to the m-th output terminal (the first input terminal to the m-th input terminal of the multiplexer MUX4) of the demultiplexer DeMUX1 are V11 to V1m, and the first output of the demultiplexer DeMUX2 is, respectively. Terminal to m-th output terminal (first input terminal to m-th input terminal of multiplexer MUX3), voltages V21 to V2m, voltage appearing at the input terminal of inverter INV4, V3, and voltage appearing at the output terminal of inverter INV4 to V4 The voltage appearing at the input terminal of the inverter INV3 is denoted by V5, and the voltage appearing at the output terminal of the inverter INV3 is denoted by V6.

  FIG. 19 is a timing chart for explaining an operation example of the data holding device according to the present invention (operation of writing data D to the first storage area and reading data D from the m-th storage area). In order, power supply voltage (VDD1, VDD2), clock signal CLK, data signal D, control signal E1, control signal E2, control signal SEL1, F reset signal FRST1, applied voltage of plate line PL11, applied voltage of plate line PL21, node The voltage waveforms of the voltage V11, the node voltage V21, the control signal SELm, the F reset signal FRSTm, the applied voltage of the plate line PL1m, the applied voltage of the plate line PL2m, the node voltage V1m, the node voltage V2m, and the output signal Q are shown.

  Note that the control signal SELi, the F reset signal FRSTy, the applied voltage of the plate line PL1y, and the applied voltage of the plate line PL2y related to the yth storage area (1 <y <m) not selected as the data D write destination or read source. The voltage, the node voltage V1y, and the node voltage V2y are the same as those in the mth storage area not selected as the data D write destination during the data D write operation, and during the data D read operation, the data D Since this is the same as that of the first storage area that is not selected as the read source, the description and description thereof will be omitted as appropriate.

  First, the normal operation of the data holding device will be described.

  Until the time point W1, the F reset signals FRST1 to FRSTm are all “1 (high level: VDD2)”, and the transistors Q11a to Q1ma, Q11b to Q1mb, Q21a to Q2ma, Q21b to Q2mb are all turned on, and ferroelectric Since both ends of the body elements CL11a to CL1ma, CL11b to CL1mb, CL21a to CL2ma, CL21b to CL2mb are short-circuited, these ferroelectric elements CL11a to CL1ma, CL11b to CL1mb, CL21a to CL2ma, CL21b to No voltage is applied to CL2mb. The plate lines PL11 to PL1m and the plate lines PL21 to PL2m are all “0 (low level: GND)”.

  Further, until the time point W1, the control signal E1 is “0 (GND)”, and the path switch SW3 and the path switch SW4 are turned off. Therefore, the data write drivers (inverters INV6 and INV7 in the example of FIG. 18). ) Are all invalid.

  Further, until the time point W1, the control signal E2 is “1 (VDD1)”, and the first input terminal (1) of the multiplexer MUX1 and the multiplexer MUX2 is selected. Is formed.

  Therefore, during the high level period of the clock signal CLK, the pass switch SW1 is turned on and the pass switch SW2 is turned off, so that the data signal D is directly passed as the output signal Q. On the other hand, since the pass switch SW1 is turned off and the pass switch SW2 is turned on during the low level period of the clock signal CLK, the data signal D is latched at the falling edge of the clock signal CLK.

  Next, a data write operation to the first storage area will be described.

  At time points W1 to W3, the clock signal CLK is set to “0 (GND)”, and the inverted clock signal CLKB is set to “1 (VDD1)”. Accordingly, the first path switch SW1 is turned off and the second path switch is turned on. As described above, by fixing the logic of the clock signal CLK and the inverted clock signal CLKB in advance, it is possible to improve the stability of the data write operation with respect to the ferroelectric element.

  At time points W1 to W3, the control signal SEL1 is set to “1 (VDD2)” and the remaining control signals SEL2 to SELm are set to “0 (GND)” in order to select the first storage area as the data D write destination. " As a result, the demultiplexers DeMUX1 and DeMUX2 are in a state in which the signal path connecting the input terminal and the first output terminal is selected, and the multiplexers MUX3 and MUX4 are selected in the signal path connecting the output terminal and the first input terminal. It becomes a state.

  At time points W1 to W3, the F reset signal FRST1 is set to “0 (GND)”, the transistors Q11a, Q11b, Q21a, and Q21b are turned off, and voltage application to the ferroelectric elements CL11a, CL11b, CL21a, and CL21b is performed. Possible state.

  On the other hand, since the F reset signals FRST2 to FRSTm are continuously maintained at “1 (VDD2)”, it is possible to avoid garbled data in the second storage area to the mth storage area.

  Further, at time points W1 to W3, the control signal E1 is set to “1 (VDD2)”, and the path switch SW3 and the path switch SW4 are turned on. Accordingly, the data write drivers (inverters INV6 and INV7 in the example of FIG. 18) are all valid.

  At the time points W1 to W3, the control signal E2 is “1 (VDD1)” and the first input terminals (1) of the multiplexer MUX1 and the multiplexer MUX2 are selected as before, so that the loop structure A normal loop is formed at the part LOOP.

  Further, at the time points W1 to W2, the plate lines PL11 and PL21 are set to “0 (GND)”, and at the time points W2 to W3, the plate lines PL11 and PL21 are set to “1 (VDD2)”. That is, the same pulse voltage is applied to the plate lines PL11 and PL21. By applying such a pulse voltage, the remanent polarization state inside the ferroelectric element is set to either the inversion state or the non-inversion state.

  Specifically, referring to the example of FIG. 19, since the output signal Q is “1 (VDD1)” at the time point W1, the node voltage V11 is “0 (GND)”, and the node voltage V21 is “1 ( VDD1) ". Therefore, at time points W1 to W2, while both the plate lines PL11 and PL21 are set to “0 (GND)”, no voltage is applied between both ends of the ferroelectric elements CL11a and CL11b. A negative voltage is applied between both ends of the body element CL21a, and a positive voltage is applied between both ends of the ferroelectric element CL21b. On the other hand, while the plate lines PL11 and PL21 are both “1 (VDD2)” at the time points W2 to W3, no voltage is applied between both ends of the ferroelectric elements CL21a and CL21b. A positive voltage is applied between both ends of the body element CL11a, and a negative voltage is applied between both ends of the ferroelectric element CL11b.

  Thus, by applying a pulse voltage to the plate lines PL11 and PL21, the remanent polarization state inside the ferroelectric element is set to either the inversion state or the non-inversion state. Note that the remanent polarization state is reversed between the ferroelectric elements CL11a and CL11b and between the ferroelectric elements CL21a and CL21b. Further, the remanent polarization state is also reversed between the ferroelectric elements CL11a and CL21a and between the ferroelectric elements CL11b and CL21b.

  Note that at the time points W1 to W3, the plate lines PL12 to PL1m and PL22 to PL2m are all maintained at “0 (GND)”.

  At the time point W3, the F reset signal FRST1 is again set to “1 (VDD2)”, the transistors Q11a, Q11b, Q21a, and Q21b are turned on, and both ends of the ferroelectric elements CL11a, CL11b, CL21a, and CL21b are all connected. Since they are short-circuited, these ferroelectric elements CL11a, CL11b, CL21a, and CL21b are in a state where no voltage is applied thereto. At this time, both the plate lines PL11 and PL21 are set to “0 (GND)”. The control signal SEL1 is also set to “0 (GND)”.

  At the time point W3, the control signal E1 is again set to “0 (GND)”, and the pass switch SW3 and the pass switch SW4 are turned off, so that the data write driver (inverters INV6 and INV7 in the example of FIG. 18) Is also invalidated. Note that the control signal E2 is not questioned, but is “0 (GND)” in the example of FIG.

  At the time point W3, the F reset signals FRST2 to FRSTm are all maintained at “1 (VDD2)”, and the control signals SEL2 to SELm, the plate lines PL12 to PL1m, and PL22 to PL2m are all “0 (GND). ) ”.

  At time point W4, the supply of the first power supply voltage VDD1 to the loop structure unit LOOP and the supply of the second power supply voltage VDD2 to the nonvolatile memory unit NVM are interrupted. At this time, the F reset signals FRST1 to FRSTm are all maintained at “1 (VDD2)” before the cutoff of the first power supply voltage VDD1 and the second power supply voltage VDD2, and the transistors Q11a to Q1ma, Q11b to Q1mb, and Q21a. -Q2ma, Q21b-Q2mb are turned on, and both ends of the ferroelectric elements CL11a-CL1ma, CL11b-CL1mb, CL21a-CL2ma, CL21b-CL2mb are short-circuited. Accordingly, no voltage is applied to the ferroelectric elements CL11a to CL1ma, CL11b to CL1mb, CL21a to CL2ma, and CL21b to CL2mb. Therefore, even if a voltage fluctuation occurs when the power is shut off, An unintended voltage is not applied to the dielectric elements CL11a to CL1ma, CL11b to CL1mb, CL21a to CL2ma, and CL21b to CL2mb, and data corruption can be avoided.

  Next, a data read operation from the mth storage area will be described.

  At time points R1 to R5, the clock signal CLK is “0 (GND)”, and the inverted clock signal CLKB is “1 (VDD1)”. Accordingly, the first path switch SW1 is turned off and the second path switch is turned on. As described above, by fixing the logic of the clock signal CLK and the inverted clock signal CLKB in advance, it is possible to improve the stability of the data reading operation from the ferroelectric element.

  At the time point R1, all the F reset signals FRST1 to FRSTm are set to “1 (VDD2)” first, and the transistors Q11a to Q1ma, Q11b to Q1mb, Q21a to Q2ma, Q21b to Q2mb are turned on, and strong. Dielectric elements CL11a to CL1ma, CL11b to CL1mb, CL21a to CL2ma, and CL21b to CL2mb are both short-circuited. Accordingly, since no voltage is applied to the ferroelectric elements CL11a to CL1ma, CL11b to CL1mb, CL21a to CL2ma, and CL21b to CL2mb, the ferroelectric elements can be used even when voltage fluctuation occurs when the power is turned on. Unintentional voltages are not applied to CL11a to CL1ma, CL11b to CL1mb, CL21a to CL2ma, and CL21b to CL2mb, and garbled data can be avoided.

  At time R1, the plate lines PL11 to PL1m and the plate lines PL21 to PL2m are all “0 (low level: GND)”.

  At time R2, the control signals E1 and E2 are both “0 (GND)” (that is, the data write driver is disabled and the normal loop is disabled in the loop structure section LOOP). ), The first power supply voltage VDD1 for the loop structure portion LOOP and the second power supply voltage VDD2 for the nonvolatile memory portion NVM are input.

  At the subsequent time point R3, the control signal SELm is set to “1 (VDD2)” and the remaining control signals SEL1 to SEL (m−1) are set to “0 ( GND) ”. As a result, the demultiplexers DeMUX1 and DeMUX2 are in a state in which the signal path connecting the input terminal and the mth output terminal is selected, and the multiplexers MUX3 and MUX4 are selected in the signal path connecting the output terminal and the mth input terminal. It becomes a state.

  At the time point R3, the F reset signal FRSTm is set to “0 (GND)”, the transistors Q1ma, Q1mb, Q2ma, Q2mb are turned off, and voltage can be applied to the ferroelectric elements CL1ma, CL1mb, CL2ma, CL2mb. On the other hand, the plate line PL1m is set to “1 (VDD2)” while the plate line PL2m is maintained at “0 (GND)”. By applying such a pulse voltage, voltage signals corresponding to the remanent polarization state in the ferroelectric element appear as the node voltage V1m and the node voltage V2m.

  A specific description will be given according to the example of FIG. 19 (when data D of logic “1” is stored in the m-th storage area). WL appears as the logic of the node voltage V1m, and the logic of the node voltage V2m. Appears as WH. That is, a voltage difference is generated between the node voltage V1m and the node voltage V2m according to the difference in the remanent polarization state in the ferroelectric element.

  At this time, at time points R3 to R4, the control signal E2 is set to “0 (GND)”, and the multiplexer MUX1 and the second input terminal (0) of the multiplexer MUX2 are selected. Therefore, the logic of the node voltage V3 becomes WL, The logic of the node voltage V4 is WH. The logic of the node voltage V5 is WH, and the logic of the node voltage V6 is WL. As described above, at the time points R3 to R4, the node voltages V1m, V2m, and V3 to V6 of each part of the device are still unstable (the logic inversion in the inverters INV3 and INV4 is not completely performed, and the output logic is surely “0 (GND)” / “1 (VDD1)”.

  At time R3, the F reset signals FRST1 to FRST (m−1) are all maintained at “1 (VDD2)”, and the control signals SEL1 to SEL (m−1) and the plate lines PL11 to PL1 (m -1) and PL21 to PL2 (m-1) are all maintained at "0 (GND)".

  At the subsequent time point R4, the control signal E2 is set to “1 (VDD1)”, and the multiplexer MUX1 and the first input terminal (1) of the multiplexer MUX2 are selected, so that a normal loop is formed in the loop structure section LOOP. . With such switching of the signal path, the output terminal (logic: WH) of the inverter INV4 and the input terminal (logic: WH) of the inverter INV3 are connected, and the output terminal (logic: WL) of the inverter INV3 and the input of the inverter INV4 The end (logic: WL) is connected. Therefore, no mismatch occurs in the signal logic (WH / WL) of each node, and the inverter INV3 receives the input of the logic WL and outputs the output while the normal loop is formed in the loop structure section LOOP. The inverter INV4 tries to raise the logic to “1 (VDD1)”, and receives the input of the logic WH, and tries to lower its output logic to “0 (GND)”. As a result, the output logic of the inverter INV3 is determined from the unstable logic WL to “0 (GND)”, and the output logic of the inverter INV4 is determined from the unstable logic WH to “1 (VDD1)”.

  As described above, at the time point R4, the signal read from the ferroelectric element (potential difference between the node voltage V1m and the node voltage V2m) is generated in the loop structure portion LOOP when the loop structure portion LOOP is changed to the normal loop. As a result, the data stored in the third storage area (“1 (VDD1)” in the example of FIG. 19) is restored as the output signal Q.

  Thereafter, at the time point R5, the F reset signal FRSTm is again set to “1 (VDD2)”, the transistors Q1ma, Q1mb, Q2ma, Q2mb are turned on, and both ends of the ferroelectric elements CL1ma, CL1mb, CL2ma, CL2mb are connected. Since both are short-circuited, no voltage is applied to these ferroelectric elements CL1ma, CL1mb, CL2ma, CL2mb. At this time, both the plate line PL1m and the plate line PL2m are set to “0 (GND)”. Therefore, the data holding device is returned to the same state as before the time point W1, that is, the normal operation state.

  As described above, in the data holding device of the fourth modified example, the nonvolatile storage unit NVM that stores the data D held in the loop structure unit LOOP in a nonvolatile manner using the hysteresis characteristics of the ferroelectric element is: It is configured to have m storage areas using ferroelectric elements, and select and use a storage area from which data D is written or read in accordance with predetermined control signals SEL1 to SELm. Yes. With such a configuration, it is possible to realize a data holding device capable of arbitrarily switching and using a plurality of data D.

  During normal operation of the data holding device, since the ferroelectric element is separated from the signal line, the increase in the ferroelectric element causes the performance of the data holding device to deteriorate (speed deterioration, increase in power consumption, etc.). There is nothing.

  Next, a modified example of the operation of reading data from the mth storage area will be described in detail with reference to FIG. FIG. 20 is a timing chart for explaining another example of the operation of the data holding device according to the present invention. In order from the top, the power supply voltage (VDD1, VDD2), the clock signal CLK, the data signal D, the control signal E1, Control signal E2, control signal SEL1, F reset signal FRST1, applied voltage of plate line PL11, applied voltage of plate line PL21, node voltage V11, node voltage V21, control signal SELm, F reset signal FRSTm, applied voltage of plate line PL1m 4 shows voltage waveforms of the applied voltage, the node voltage V1m, the node voltage V2m, and the output signal Q of the plate line PL2m.

  Note that the control signal SELi, the F reset signal FRSTy, the applied voltage of the plate line PL1y, and the applied voltage of the plate line PL2y related to the yth storage area (1 <y <m) not selected as the data D write destination or read source. The voltage, the node voltage V1y, and the node voltage V2y are the same as those in the mth storage area not selected as the data D write destination during the data D write operation, and during the data D read operation, the data D Since this is the same as that of the first storage area that is not selected as the read source, the description and description thereof will be omitted as appropriate.

  At time points R1 to R5, the clock signal CLK is “0 (GND)”, and the inverted clock signal CLKB is “1 (VDD1)”. Accordingly, the first path switch SW1 is turned off and the second path switch is turned on. As described above, by fixing the logic of the clock signal CLK and the inverted clock signal CLKB in advance, it is possible to improve the stability of the data reading operation from the ferroelectric element.

  At the time point R1, the F reset signals FRST1 to FRSTm are set to “1 (VDD2)” first, and the transistors Q11a to Q1ma, Q11b to Q1mb, Q21a to Q2ma, Q21b to Q2mb are turned on, and the ferroelectric element All ends of CL11a to CL1ma, CL11b to CL1mb, CL21a to CL2ma, and CL21b to CL2mb are short-circuited. Therefore, since no voltage is applied to the ferroelectric elements CL11a to CL1ma, CL11b to CL1mb, CL21a to CL2ma, and CL21b to CL2mb, even if a voltage fluctuation occurs when the power is turned on, An unintended voltage is not applied to the dielectric elements CL11a to CL1ma, CL11b to CL1mb, CL21a to CL2ma, and CL21b to CL2mb, and data corruption can be avoided.

  At time R1, the plate lines PL11 to PL1m and the plate lines PL21 to PL2m are all “0 (low level: GND)”.

  At the time point R2, the F reset signal FRSTm is set to “0 (GND)”, the transistors Q1ma, Q1mb, Q2ma, Q2mb are turned off, and a voltage can be applied to the ferroelectric elements CL1ma, CL1mb, CL2ma, CL2mb. On the other hand, the plate line PL1m is set to “1 (VDD2)” while the plate line PL2m is maintained at “0 (GND)”. By applying such a pulse voltage, voltage signals corresponding to the remanent polarization state in the ferroelectric element appear as the node voltage V1m and the node voltage V2m.

  Specifically, in accordance with the example of FIG. 20 (when data D of logic “1” is stored in the third storage area), WL appears as the logic of the node voltage V1m, and the logic of the node voltage V2m. Appears as WH. That is, a voltage difference is generated between the node voltage V1m and the node voltage V2m according to the difference in the remanent polarization state in the ferroelectric element.

  However, since the first power supply voltage VDD1 is not yet applied at the time points R2 to R3, the node voltages V3 to V6 of each part of the loop structure portion LOOP are all “0 (GND)”. The output signal Q is “0” (GND).

  At the subsequent time point R3, the control signal SELm is set to “1 (VDD2)” and the remaining control signals SEL1 to SEL (m−1) are set to “0 ( GND) ”. As a result, the demultiplexers DeMUX1 and DeMUX2 are in a state in which the signal path connecting the input terminal and the mth output terminal is selected, and the multiplexers MUX3 and MUX4 are selected in the signal path connecting the output terminal and the mth input terminal. It becomes a state.

  At the time point R3, the control signals E1 and E2 are both “0 (GND)” (that is, the data write driver is disabled, and the normal loop is disabled in the loop structure section LOOP). In the state), the first power supply voltage VDD1 for the loop structure portion LOOP and the second power supply voltage VDD2 for the nonvolatile memory portion NVM are input.

  At time points R3 to R4, the control signal E2 is set to “0 (GND)”, and the multiplexer MUX1 and the second input terminal (0) of the multiplexer MUX2 are selected. Therefore, the logic of the node voltage V3 is WL, The logic of the node voltage V4 is WH. The logic of the node voltage V5 is WH, and the logic of the node voltage V6 is WL. As described above, at the time points R3 to R4, the node voltages V1 to V6 of each part of the device are still unstable (the logic inversion in the inverter INV3 and the inverter INV4 is not completely performed, and the output logic is surely “0 (GND ) ”/“ 1 (VDD1) ”).

  At the subsequent time point R4, the control signal E2 is set to “1 (VDD1)”, and the multiplexer MUX1 and the first input terminal (1) of the multiplexer MUX2 are selected, so that a normal loop is formed in the loop structure section LOOP. . With such switching of the signal path, the output terminal (logic: WH) of the inverter INV4 and the input terminal (logic: WH) of the inverter INV3 are connected, and the output terminal (logic: WL) of the inverter INV3 and the input of the inverter INV4 The end (logic: WL) is connected. Therefore, no mismatch occurs in the signal logic (WH / WL) of each node, and the inverter INV3 receives the input of the logic WL and outputs the output while the normal loop is formed in the loop structure section LOOP. The inverter INV4 tries to raise the logic to “1 (VDD1)”, and receives the input of the logic WH, and tries to lower its output logic to “0 (GND)”. As a result, the output logic of the inverter INV3 is determined from the unstable logic WL to “0 (GND)”, and the output logic of the inverter INV4 is determined from the unstable logic WH to “1 (VDD1)”.

  As described above, at the time point R4, the signal read from the ferroelectric element (potential difference between the node voltage V1m and the node voltage V2m) is generated in the loop structure portion LOOP when the loop structure portion LOOP is changed to the normal loop. As a result, the data stored in the third storage area (“1 (VDD1)” in the example of FIG. 20) is restored as the output signal Q.

  Thereafter, at the time point R5, the F reset signal FRSTm is again set to “1 (VDD2)”, the transistors Q1ma, Q1mb, Q2ma, Q2mb are turned on, and both ends of the ferroelectric elements CL1ma, CL1mb, CL2ma, CL2mb are connected. Since both are short-circuited, no voltage is applied to these ferroelectric elements CL1ma, CL1mb, CL2ma, CL2mb. At this time, both the plate line PL1m and the plate line PL2m are set to “0 (GND)”. Therefore, the data holding device is returned to the normal operation state as before the time point W1.

  As described above, unlike the data read operation of FIG. 19, the data read operation of FIG. 20 corresponds to the remanent polarization state in the ferroelectric element before the first power supply voltage VDD1 and the second power supply voltage VDD2 are turned on. The drawing operation of the voltage signals (node voltages V1m and V2m) is started. With such a configuration, the number of operation steps after the first power supply voltage VDD1 and the second power supply voltage VDD2 are input is reduced (in the operation example of FIG. 19, three steps (time points R3, R4, and R5) are reduced. In contrast, in the operation example of FIG. 20, it is possible to shorten the time required to return to the normal operation by two steps (only time points R4 and R5).

<CPU processing switching operation>
Next, a process switching operation when the data holding device of the fourth modification is applied to a CPU will be described with reference to FIG. FIG. 21 is a schematic diagram illustrating an example of a process switching operation by data exchange. By arbitrarily switching between the first storage area and the m-th storage area of the data holding device, process A (for example, moving image compression process) and A mode that processing B (for example, spreadsheet processing) is alternately switched is schematically shown. The left side of FIG. 21 shows a state where processing A and processing B are alternately switched with the vertical axis as a time axis, and the right side of FIG. 21 shows the data holding device used in the CPU. The operating state is shown schematically.

  When moving from the process A to the process B, the data holding device writes the data DA related to the process A to the first storage area (CL11a to CL21b) and reads the data DB related to the process B from the mth storage area (CL1ma to CL2mb). Thus, the data stored in the data holding device is replaced. On the other hand, when moving from process B to process A, contrary to the above, the data holding device writes the data DB related to process B in the m-th storage area (CL1ma to CL2mb), and the data DA related to process A is stored in the first memory. By reading from the area (CL11a to CL21b), the data stored in the data holding device is replaced. By such data replacement processing, processing executed by the CPU can be instantaneously switched.

  Note that when CPU processing is switched by exchanging data, the power-off period shown in FIGS. 19 and 20 is not necessarily required.

<Cell pattern>
Next, the layout of the cell pattern of the ferroelectric element will be described in detail with reference to FIGS. 22 to 25 are schematic diagrams showing first to fourth layout examples of the cell pattern of the ferroelectric element, respectively. In addition, the code | symbol ad in a figure has each shown the ferroelectric element, and the code | symbols x and y each have shown the distance between elements.

  When a plurality of ferroelectric elements are formed on a semiconductor substrate, in the layout stage, all the ferroelectric elements are designed to have the same shape (for example, a shape that becomes a square or a rectangle when viewed from above). However, an actual element shape formed on a semiconductor substrate through a masking process or an etching process often does not have a designed shape because of process characteristics.

  For example, in FIG. 22, since the ferroelectric elements a and d are not adjacent to any of the four sides, the corner portion of the element is easily etched, and the actual element shape formed on the semiconductor substrate Is a relatively large rounded shape at each of the four corners. On the other hand, since the ferroelectric elements b and c are close to each other in such a manner that one side faces each other, the corner portion of the element including the one side is difficult to be etched, and the actual element formed on the semiconductor substrate The shape is a shape in which two opposite corners of each of the four corners are rounded relatively small and the other two corners are rounded relatively large. The examples of FIGS. 23 to 25 are the same as described above.

  As described above, the actual element shape formed on the semiconductor substrate differs in the degree of etching at the four corners depending on the density of the element, but the pair of the ferroelectric element CL1a and the ferroelectric element CL1b, and The pairs of the ferroelectric element CL2a and the ferroelectric element CL2b are preferably arranged so that the actual shapes formed on the semiconductor substrate are equal to each other.

  In the example of FIG. 22, the ferroelectric elements a and d may be a first pair, and the ferroelectric elements b and c may be a second pair. In the example of FIG. 23, the ferroelectric elements a and b may be the first pair, and the ferroelectric elements c and d may be the second pair (see (a) in the figure), or The ferroelectric elements a and c may be a first pair, and the ferroelectric elements b and d may be a second pair (see (b) in the figure). In the example of FIG. 24, the ferroelectric elements a and c may be a first pair, and the ferroelectric elements b and d may be a second pair (see (a) in the figure). The body elements a and b may be the first pair and the ferroelectric elements c and d may be the second pair (see (b) in the figure), or the ferroelectric elements a and d are the first pair. The ferroelectric elements b and c may be a second pair (see (c) in the figure). In the example of FIG. 25, the ferroelectric elements a and d may be a first pair, and the ferroelectric elements b and c may be a second pair.

  By laying out such a cell pattern, it becomes possible to align the shape (area) of the paired ferroelectric elements and improve their pairing properties, and thus to improve the data retention characteristics of the data retention device. It becomes possible to improve.

  Further, as shown in FIG. 18, the case where a plurality of storage areas are provided is the same as described above, and a pair of ferroelectric elements CL11a to CL1ma and ferroelectric elements CL11b to CL1mb, and ferroelectric elements CL21a to CL21a. Regarding the pair of CL1ma and the ferroelectric elements CL21b to CL2mb, it is important that their shapes (areas) are aligned.

<Fifth Modification>
Next, a fifth modification of the data holding device according to the present invention will be described in detail with reference to FIG. FIG. 26 is a circuit diagram showing a fifth modification of the data holding device according to the present invention. In the above description, the configuration in which different power supply voltages are supplied to the loop structure unit LOOP and the nonvolatile memory unit NVM has been exemplified. However, the configuration of the present invention is not limited to this, and the loop The same power supply voltage may be supplied to both the structure part LOOP and the nonvolatile memory part NVM. Therefore, in the fifth modified example described below, the other configurations described above can be used without referring to the coincidence / mismatch of the power supply voltages supplied to the loop structure unit LOOP and the nonvolatile memory unit NVM. Will focus on the differences.

  As shown in FIG. 26, the data holding device according to the present modification includes a loop structure unit LOOP, a nonvolatile storage unit NVM, and a circuit separation unit SEP, and further includes a set / reset control unit SRC and clock pulse control. It has a section CPC and a test circuit section TEST, and functions as a D flip-flop (register) having a set / reset function.

  The loop structure unit LOOP includes NAND operation units NAND1 to NAND4, path switches SW1, SW2, SW5, and SW6, inverters INV5 and INV5 ', and three-state inverters INV8 and INV8'.

  The input end of the inverter INV8 is connected to the input end of the data D. The input end of the inverter INV8 'is connected to the input end of the scan data SD. The output terminals of the inverters INV8 and INV8 'are both connected to the first input terminal of the NAND operator NAND1 via the pass switch SW6. The second input terminal of the NAND operator NAND1 is connected to the input terminal of the internal set signal SNL. The output terminal of the NAND operator NAND1 is connected to the first input terminal of the NAND operator NAND2, and is also connected to the first input terminal of the NAND operator NAND4 via the path switch SW1. ing. The second input terminal of the NAND operator NAND2 is connected to the input terminal of the internal reset signal RNL. The output terminal of the NAND operator NAND2 is connected to the first input terminal of the NAND operator NAND1 via the path switch SW5.

  The second input terminal of the NAND operator NAND4 is connected to the input terminal of the internal reset signal RNL. The output terminal of the NAND operator NAND4 is connected to the output terminal of the output data Q through the inverter INV5, and is also connected to the output terminal of the scan output data SO through the inverter INV5 '. The output terminal of the NAND operator NAND4 is also connected to the first input terminal of the NAND operator NAND3. The second input terminal of the NAND operator NAND3 is connected to the input terminal of the internal set signal SNL. The output terminal of the NAND operator NAND3 is connected to the first input terminal of the NAND operator NAND4 via the path switch SW2.

  The control terminal of the inverter INV8 is connected to the input terminal of the inverted scan control signal SCB (logically inverted signal of the scan control signal SCB). The control end of the inverter INV8 'is connected to the input end of the scan control signal SC. Therefore, the output terminals of the inverter INV8 and the inverter INV8 'are in a high impedance state exclusively (complementarily) to each other.

  The control terminal of the path switch SW1 and the control terminal of the path switch SW5 are both connected to the input terminal of the internal clock signal CPL. The control terminal of the path switch SW2 and the control terminal of the path switch SW6 are both connected to the input terminal of the inverted internal clock signal CPLB (the logically inverted signal of the internal clock signal CPL). Therefore, the path switches SW1 and SW5 and the path switches SW2 and SW6 are turned on / off exclusively (complementarily). More specifically, when the path switches SW1 and SW5 are turned on, the path switches SW2 and SW6 are turned off. Conversely, when the path switches SW1 and SW5 are turned off, the path switches SW2 and SW6 are turned off. SW6 is turned on.

  As described above, also in the data holding device of the present modification example, the logic gates connected in a loop (using the negative logical product operators NAND1 and NAND2 on the master side and the negative logical product operators NAND3 and NAND4 on the slave side) are used. The basic structure of the loop structure section LOOP that holds the input data signal D is the same as that of the above-described embodiment. However, the loop structure unit LOOP forming the data holding device of the present modification is such that the multiplexers MUX1 and MUX2 are removed, and a clock stop process at the time of data saving / restoring is not required, and a serial using a scan path is used. It is characterized by having a data input / output function.

  The nonvolatile memory unit NVM includes ferroelectric elements CL1a, CL1b, CL2a, and CL2b, and N-channel MOS field effect transistors Q1a, Q1b, Q2a, and Q2b.

  The positive electrode end of the ferroelectric element CL1a is connected to the first plate line PL1D of the D system. The negative end of the ferroelectric element CL1a is connected to the first input end of the NAND operator NAND4 that forms the loop structure unit LOOP via the circuit separation unit SEP (inverter INV9). A transistor Q1a is connected between both ends of the ferroelectric element CL1a. The gate of the transistor Q1a is connected to the application end of the F reset signal FRSTD of the D system.

  The positive terminal of the ferroelectric element CL1b is connected to the first input terminal of the NAND operator NAND4 that forms the loop structure section LOOP via the circuit separation section SEP (inverter INV9). The negative electrode end of the ferroelectric element CL1b is connected to the second plate line PL2D of the D system. A transistor Q1b is connected between both ends of the ferroelectric element CL1b. The gate of the transistor Q1b is connected to the application terminal for the F reset signal FRSTD of the D system.

  The positive end of the ferroelectric element CL2a is connected to the first plate line PL1U of the U system. The negative end of the ferroelectric element CL2a is connected to the first input end of the NAND operator NAND3 that forms the loop structure unit LOOP via the circuit separation unit SEP (inverter INV10). A transistor Q2a is connected between both ends of the ferroelectric element CL2a. The gate of the transistor Q2a is connected to the application terminal of the U-system F reset signal FRSTU.

  The positive electrode terminal of the ferroelectric element CL2b is connected to the first input terminal of the NAND operator NAND3 that forms the loop structure unit LOOP via the circuit separation unit SEP (inverter INV10). The negative electrode end of the ferroelectric element CL2b is connected to the U-system second plate line PL2U. A transistor Q2b is connected between both ends of the ferroelectric element CL2b. The gate of the transistor Q2b is connected to the application terminal of the U-system F reset signal FRSTU.

  As described above, also in the data holding device of this modification, the data D held in the loop structure portion LOOP is stored in a nonvolatile manner using the hysteresis characteristics of the ferroelectric elements (CL1a, CL1b, CL2a, CL2b). The basic configuration of the non-volatile storage unit NVM is the same as that of the above-described embodiment. However, the nonvolatile memory unit NVM forming the data holding device of the present modification example uses the first plate line in order to evaluate the characteristics of the ferroelectric elements (CL1a, CL1b, CL2a, CL2b) using the test circuit unit TEST. The second plate line and the F reset signal line each have two systems (U system / D system).

  The circuit separation unit SEP includes three-state inverters INV9 and INV10 as means for electrically separating the loop structure unit LOOP and the nonvolatile memory unit NVM. Each of the inverters INV9 and INV10 is set to a high impedance state in accordance with the control signal E1.

  The set / reset control unit SRC includes a sense amplifier (differential amplifier) SA and AND operators AND1 and AND2. The first input terminal of the sense amplifier SA is connected to the D system output terminal (a connection node between the negative electrode terminal of the ferroelectric element CL1a and the positive electrode terminal of the ferroelectric element CL1b) of the nonvolatile memory unit NVM. A second input terminal of the sense amplifier SA is connected to a U-system output terminal (a connection node between the negative electrode terminal of the ferroelectric element CL2a and the positive electrode terminal of the ferroelectric element CL2b) of the nonvolatile memory unit NVM. The first output terminal (inversion format) of the sense amplifier SA is connected to the first input terminal of the AND operator AND1. The second input terminal of the AND operator AND1 is connected to the input terminal of the external set signal SN. The output terminal of the AND operator AND1 functions as the output terminal of the internal set signal SNL. The second output terminal of the sense amplifier SA is connected to the first input terminal of the AND operator AND2. The second input terminal of the AND operator AND2 is connected to the input terminal of the external reset signal RN. The output terminal of the AND operator AND2 functions as the output terminal of the internal reset signal RNL. The control terminal of the sense amplifier SA is connected to the input terminal of the sense amplifier enable signal SAE. The specific operation of the set / reset control unit SRC configured as described above will be described in detail later.

  The clock pulse control unit CPC includes a NAND operator NAND5. The first input terminal of the NAND operator NAND5 is connected to the input terminal of the external clock signal CP. The second input terminal (inverted input format) of the NAND operator NAND5 is connected to the input terminal of the data holding control signal HS. The output terminal of the NAND operator NAND5 functions as the output terminal of the internal clock signal CPL. Therefore, when the data holding control signal HS is at a high level (clock invalid state), the internal clock signal CPL is always a high level signal regardless of the external clock signal CP, and the data holding control signal HS is at a low level ( In the clock valid state), this is a logical inversion signal of the external clock signal CP.

  The test circuit unit TEST includes three-state inverters INV11 to INV14 and pass switches SW7 to SW10.

  The input terminals of the inverters INV11 and INV12 are both connected to the first digital plate line PL1_D. The output terminal of the inverter INV11 is connected to the first plate line PL1U of the U system. The output terminal of the inverter INV12 is connected to the first plate line PL1D of the D system. The control terminal of the inverter INV11 is connected to an input terminal of a U-system inverted analog enable signal TESTUB (logically inverted signal of the analog enable signal TESTTU). A control terminal of the inverter INV12 is connected to an input terminal of an inverted analog enable signal TESTDB (logically inverted signal of the analog enable signal TESTD) of the D system.

  The input terminal of the path switch SW7 is connected to the U-system first analog plate line PL1U_A. The output terminal of the path switch SW7 is connected to the first plate line PL1U of the U system. The control end of the path switch SW7 is connected to the input end of the U-system analog enable signal TESTU. An input terminal of the path switch SW8 is connected to the first analog plate line PL1D_A of the D system. The output terminal of the path switch SW8 is connected to the first plate line PL1D of the D system. The control end of the path switch SW8 is connected to the input end of the D system analog enable signal TESTD.

  The input terminals of the inverters INV13 and INV14 are both connected to the second digital plate line PL2_D. The output terminal of the inverter INV13 is connected to the second plate line PL2U of the U system. The output terminal of the inverter INV14 is connected to the second plate line PL2D of the D system. A control end of the inverter INV13 is connected to an input end of a U-system inverted analog enable signal TESTUB (logically inverted signal of the analog enable signal TESTTU). The control terminal of the inverter INV14 is connected to the input terminal of the D system inverted analog enable signal TESTDB (logically inverted signal of the analog enable signal TESTD).

  An input terminal of the path switch SW9 is connected to a U-system second analog plate line PL2U_A. The output terminal of the path switch SW9 is connected to the U-system second plate line PL2U. The control end of the path switch SW9 is connected to the input end of the U-system analog enable signal TESTU. The input terminal of the path switch SW10 is connected to the D system second analog plate line PL2D_A. The output terminal of the path switch SW10 is connected to the second plate line PL2D of the D system. The control end of the path switch SW10 is connected to the input end of the D system analog enable signal TESTD.

  In the test circuit unit TEST having the above-described configuration, the U-system analog enable signal TESTU and the D-system analog enable signal TESTD are mutually contradictory. More specifically, when the U-system analog enable signal TESTTU is at a high level (enable logic), the D-system analog enable signal TESTD is at a low level (disable logic). In contrast, when the U-system analog enable signal TESTTU is at a low level (disable logic), the D-system analog enable signal TESTD is at a high level (enable logic). The specific operation of the test circuit unit TEST having the above configuration will be described in detail later.

  FIG. 27 is a block diagram showing signal pins used in the data holding device of the fifth modified example, and FIG. 28 is a function explanatory table of the signal pins. As shown in both figures, in the data holding device of this modification, as a signal pin for logic control, a clock terminal (CP), a data input terminal (D), a preset terminal (SN), a clear terminal (RN), A scan data input terminal (SD) and a scan control terminal (SC) are provided. The signal pins for controlling the ferroelectric element include a ferroelectric element write enable terminal (E1), a data hold terminal (HS), a sense amplifier enable terminal (SAE), a U-system ferroelectric element reset terminal (FRSTU). ), A D system ferroelectric element reset terminal (FRSTD), a first plate line digital input terminal (PL1_D), and a second plate line digital input terminal (PL2_D). In addition, as signal pins for ferroelectric element testing, U system PL1 / 2 analog enable terminal (TESTTU), D system PL1 / 2 analog enable terminal (TESTD), PL1U analog input terminal (PL1U_A), PL2U analog An input terminal (PL2U_A), a PL1D analog input terminal (PL1D_A), a PL2D analog input terminal (PL2D_A), a scan output terminal (SO), and an output terminal (Q) are provided.

  FIG. 29 is a circuit diagram showing a configuration example of the sense amplifier SA. The sense amplifier SA of this configuration example includes P-channel field effect transistors P1 to P4 and N-channel field effect transistors N1 to N5.

  The source and back gate of the transistor P1 are connected to the application terminal of the power supply voltage VDD. The drain of the transistor P1 is connected to the second output terminal (the output terminal of the second output signal SDC_OUT) of the sense amplifier SA. The gate of the transistor P1 is connected to the input terminal of the sense amplifier enable signal SAE.

  The source and back gate of the transistor P2 are connected to the application terminal of the power supply voltage VDD. The drain of the transistor P2 is connected to the second output terminal (the output terminal of the second output signal SDC_OUT) of the sense amplifier SA. The gate of the transistor P2 is connected to the first output terminal (the output terminal of the first output signal SDnC_OUT) of the sense amplifier SA.

  The source and back gate of the transistor P3 are connected to the application terminal of the power supply voltage VDD. The drain of the transistor P3 is connected to the first output terminal (the output terminal of the first output signal SDnC_OUT) of the sense amplifier SA. The gate of the transistor P3 is connected to the second output terminal (the output terminal of the second output signal SDC_OUT) of the sense amplifier SA.

  The source and back gate of the transistor P4 are connected to the application terminal of the power supply voltage VDD. The drain of the transistor P4 is connected to the first output terminal (the output terminal of the first output signal SDnC_OUT) of the sense amplifier SA. The gate of the transistor P4 is connected to the input terminal of the sense amplifier enable signal SAE.

  The drain of the transistor N1 is connected to the second output terminal (the output terminal of the second output signal SDC_OUT) of the sense amplifier SA. The source of the transistor N1 is connected to the drain of the transistor N3. The gate of the transistor N1 is connected to the first output terminal (the output terminal of the first output signal SDnC_OUT) of the sense amplifier SA. The back gate of the transistor N1 is connected to the application terminal of the ground voltage VSS.

  The drain of the transistor N2 is connected to the first output terminal (the output terminal of the first output signal SDnC_OUT) of the sense amplifier SA. The source of the transistor N2 is connected to the drain of the transistor N4. The gate of the transistor N2 is connected to the second output terminal (the output terminal of the second output signal SDC_OUT) of the sense amplifier SA. The back gate of the transistor N2 is connected to the application terminal of the ground voltage VSS.

  The drain of the transistor N3 is connected to the source of the transistor N1. The source of the transistor N3 is connected to the drain of the transistor N5. The gate of the transistor N3 is connected to the first input terminal (the input terminal of the first input signal SDnC) of the source amplifier SA. The back gate of the transistor N3 is connected to the application terminal of the ground voltage VSS.

  The drain of the transistor N4 is connected to the source of the transistor N2. The source of the transistor N4 is connected to the drain of the transistor N5. The gate of the transistor N4 is connected to the second input terminal (the input terminal for the second input signal SDC) of the source amplifier SA. The back gate of the transistor N4 is connected to the application terminal of the ground voltage VSS.

  The drain of the transistor N5 is connected to the sources of the transistors N3 and N4. The source and back gate of the transistor N5 are connected to the application terminal of the ground voltage VSS. The gate of the transistor N5 is connected to the input terminal of the sense amplifier enable signal SAE.

  In the source amplifier SA configured as described above, when the sense amplifier enable signal SAE is at a high level (enable logic), the transistors P1 and P2 are turned off, the transistor N5 is turned on, and the operation of the source amplifier SA is permitted. It will be in the state. At this time, if the first input signal SDnC is higher than the second input signal SDC, the first output signal SDnC_OUT is at a high level (power supply voltage VDD), and the second output signal SDC_OUT is at a low level (ground voltage VSS). It becomes. Conversely, if the first input signal SDnC is lower in voltage than the second input signal SDC, the first output signal SDnC_OUT is at a low level (ground voltage VSS), and the second output signal SDC_OUT is at a high level (power supply voltage VDD). It becomes. On the other hand, when the sense amplifier enable signal SAE is at a low level (disable logic), the transistors P1 and P2 are turned on, the transistor N5 is turned off, and the operation of the source amplifier SA is prohibited. At this time, the first output signal SDnC_OUT and the second output signal SDC_OUT are always fixed at a high level (power supply voltage VDD) regardless of the first input signal SDnC and the second input signal SDC.

  Next, the operation of the data holding device having the above configuration will be described with reference to the drawings.

  First, the normal operation of the data holding device will be described. FIG. 30 is a circuit diagram showing the operating state of each part of the apparatus during normal operation.

  During the normal operation of the data holding device, a low level (0) data holding control signal HS is input to the clock pulse control unit CPC so as to validate the external clock signal CP. As a result, the external clock signal CP (more precisely, its logic inversion signal) is supplied from the clock pulse control unit CPC to the loop structure unit LOOP as the internal clock signal CPL. Based on the clock signal CPL (and hence the external clock signal CP), the data signal D is latched.

  In the normal operation of the data holding device, the circuit separation unit SEP controls the low level (0) so as to turn off the three-state inverters INV9 and INV10 (corresponding to write drivers for the ferroelectric elements). A signal E1 is input. As a result, the output terminals of the three-state inverters INV9 and INV10 are both in a high impedance state, and the loop structure portion LOOP and the nonvolatile memory portion NVM are electrically separated.

  Further, during the normal operation of the data holding device, the high-level (1) F reset signals FRSTD and FRSTU are input to the nonvolatile memory unit NVM. As a result, the transistors Q1a, Q1b, Q2a, and Q2b are all turned on, and both ends of the ferroelectric elements CL1a, CL1b, CL2a, and CL2b are short-circuited, so that each ferroelectric element is not intended. It is possible to avoid voltage application. At this time, a low level (0) voltage signal is applied to the first plate lines PL1D and PL1U and the second plate lines PL2D and PL2U.

  Further, during the normal operation of the data holding device, a low level (0) sense amplifier enable signal SAE is input to the set / reset control unit SRC. Accordingly, the first output signal SDnC_OUT and the second output signal SDC_OUT of the source amplifier SA are both fixed at a high level. Therefore, the external set signal SN and the external reset signal RN are output as they are as the internal set signal SNL and the internal reset signal RNL from the set / reset control unit SRC to the loop structure unit LOOP.

  Further, during the normal operation of the data holding device, the low level (0) analog enable signals TESTD and TESTU are input to the test circuit unit TEST. As a result, the switches SW7 to SW10 are all turned off, and the three-state inverters INV11 to INV14 are all turned on. At this time, a high level (1) voltage signal is applied to both the first digital plate line PL1_D and the second digital plate line PL2_D. Therefore, a low level (0) voltage signal is applied to the first plate lines PL1D and PL1U and the second plate lines PL2D and PL2U via the three-state inverters INV11 to INV14, respectively. At this time, a low level (0) voltage signal is applied to the first analog plate lines PL1D_A and PL1U_A and the second analog plate lines PL2D_A and PL2U_A.

  Next, a data write operation (data save operation to the non-volatile storage unit NVM) of the data holding device will be described. FIG. 31 is a circuit diagram showing an operation state of each part of the apparatus during a data write operation.

  During the data write operation of the data holding device, a high level (1) data holding control signal HS is input to the clock pulse control unit CPC so as to invalidate the external clock signal CP. As a result, the internal clock signal CPL can be fixed at a high level without depending on the external clock signal CP, so the contents of the data stored in the loop structure portion LOOP (that is, the data to be saved in the nonvolatile storage portion NVM) As a result, the input path of the data signal D can be blocked so that the stability of the data write operation (data save operation) to the nonvolatile memory unit NVM can be improved. Become.

  Further, during the data write operation of the data holding device, the circuit separation unit SEP has a high level (1) so as to turn on the three-state inverters INV9 and INV10 (corresponding to a write driver to the ferroelectric element). A control signal E1 is input. As a result, the three-state inverters INV9 and INV10 are in a state in which the respective logic inversion outputs are possible, and the loop structure portion LOOP and the nonvolatile memory portion NVM are electrically connected.

  Further, during the data write operation of the data holding device, the low-level (0) F reset signals FRSTD and FRSTU are input to the nonvolatile memory unit NVM. As a result, the transistors Q1a, Q1b, Q2a, and Q2b are all turned off, and the both ends of the ferroelectric elements CL1a, CL1b, CL2a, and CL2b are all in an open state (non-short state). A data write voltage can be applied to the ferroelectric element. At this time, the same pulse voltage signal (for example, high level to low level) is applied to the first plate lines PL1D and PL1U and the second plate lines PL2D and PL2U as the data write voltages. Applied. By applying such a pulse voltage signal, the remanent polarization state inside the ferroelectric element is set to either the inversion state or the non-inversion state. Since this is the same as described above, a duplicate description is omitted.

  In addition, during the data write operation of the data holding device, the low / (0) sense amplifier enable signal SAE is input to the set / reset control unit SRC as in the normal operation. Accordingly, the first output signal SDnC_OUT and the second output signal SDC_OUT of the source amplifier SA are both fixed at a high level. Therefore, the external set signal SN and the external reset signal RN are output as they are as the internal set signal SNL and the internal reset signal RNL from the set / reset control unit SRC to the loop structure unit LOOP.

  Further, during the data write operation of the data holding device, the analog enable signals TESTD and TESTU at the low level (0) are input to the test circuit unit TEST as in the normal operation. As a result, the switches SW7 to SW10 are all turned off, and the three-state inverters INV11 to INV14 are all turned on. At this time, the same pulse voltage signal (for example, low level to high level) is applied to both the first digital plate line PL1_D and the second digital plate line PL2_D. Accordingly, the same pulse voltage signal (for example, high level to low level) is applied to the first plate lines PL1D and PL1U and the second plate lines PL2D and PL2U via the three-state inverters INV11 to INV14, respectively. . At this time, a low level (0) voltage signal is applied to the first analog plate lines PL1D_A and PL1U_A and the second analog plate lines PL2D_A and PL2U_A.

  Next, a data read operation (data return operation to the loop structure unit LOOP) of the data holding device will be described. FIG. 32 is a circuit diagram showing an operation state of each part of the apparatus during a data read operation.

  During the data reading operation of the data holding device, the low-level (0) data holding control signal HS is input to the clock pulse control unit CPC so as to enable the external clock signal CP as in the normal operation. . As a result, the external clock signal CP (more precisely, its logic inversion signal) is supplied from the clock pulse control unit CPC to the loop structure unit LOOP as the internal clock signal CPL. As described above, in the data holding device of the fifth modified example, data recovery from the nonvolatile memory unit NVM to the loop structure unit LOOP is performed without stopping the input of the external clock signal CP.

  Further, during the data read operation of the data holding device, the circuit separation unit SEP is configured to turn off the three-state inverters INV9 and INV10 (corresponding to a write driver for the ferroelectric element) as in the normal operation. A low level (0) control signal E1 is input. As a result, the output terminals of the three-state inverters INV9 and INV10 are both in a high impedance state, and the loop structure portion LOOP and the nonvolatile memory portion NVM are electrically separated.

  Further, during the data read operation of the data holding device, the low-level (0) F reset signals FRSTD and FRSTU are input to the nonvolatile memory unit NVM. As a result, the transistors Q1a, Q1b, Q2a, and Q2b are all turned off, and the both ends of the ferroelectric elements CL1a, CL1b, CL2a, and CL2b are all in an open state (non-short state). A data read voltage can be applied to the ferroelectric element. At this time, as the data read voltage, a predetermined pulse voltage signal (for example, low level to high level) is applied to the first plate lines PL1D and PL1U while the second plate lines PL2D and PL2U are maintained at the low level. ) Is applied. By applying such a pulse voltage signal, the D system output terminal of the nonvolatile memory unit NVM (the connection node between the negative electrode terminal of the ferroelectric element CL1a and the positive electrode terminal of the ferroelectric element CL1b), and the U system output terminal A return voltage signal corresponding to the remanent polarization state in the ferroelectric element (first of the source amplifier SA) is connected to (a connection node between the negative end of the ferroelectric element CL2a and the positive end of the ferroelectric element CL2b). An input signal SDnC and a second input signal SDC) appear. Since this is the same as described above, a duplicate description is omitted.

  In addition, during the data read operation of the data holding device, the high level (1) sense amplifier enable signal SAE is input to the set / reset control unit SRC. As a result, the first output signal SDnC_OUT and the second output signal SDC_OUT of the source amplifier SA have logic levels corresponding to the voltage level of the first input signal SDnC and the voltage level of the second input signal SDC, respectively. . Specifically, if the first input signal SDnC is higher in voltage than the second input signal SDC, the first output signal SDnC_OUT becomes high level (1), and the second output signal SDC_OUT becomes low level (0). Become. Conversely, if the first input signal SDnC is lower in voltage than the second input signal SDC, the first output signal SDnC_OUT becomes low level (0), and the second output signal SDC_OUT becomes high level (1).

  Further, during the data read operation of the data holding device, both the external set signal SN and the external reset signal RN that are input to the set / reset control unit SRC are fixed to the high level (1). Thus, the first output signal SDnC_OUT and the second output signal SDC_OUT of the source amplifier SA are output as they are as the internal set signal SNL and the internal reset signal RNL from the set / reset control unit SRC to the loop structure unit LOOP.

  In the loop structure section LOOP, when the internal set signal SNL inputted to the NAND operator NAND1 and NAND3 becomes low level (0), the output signal Q is forcibly set to high level (1), and the negative logic When the internal reset signal RNL input to the product calculators NAND2 and NAND4 becomes low level (0), the output signal Q is forced to become low level (0). That is, in the data holding device of the fifth configuration example, the loop structure unit LOOP set / reset control (internal set signal SNL and internal reset signal RNL generation control) is performed based on the output signal of the nonvolatile storage unit NVM. Thus, a data read operation (return operation) is realized.

  For example, consider a case where the saved data written from the loop structure unit LOOP to the nonvolatile memory unit NVM is “1” by the data write operation of the data holding device. In this case, the first input signal SDnC input from the nonvolatile storage unit NVM to the set / reset control unit SRC by the data read operation of the data holding device is also input from the nonvolatile storage unit NVM to the set / reset control unit SRC. The voltage is lower than the second input signal SDC. Accordingly, the first output voltage SDnC_OUT of the source amplifier SA becomes low level (0), and the internal set signal SNL becomes low level (0). Therefore, the output signal Q is forcibly set to high level (1). Set. This means that the saved data “1” written in the volatile storage unit NVM is restored to the loop structure unit LOOP.

  Conversely, a case is considered in which the saved data written from the loop structure unit LOOP to the nonvolatile memory unit NVM is “0” by the data write operation of the data holding device. In this case, the first input signal SDnC input from the nonvolatile storage unit NVM to the set / reset control unit SRC by the data read operation of the data holding device is also input from the nonvolatile storage unit NVM to the set / reset control unit SRC. Is higher than the second input signal SDC. Accordingly, the second output voltage SDC_OUT of the source amplifier SA becomes low level (0), and the internal reset signal RNL becomes low level (0). Therefore, the output signal Q is forcibly set to low level (0). Reset. This means that the saved data “0” written in the volatile storage unit NVM has been restored to the loop structure unit LOOP.

  Further, during the data read operation of the data holding device, the analog enable signals TESTD and TESTU at the low level (0) are input to the test circuit unit TEST as in the normal operation. As a result, the switches SW7 to SW10 are all turned off, and the three-state inverters INV11 to INV14 are all turned on. At this time, a predetermined pulse voltage signal (for example, high level to low level) is applied to the first digital plate line PL1_D, and a high level (1) voltage signal is applied to the second digital plate line PL2_D. Applied. Accordingly, the same pulse voltage signal (for example, low level to high level) is applied to the first plate lines PL1D and PL1U through the three-state inverters INV11 and INV12, respectively, and the second plate lines PL2D and PL2U are applied to the second plate lines PL2D and PL2U. The low level (0) voltage signal is applied through the three-state inverters INV13 and INV14, respectively. At this time, a low level (0) voltage signal is applied to the first analog plate lines PL1D_A and PL1U_A and the second analog plate lines PL2D_A and PL2U_A.

  As described above, the data holding device of the fifth modification differs from the previous configuration in that the loop structure portion LOOP is not used as a sense amplifier for data restoration, but a separate independent sense amplifier SA is provided. Is used to perform set / reset control of the loop structure portion LOOP. Further, the data holding device of the fifth modification is configured to control whether or not the external clock signal CP is transmitted to the loop structure unit LOOP as the internal clock signal CPL without stopping. This configuration eliminates the need to stop the external clock CP when saving / restoring data, facilitating timing analysis during design, and compatibility with low-power consumption technologies using gated clocks, etc. Will be better.

  Next, the test operation of the data holding device (analog characteristic evaluation operation of the ferroelectric element) will be described. FIG. 33 is a circuit diagram showing an operation state of each part of the apparatus during a test operation (particularly, at a restoration step of stored data included in a series of test operation sequences). In the following, an example in which analog characteristic evaluation (measurement of voltage value of the second input signal SDC) of the second input signal SDC input to the source amplifier SA from the U-system output terminal of the nonvolatile memory unit NVM is performed will be described. This will be specifically described as “the U system test operation of the non-volatile memory unit NVM”.

  At the time of the U system test operation of the nonvolatile memory unit NVM, the clock pulse control unit CPC receives low level (0) data so as to enable the external clock signal CP as in the normal operation or data read operation. The holding control signal HS is input. As a result, the external clock signal CP (more precisely, its logic inversion signal) is supplied from the clock pulse control unit CPC to the loop structure unit LOOP as the internal clock signal CPL. Thus, in the data holding device of the fifth modified example, the U-system test operation of the nonvolatile memory unit NVM is performed without stopping the input of the external clock signal CP.

  Further, during the U-system test operation of the nonvolatile memory unit NVM, the circuit separation unit SEP has three-state inverters INV9 and INV10 (corresponding to write drivers for ferroelectric elements) as in the normal operation and the data read operation. ) Is turned off so that a low level (0) control signal E1 is input. As a result, the output terminals of the three-state inverters INV9 and INV10 are both in a high impedance state, and the loop structure portion LOOP and the nonvolatile memory portion NVM are electrically separated.

  Further, during the U system test operation of the nonvolatile memory unit NVM, the low level (0) F reset signal FRSTU is input to the U system of the nonvolatile memory unit NVM. As a result, both the transistors Q2a and Q2b are turned off, and both ends of the ferroelectric elements CL2a and CL2b are both in an open state (non-shorted state), so that data is stored for each ferroelectric element. A read voltage can be applied. At this time, as the data read voltage, a predetermined pulse voltage signal (for example, low level to high level) is applied to the first plate line PL1U while the second plate line PL2U is maintained at the low level. . By applying such a pulse voltage signal, a ferroelectric element is connected to the U-system output end (a connection node between the negative end of the ferroelectric element CL2a and the positive end of the ferroelectric element CL2b) of the nonvolatile memory unit NVM. A return voltage signal (corresponding to the second input signal SDC of the source amplifier SA) corresponding to the residual polarization state appears. Since this is as described above, a duplicate description is omitted.

  On the other hand, during the U system test operation of the nonvolatile memory unit NVM, the high level (1) F reset signal FRSTD is input to the D system of the nonvolatile memory unit NVM. As a result, the transistors Q1a and Q1b are both turned on, and both ends of the ferroelectric elements CL1a and CL1b are short-circuited. At this time, both the first plate line PL1D and the second plate line PL2D are arbitrarily set between a predetermined analog voltage value (low level (ground voltage VSS) and high level (power supply voltage VDD)). A reference voltage signal Vref having an intermediate voltage value that can be set is applied. Therefore, from the D system output terminal (the connection node between the negative electrode terminal of the ferroelectric element CL1a and the positive electrode terminal of the ferroelectric element CL1b) of the nonvolatile memory unit NVM to the source amplifier SA as the first input signal SDnC The reference voltage signal Vref is directly input. The significance of directly inputting the reference voltage Vref as the first input signal SDnC of the source amplifier SA will be described later in detail.

  In addition, during the U-system test operation of the nonvolatile memory unit NVM, the high level (1) sense amplifier enable signal SAE is input to the set / reset control unit SRC. Accordingly, the first output signal SDnC_OUT and the second output signal SDC_OUT of the source amplifier SA have logic levels corresponding to the levels of the voltage level of the first input signal SDnC and the voltage level of the second input signal SDC, respectively. Become. Specifically, if the first input signal SDnC is higher in voltage than the second input signal SDC, the first output signal SDnC_OUT becomes high level (1), and the second output signal SDC_OUT becomes low level (0). Become. Conversely, if the first input signal SDnC is lower in voltage than the second input signal SDC, the first output signal SDnC_OUT becomes low level (0), and the second output signal SDC_OUT becomes high level (1).

  Further, during the U-system test operation of the nonvolatile memory unit NVM, both the external set signal SN and the external reset signal RN input to the set / reset control unit SRC are fixed to the high level (1). Thus, the first output signal SDnC_OUT and the second output signal SDC_OUT of the source amplifier SA are output as they are as the internal set signal SNL and the internal reset signal RNL from the set / reset control unit SRC to the loop structure unit LOOP. This is the same as in the data read operation described above.

  Further, during the U system test operation of the nonvolatile memory unit NVM, the U system analog enable signal TESTU input to the test circuit unit TEST is set to a low level (0). As a result, the switches SW7 and SW9 are both turned off, and the three-state inverters INV11 and INV13 are both turned on. At this time, a predetermined pulse voltage signal (for example, high level to low level) is applied to the first digital plate line PL1_D, and a high level (1) voltage signal is applied to the second digital plate line PL2_D. Applied. Therefore, a predetermined pulse voltage signal (for example, low level to high level) is applied to the first plate line PL1U of the U system via the three-state inverter INV11, and the second plate line PL2U of the U system is A low level (0) voltage signal is applied via the three-state inverter INV13. At this time, a low level (0) voltage signal is applied to the U-system first analog plate line PL1U_A and the U-system second analog plate line PL2U_A.

  On the other hand, during the U system test operation of the nonvolatile memory unit NVM, the D system analog enable signal TESTD input to the test circuit unit TEST is set to the high level (1). As a result, the switches SW8 and SW10 are both turned on, and the three-state inverters INV12 and INV14 are both turned off. At this time, the reference voltage signal Vref having a predetermined voltage value is applied to the first analog plate line PL1D_A of the D system and the second analog plate line PL2D_A of the D system. Accordingly, the reference voltage signal Vref having a predetermined voltage value is applied to the first plate line PL1D of the D system and the second plate line PL2D of the D system via the switches SW8 and SW10, respectively.

<Analog characteristics evaluation operation>
FIG. 34 is a timing chart for explaining the analog characteristic evaluation operation of the ferroelectric element. The pulse voltage signal applied to the first plate line PL1U of the U system is applied to the U system output terminal of the nonvolatile memory unit NVM. The return voltage signal that appears (corresponding to the second input signal SDC of the source amplifier SA), and the reference voltage signal Vref (in FIG. 34, three voltage values Vref1 to Vref1) that are directly input to the D system output terminal of the nonvolatile memory unit NVM. Vref3) is depicted.

  During the U system test operation of the nonvolatile memory unit NVM, a predetermined pulse voltage signal (for example, from a low level) is applied to the U system first plate line PL1U while the U system second plate line PL2U is maintained at a low level. When the high level is applied, the U-system output end of the nonvolatile memory unit NVM (the connection node between the negative end of the ferroelectric element CL2a and the positive end of the ferroelectric element CL2b) is also described above. Thus, a return voltage signal (corresponding to the second input signal SDC of the source amplifier SA) corresponding to the remanent polarization state in the ferroelectric element appears.

  Here, when data “0” is stored in the non-volatile storage unit NVM (S = 0), the second input signal SDC of the source amplifier SA is the first return voltage level VSO (S = 0) ( When the data “1” is stored in the non-volatile storage unit NVM (S = 1), the second input signal SDC of the source amplifier SA is changed to the first return voltage level VSO. The second return voltage level VSO (S = 1) (corresponding to the above-described logic WH) is higher than (S = 0).

  On the other hand, during the U system test operation of the nonvolatile memory unit NVM, the D system output terminal of the nonvolatile memory unit NVM (a connection node between the negative electrode terminal of the ferroelectric element CL1a and the positive electrode terminal of the ferroelectric element CL1b) A reference voltage signal Vref having an arbitrary analog voltage value (corresponding to the first input voltage SDnC of the source amplifier SA) is directly input from the outside of the apparatus.

  Therefore, the reference voltage signal Vref inputted as the first input signal SDnC of the source amplifier SA is inputted while the return voltage signal appearing at the U system output terminal of the nonvolatile memory unit NVM is inputted as the second input signal SDC of the source amplifier SA. The voltage value is sequentially changed by step control or sweep control, and each time it appears at the U system output terminal of the nonvolatile memory unit NVM by monitoring the logic level of the output signal Q returned to the loop structure unit LOOP. The analog voltage value of the return voltage signal (second input signal SDC of the source amplifier SA) can be known.

  FIG. 35 is a schematic diagram showing the relationship between the reference voltage signal Vref and the output signal Q. In the test sequence shown in this figure, the data “0” writing step (0S), the data reading step (R), the data “1” writing step (1S), and the data reading step (R) are set to 1. As the cycle, the logic level of the output signal Q returned to the loop structure unit LOOP is monitored each time while the voltage value of the reference voltage signal Vref is sequentially changed for each cycle. The analog voltage value of the return voltage signal that appears at the U-system output terminal of the sex memory unit NVM is measured.

  The data “0” writing step (0S) and the data “1” writing step (1S) are performed after the data “0” and the data “1” are input to the loop structure portion LOOP. This is a step of saving data stored in the loop structure section LOOP in the storage section NVM. The data reading step (R) is a step of returning the stored data of the nonvolatile storage unit NVM to the loop structure unit LOOP and reading the return data as the output signal Q.

  A specific description will be given below with reference to the example of FIG.

  First, in the first cycle X1, the voltage value of the reference voltage signal Vref is lower than both the first return voltage level VSO (S = 0) and the second return voltage level VSO (S = 1). Set to the value Vref1. Therefore, regardless of whether data “0” or data “1” is written in the nonvolatile storage unit NVM, the data “1” is always returned to the loop structure unit LOOP. That is, in the two data read steps included in the first cycle X1, data “1” is read as the output signal Q in both cases.

  Next, in the second cycle X2, the voltage value of the reference voltage signal Vref is set to a voltage value Vref2 higher than the voltage value Vref1 set in the first cycle X1. In the example of FIG. 35, the voltage value Vref2 is higher than the first return voltage level VSO (S = 0) and lower than the second return voltage level VSO (S = 1). Therefore, when data “0” is written in the nonvolatile storage unit NVM, data “0” is restored to the loop structure unit LOOP, and when data “1” is written in the nonvolatile storage unit NVM, the loop Data “1” is returned to the structure part LOOP. That is, in the two data read steps included in the second cycle X2, the data “0” and the data “1” are sequentially read as the output signal Q. This is an operating state in which the content (0/1) of data stored in the nonvolatile storage unit NVM is determined and data restoration to the loop structure unit LOOP is normally performed.

  At this time, it can be seen that the first return voltage level VSO (S = 0) is higher than the voltage value Vref1 and lower than the voltage value Vref2.

  Thereafter, in the third cycle X3, the voltage value of the reference voltage signal Vref is set to a voltage value Vref3 higher than the voltage value Vref2, and in the subsequent fourth cycle X4, the voltage value of the reference voltage signal Vref is higher than the voltage value Vref3. The high voltage value Vref4 is set. However, the voltage values Vref3 and Vref4 are higher than the first return voltage level VSO (S = 0) but lower than the second return voltage level VSO (S = 1), similarly to the voltage value Vref2. When data “0” is written to the nonvolatile storage unit NVM, data “0” is restored to the loop structure unit LOOP, and when data “1” is written to the nonvolatile storage unit NVM, the loop structure unit LOOP is restored. Data “1” is restored to. That is, in the two data read steps included in the third cycle X3 and the fourth cycle X4, the data “0” and the data “1” are sequentially read as the output signal Q.

  Next, in the fifth cycle X5, the voltage value of the reference voltage signal Vref is set to a voltage value Vref5 that is higher than the voltage value Vref4. In the example of FIG. 35, the voltage value Vref5 is higher than both the first return voltage level VSO (S = 0) and the second return voltage level VSO (S = 1). Therefore, regardless of whether data “0” or data “1” is written in the nonvolatile storage unit NVM, the data “0” is always restored to the loop structure unit LOOP. That is, in the two data read steps included in the fifth cycle X5, data “0” is read as the output signal Q in both cases.

  At this time, it can be seen that the second return voltage level VSO (S = 1) is higher than the voltage value Vref4 and lower than the voltage value Vref5.

  In the example of FIG. 35, it is depicted that the sequence after the sixth step X6 is continued thereafter, but the first return voltage level VSO (S = 0) and the second return voltage level. The test sequence may be terminated when both analog voltage values of VSO (S = 1) are found.

  In FIG. 35, a test sequence in which the data “0” write step (0S), the data read step (R), the data “1” write step (1S), and the data read step (R) are one cycle. However, the test sequence is not limited to this. For example, the data “0” writing step (0S) and the data reading step (R) are defined as one cycle, and the first sequence After measuring only the return voltage level VSO (S = 0), the data “1” writing step (1S) and the data reading step (R) are made one cycle again, and the second return voltage level VSO (S = 1) Only the measurement may be performed.

  In the above description, an example in which the analog characteristic evaluation (voltage value measurement of the second input signal SDC) of the second input signal SDC input to the source amplifier SA from the U-system output terminal of the nonvolatile storage unit NVM is performed is given as an example. As described above, the analog characteristic evaluation (measurement of the voltage value of the first input signal SDnC) of the first input signal SDnC input to the source amplifier SA from the D system output terminal of the nonvolatile memory unit NVM is also performed. Needless to say, the same is true.

  That is, in the case of measuring the voltage value of the first input signal SDnC, a connection node between the negative electrode end of the D system output terminal ferroelectric element CL1a and the positive electrode terminal of the ferroelectric element CL1b of the nonvolatile memory unit NVM). A recovery voltage signal (corresponding to the first input voltage SDnC of the source amplifier SA) corresponding to the content of the stored data is extracted from the U system output terminal (the negative electrode terminal of the ferroelectric element CL2a and the ferroelectric memory). The reference voltage signal Vref (corresponding to the second input voltage SDC of the source amplifier SA) having an arbitrary analog voltage value is directly input to the connection node with the positive terminal of the body element CL2b, and a test sequence similar to the above is performed. Just do it.

<Scan path>
Next, the test operation of the data holding device using the scan path will be described. FIG. 36 is a block diagram for explaining the test operation of the data holding device utilizing the scan path. The arithmetic device 1 is a semiconductor integrated circuit device having x (where x is an integer of 2 or more) registers REG1 to REGx in parallel. Each of the registers REG1 to REGx corresponds to the data holding device (see FIG. 26 and the like) of the fifth modified example described above.

  During normal operation of the arithmetic unit 1, data D1 to Dx are input from the previous stage logic circuit (not shown) to the registers REG1 to REGx, respectively, and from the registers REG1 to REGx to the subsequent stage logic circuit (not shown), respectively. Output signals Q1-Qx are output.

  On the other hand, during the test operation of the arithmetic device 1, a control signal is input from the tester (sequencer) 2 so that the registers REG1 to REGx form a serially connected shift register via a scan path. That is, the scan data SD1 is input from the tester 2 to the first-stage register REG1, and the scan output signal SO1 of the register REG1 is input to the register REG2 as scan data SD2. The same applies to the registers after the next stage. The scan output signal of the previous stage register is sequentially input as the scan data of the subsequent stage register, and the scan output signal SOx output from the final stage register REGx is input to the tester 2. The

  Thus, by adopting a configuration in which the test operation of the data holding device is performed by utilizing the scan path, even in a system in which a large number of data holding devices to be tested (registers REG1 to REGx in FIG. 36) exist, they are external to the device. The test operation can be appropriately performed without unnecessarily increasing the number of pins of the data output terminal to be drawn.

  FIG. 37A is a flowchart showing an example of a test operation utilizing a scan path, and basically follows the test sequence illustrated in FIG.

  First, in step S11, data “0” is input to the loop structure portions LOOP of the registers REG1 to REGx. As an input method of data “0”, a method of inputting data “0” from the input end of data D, a method of inputting data “0” from the input end of scan data SD, or an external reset signal RN is used. Any method of inputting data “0” by resetting the loop structure portion LOOP using the loop structure portion LOOP may be employed.

  Next, in step S12, data is saved from each loop structure unit LOOP of the registers REG1 to REGx to each nonvolatile memory unit NVM. In subsequent step S13, data is saved from each nonvolatile memory unit NVM of the registers REG1 to REGx. Data restoration is performed for each loop structure section LOOP. At this time, when measuring the voltage value of the first input signal SDnC, an arbitrary reference voltage signal Vref may be directly input as the second input voltage SDC. Conversely, the voltage value of the second input signal SDC is measured. When performing, an arbitrary reference voltage signal Vref may be directly input as the first input voltage SDnC. Since such data saving / restoring operation is as described above, a duplicate description is omitted.

  Next, in step S14, serial output of the data restored to each loop structure section LOOP of the registers REG1 to REGx is performed using the scan path. Specifically, the scan data SD1 is input x times from the tester 2 to the front-stage register REG1 in synchronization with the clock signal of x, and the last-stage register REGx responds to the tester 2 accordingly. The scan output signal SOx is output x times. That is, the data returned to the loop structure portions LOOP of the registers REG1 to REGx is serially output to the tester 2 in the reverse order (the order of the registers REGx to REG1). At this time, the content of the scan data SD1 input from the tester 2 to the register REG1 in the foremost stage is not questioned.

  Next, in step S15, data “1” is input to each loop structure unit LOOP of the registers REG1 to REGx. As an input method of data “1”, a method of inputting data “1” from the input end of data D, a method of inputting data “1” from the input end of scan data SD, or an external set signal SN Any method of inputting data “1” by setting the loop structure portion LOOP using the loop structure portion LOOP may be employed.

  Next, in step S16, data is saved from each loop structure unit LOOP of the registers REG1 to REGx to each nonvolatile memory unit NVM. In subsequent step S17, data is saved from each nonvolatile memory unit NVM of the registers REG1 to REGx. Data restoration is performed for each loop structure section LOOP. At this time, when measuring the voltage value of the first input signal SDnC, an arbitrary reference voltage signal Vref may be directly input as the second input voltage SDC. Conversely, the voltage value of the second input signal SDC is measured. When performing, an arbitrary reference voltage signal Vref may be directly input as the first input voltage SDnC. Since such data saving / restoring operation is as described above, a duplicate description is omitted.

  Next, in step S18, serial output of the data restored to each loop structure section LOOP of the registers REG1 to REGx is performed using the scan path. Specifically, the scan data SD1 is input x times from the tester 2 to the front-stage register REG1 in synchronization with the clock signal of x, and the last-stage register REGx responds to the tester 2 accordingly. The scan output signal SOx is output x times. That is, the data returned to the loop structure portions LOOP of the registers REG1 to REGx is serially output to the tester 2 in the reverse order (the order of the registers REGx to REG1).

  Next, in step S19, the voltage value of the reference voltage Vref is updated, and the flow returns to step S11. Such a series of steps is set as one cycle, the test sequence illustrated in FIG. 35 is executed, and the voltage values of the first input signal SDnC to the second input signal SDC are measured.

  FIG. 37B is a flowchart showing another example of the test operation utilizing the scan path, and basically follows the test sequence illustrated in FIG.

  First, in step S21, data “0” is input to the loop structure portions LOOP of the registers REG1 to REGx. As an input method of data “0”, a method of inputting data “0” from the input end of data D, a method of inputting data “0” from the input end of scan data SD, or an external reset signal RN is used. Any method of inputting data “0” by resetting the loop structure portion LOOP using the loop structure portion LOOP may be employed.

  Next, in step S22, data is saved from each loop structure unit LOOP of the registers REG1 to REGx to each nonvolatile memory unit NVM. In subsequent step S23, data is saved from each nonvolatile memory unit NVM of the registers REG1 to REGx. Data restoration is performed for each loop structure section LOOP. At this time, when measuring the voltage value of the first input signal SDnC, an arbitrary reference voltage signal Vref may be directly input as the second input voltage SDC. Conversely, the voltage value of the second input signal SDC is measured. When performing, an arbitrary reference voltage signal Vref may be directly input as the first input voltage SDnC. Since such data saving / restoring operation is as described above, a duplicate description is omitted.

  Next, in step S24, the scan path is used to serially output the restored data to the loop structure portions LOOP of the registers REG1 to REGx, and to the loop structure portions LOOP of the registers REG1 to REGx. , Serial input of data “1” is performed. Specifically, in synchronization with the clock signal of x, the scan data SD1 of data “1” is input x times from the tester 2 to the register REG1 in the forefront stage, and the register REGx in the last stage is input accordingly. The scan output signal SOx is output x times to the tester 2. That is, to the tester 2, the data returned to the loop structure units LOOP of the registers REG1 to REGx is serially output in the reverse order (the order of the registers REGx to REG1), and the loop structure units of the registers REG1 to REGx. For LOOP, data “1” is serially input sequentially. Therefore, step S14 and step S15 in FIG. 37A can be combined into a single step S24.

  Next, in step S25, data is saved from each loop structure unit LOOP of the registers REG1 to REGx to each nonvolatile memory unit NVM. In subsequent step S26, data is saved from each nonvolatile memory unit NVM of the registers REG1 to REGx. Data restoration is performed for each loop structure section LOOP. At this time, when measuring the voltage value of the first input signal SDnC, an arbitrary reference voltage signal Vref may be directly input as the second input voltage SDC. Conversely, the voltage value of the second input signal SDC is measured. When performing, an arbitrary reference voltage signal Vref may be directly input as the first input voltage SDnC. Since such data saving / restoring operation is as described above, a duplicate description is omitted.

  Next, in step S27, the scan path is used to serially output the restored data to the loop structure portions LOOP of the registers REG1 to REGx, and to the loop structure portions LOOP of the registers REG1 to REGx. , Serial input of data “0” is performed. Specifically, in synchronization with the x-number of clock signals, the scan data SD1 of data “0” is input x times from the tester 2 to the first-stage register REG1, and in response to this, the last-stage register REGx The scan output signal SOx is output x times to the tester 2. That is, to the tester 2, the data returned to the loop structure units LOOP of the registers REG1 to REGx is serially output in the reverse order (the order of the registers REGx to REG1), and the loop structure units of the registers REG1 to REGx. For LOOP, data “0” is serially input sequentially. Therefore, step S18 and step S11 in FIG. 37A can be combined into a single step S27.

  Next, in step S28, the voltage value of the reference voltage Vref is updated, and the flow returns to step S22. Such a series of steps is set as one cycle, the test sequence illustrated in FIG. 35 is executed, and the voltage values of the first input signal SDnC to the second input signal SDC are measured.

  As described above, if the data holding device of the fifth modification is used, it is possible to evaluate the analog characteristics of the ferroelectric element in detail even when it is incorporated in the system.

<Sixth Modification>
FIG. 38 is a circuit diagram showing a sixth modification of the data holding device according to the present invention. Note that this modification has substantially the same configuration as the fifth modification (FIG. 26), and only the output signal Q of the loop structure section LOOP is input to the circuit separation section SEP. Note that the circuit separation unit SEP directly inputs the output signal Q to the three-state inverter INV9, whereas the three-state inverter INV10 receives the output signal Q via the newly inserted inverter 10 ′. A logic inversion signal is input. By adopting such a configuration, the circuit separation unit SEP, the nonvolatile storage unit NVM, the set / reset control unit SRC, and the like can be retrofitted without any modification to the loop structure unit LOOP. Existing data storage devices can be easily made nonvolatile.

<Seventh Modification>
FIG. 39 is a circuit diagram showing a seventh modification of the data holding device according to the present invention. In this modification, in the data holding device of FIG. 1, the first plate line, the second plate line, and the F reset signal line are separated into two systems (U system / D system), respectively. This corresponds to a configuration incorporating the test circuit unit TEST.

  First, the normal operation of the data holding device will be described. FIG. 40 is a circuit diagram showing the operating state of each part of the apparatus during normal operation.

  During the normal operation of the data holding device, the loop structure section LOOP performs the latch operation of the data signal D based on the pulse-driven clock signal CLK or inverted clock signal CLKB.

  In the normal operation of the data holding device, in the circuit separation unit SEP, the control signal E1 is set to low level (0), both the switches SW3 and SW4 are turned off, and the control signal E2 is set to high level ( 1), the first input terminals (1) of the multiplexers MUX1 and MUX2 are selected. Thus, a normal loop of the loop structure portion LOOP is formed in a state where the loop structure portion LOOP and the nonvolatile memory portion NVM are electrically separated.

  Further, during the normal operation of the data holding device, the high-level (1) F reset signals FRSTD and FRSTU are input to the nonvolatile memory unit NVM. As a result, the transistors Q1a, Q1b, Q2a, and Q2b are all turned on, and both ends of the ferroelectric elements CL1a, CL1b, CL2a, and CL2b are short-circuited, so that each ferroelectric element is not intended. It is possible to avoid voltage application. At this time, a low level (0) voltage signal is applied to the first plate lines PL1D and PL1U and the second plate lines PL2D and PL2U.

  Further, during the normal operation of the data holding device, the low level (0) analog enable signals TESTD and TESTU are input to the test circuit unit TEST. As a result, the switches SW7 to SW10 are all turned off, and the three-state inverters INV11 to INV14 are all turned on. At this time, a high level (1) voltage signal is applied to both the first digital plate line PL1_D and the second digital plate line PL2_D. Therefore, a low level (0) voltage signal is applied to the first plate lines PL1D and PL1U and the second plate lines PL2D and PL2U via the three-state inverters INV11 to INV14, respectively. At this time, a low level (0) voltage signal is applied to the first analog plate lines PL1D_A and PL1U_A and the second analog plate lines PL2D_A and PL2U_A.

  Next, a data write operation (data save operation to the non-volatile storage unit NVM) of the data holding device will be described. FIG. 41 is a circuit diagram showing an operation state of each part of the apparatus during a data write operation.

  During the data write operation of the data holding device, the clock signal CLK and the inverted clock signal CLKB input to the loop structure unit LOOP are fixed at the low level (0) and the high level (1), respectively. This makes it possible to block the input path of the data signal D so that the content of the data stored in the loop structure section LOOP (that is, data to be saved in the nonvolatile storage section NVM) does not change. Thus, the stability of the data write operation (data save operation) to the nonvolatile storage unit NVM can be improved.

  In the data writing operation of the data holding device, in the circuit separation unit SEP, the control signal E1 is set to the high level (1), the switches SW3 and SW4 are turned on, and the control signal E2 is set to the high level (1). ) And the first input terminals (1) of the multiplexers MUX1 and MUX2 are selected. Thereby, the loop structure part LOOP and the nonvolatile memory part NVM are electrically connected in a state where the normal loop of the loop structure part LOOP is formed.

  Further, during the data write operation of the data holding device, the low-level (0) F reset signals FRSTD and FRSTU are input to the nonvolatile memory unit NVM. As a result, the transistors Q1a, Q1b, Q2a, and Q2b are all turned off, and the both ends of the ferroelectric elements CL1a, CL1b, CL2a, and CL2b are all in an open state (non-short state). A data write voltage can be applied to the ferroelectric element. At this time, the same pulse voltage signal (for example, high level to low level) is applied to the first plate lines PL1D and PL1U and the second plate lines PL2D and PL2U as the data write voltages. Applied. By applying such a pulse voltage signal, the remanent polarization state inside the ferroelectric element is set to either the inversion state or the non-inversion state. Since this is the same as described above, a duplicate description is omitted.

  Further, during the data write operation of the data holding device, the analog enable signals TESTD and TESTU at the low level (0) are input to the test circuit unit TEST as in the normal operation. As a result, the switches SW7 to SW10 are all turned off, and the three-state inverters INV11 to INV14 are all turned on. At this time, the same pulse voltage signal (for example, low level to high level) is applied to both the first digital plate line PL1_D and the second digital plate line PL2_D. Accordingly, the same pulse voltage signal (for example, high level to low level) is applied to the first plate lines PL1D and PL1U and the second plate lines PL2D and PL2U via the three-state inverters INV11 to INV14, respectively. . At this time, a low level (0) voltage signal is applied to the first analog plate lines PL1D_A and PL1U_A and the second analog plate lines PL2D_A and PL2U_A.

  Next, a data read operation (data return operation to the loop structure unit LOOP) of the data holding device will be described. FIG. 42 is a circuit diagram showing an operation state of each part of the apparatus during a data read operation.

  During the data read operation of the data holding device, the clock signal CLK and the inverted clock signal CLKB input to the loop structure unit LOOP are fixed at the low level (0) and the high level (1), respectively, as in the data write operation. The Note that the pulse driving of the clock signal CLK and the inverted clock signal CLKB is resumed after the data read operation is completed.

  In the data read operation of the data holding device, in the circuit separation unit SEP, the control signal E1 is set to the low level (0), the switches SW3 and SW4 are turned off, and the control signal E2 is set to the low level (0). ) And the second input terminals (0) of the multiplexers MUX1 and MUX2 are selected. As a result, the loop structure unit LOOP and the non-volatile storage unit NVM are electrically connected in a connection form in which data can be read from the nonvolatile storage unit NVM to the loop structure unit LOOP.

  Further, during the data read operation of the data holding device, the low-level (0) F reset signals FRSTD and FRSTU are input to the nonvolatile memory unit NVM. As a result, the transistors Q1a, Q1b, Q2a, and Q2b are all turned off, and the both ends of the ferroelectric elements CL1a, CL1b, CL2a, and CL2b are all in an open state (non-short state). A data read voltage can be applied to the ferroelectric element. At this time, as the data read voltage, a predetermined pulse voltage signal (for example, low level to high level) is applied to the first plate lines PL1D and PL1U while the second plate lines PL2D and PL2U are maintained at the low level. ) Is applied. By applying such a pulse voltage signal, the D system output terminal of the nonvolatile memory unit NVM (the connection node between the negative electrode terminal of the ferroelectric element CL1a and the positive electrode terminal of the ferroelectric element CL1b), and the U system output terminal Node signals V1 and V2 corresponding to the remanent polarization state in the ferroelectric element appear at (a connection node between the negative end of the ferroelectric element CL2a and the positive end of the ferroelectric element CL2b), respectively. In this manner, the return voltage signal (potential difference between the node voltage V1 and the node voltage V2) read from the nonvolatile memory unit NVM is raised from the low level (0) to the high level (1). When this occurs, the data is amplified by the loop structure section LOOP, and the held data before power shut-off is restored as the output signal Q. Since this is the same as described above, a duplicate description is omitted.

  Further, during the data read operation of the data holding device, the analog enable signals TESTD and TESTU at the low level (0) are input to the test circuit unit TEST as in the normal operation. As a result, the switches SW7 to SW10 are all turned off, and the three-state inverters INV11 to INV14 are all turned on. At this time, a predetermined pulse voltage signal (for example, high level to low level) is applied to the first digital plate line PL1_D, and a high level (1) voltage signal is applied to the second digital plate line PL2_D. Applied. Accordingly, the same pulse voltage signal (for example, low level to high level) is applied to the first plate lines PL1D and PL1U through the three-state inverters INV11 and INV12, respectively, and the second plate lines PL2D and PL2U are applied to the second plate lines PL2D and PL2U. The low level (0) voltage signal is applied through the three-state inverters INV13 and INV14, respectively. At this time, a low level (0) voltage signal is applied to the first analog plate lines PL1D_A and PL1U_A and the second analog plate lines PL2D_A and PL2U_A.

  Next, the test operation of the data holding device (analog characteristic evaluation operation of the ferroelectric element) will be described. FIG. 43 is a circuit diagram showing an operation state of each part of the apparatus at the time of a test operation (particularly, at the time of restoring stored data included in a series of test operation sequences). In the following, a case where the analog characteristic evaluation of the node voltage V2 appearing at the U system output terminal of the nonvolatile memory unit NVM is performed as an example is referred to as “U system test operation of the nonvolatile memory unit NVM”. This will be specifically described.

  During the U-system test operation of the nonvolatile memory unit NVM, the clock signal CLK and the inverted clock signal CLKB input to the loop structure unit LOOP are low level (0) and high level, respectively, as in the data write operation and the data read operation. Fixed at level (1). Note that the pulse driving of the clock signal CLK and the inverted clock signal CLKB is resumed after the test operation is completed.

  In the U system test operation of the nonvolatile memory unit NVM, in the circuit separation unit SEP, the control signal E1 is set to low level (0), the switches SW3 and SW4 are turned off, and the control signal E2 is set to low level. At level (0), the second input terminals (0) of the multiplexers MUX1 and MUX2 are selected. As a result, the loop structure unit LOOP and the non-volatile storage unit NVM are electrically connected in a connection form in which data can be read from the nonvolatile storage unit NVM to the loop structure unit LOOP.

  Further, during the U system test operation of the nonvolatile memory unit NVM, the low level (0) F reset signal FRSTU is input to the U system of the nonvolatile memory unit NVM. As a result, both the transistors Q2a and Q2b are turned off, and both ends of the ferroelectric elements CL2a and CL2b are both in an open state (non-shorted state), so that data is stored for each ferroelectric element. A read voltage can be applied. At this time, as the data read voltage, a predetermined pulse voltage signal (for example, low level to high level) is applied to the first plate line PL1U while the second plate line PL2U is maintained at the low level. . By applying such a pulse voltage signal, a ferroelectric element is connected to the U-system output end (a connection node between the negative end of the ferroelectric element CL2a and the positive end of the ferroelectric element CL2b) of the nonvolatile memory unit NVM. A node voltage V2 corresponding to the remanent polarization state appears. Since this is as described above, a duplicate description is omitted.

  On the other hand, during the U system test operation of the nonvolatile memory unit NVM, the high level (1) F reset signal FRSTD is input to the D system of the nonvolatile memory unit NVM. As a result, the transistors Q1a and Q1b are both turned on, and both ends of the ferroelectric elements CL1a and CL1b are short-circuited. At this time, the reference voltage signal Vref having a predetermined analog voltage value is applied to the first plate line PL1D and the second plate line PL2D. Accordingly, the node voltage V1 appearing at the D-system output terminal (the connection node between the negative electrode terminal of the ferroelectric element CL1a and the positive electrode terminal of the ferroelectric element CL1b) of the nonvolatile memory unit NVM becomes the reference voltage signal Vref. .

  Further, during the U system test operation of the nonvolatile memory unit NVM, the U system analog enable signal TESTU input to the test circuit unit TEST is set to a low level (0). As a result, the switches SW7 and SW9 are both turned off, and the three-state inverters INV11 and INV13 are both turned on. At this time, a predetermined pulse voltage signal (for example, high level to low level) is applied to the first digital plate line PL1_D, and a high level (1) voltage signal is applied to the second digital plate line PL2_D. Applied. Therefore, a predetermined pulse voltage signal (for example, low level to high level) is applied to the first plate line PL1U of the U system via the three-state inverter INV11, and the second plate line PL2U of the U system is A low level (0) voltage signal is applied via the three-state inverter INV13. At this time, a low level (0) voltage signal is applied to the U-system first analog plate line PL1U_A and the U-system second analog plate line PL2U_A.

  On the other hand, during the U system test operation of the nonvolatile memory unit NVM, the D system analog enable signal TESTD input to the test circuit unit TEST is set to the high level (1). As a result, the switches SW8 and SW10 are both turned on, and the three-state inverters INV12 and INV14 are both turned off. At this time, the reference voltage signal Vref having a predetermined voltage value is applied to the first analog plate line PL1D_A of the D system and the second analog plate line PL2D_A of the D system. Accordingly, the reference voltage signal Vref having a predetermined voltage value is applied to the first plate line PL1D of the D system and the second plate line PL2D of the D system via the switches SW8 and SW10, respectively.

  In this way, while reading the node voltage V2 appearing at the U-system output terminal of the nonvolatile memory unit NVM, the voltage value of the reference voltage signal Vref input as the node voltage V1 is sequentially changed by step control or sweep control, Each time, by monitoring the logic level of the output signal Q returned to the loop structure section LOOP, it becomes possible to know the analog voltage value of the node voltage V2 appearing at the U system output terminal of the nonvolatile memory section NVM. Since this point is as described above, a detailed description is omitted. Further, as described above, when it is desired to know the analog voltage value of the node voltage V1 appearing at the D system output terminal of the non-volatile memory unit NVM, the control opposite to the above may be performed.

  As described above, it is naturally possible to incorporate the test circuit unit TEST into a data holding device that needs to stop the clock signal when saving / restoring data.

<Data destruction prevention operation>
FIG. 44 is a timing chart for explaining the data destruction prevention operation at the time of power on / off. From the top, the power voltage VDD, the external clock signal CP, the data signal D, the scan control signal SC, the scan data SD, External reset signal RN, external set signal SN, data holding control signal HS, control signal E1, sense amplifier enable signal SAE, U system F reset signal FRSTU, D system F reset signal FRSTD, first digital plate line PL1_D, first 2 digital plate lines PL2_D, U system first analog plate line PL1U_A, U system second analog plate line PL2U_A, D system first analog plate line PL1D_A, D system second analog plate line PL2D_A, U system analog Enable signal TESTU, analog enable signal TESTD the D line, the scan output data SO, and the output signal Q is depicted.

  As shown in this timing chart, in the data holding device according to the present invention, even when the driver (INV) for applying a voltage signal to the ferroelectric element malfunctions in a transient state such as when the power is turned on / off, Appropriate sequence control is performed between both ends of the dielectric element so as not to apply such a high voltage that the data stored in the nonvolatile storage unit NVM is destroyed. As a result, highly reliable nonvolatile storage is possible.

<Control circuit>
Next, for example, a control circuit that can be suitably used as means for controlling the data saving / restoring operation of the data holding device will be described.

  FIG. 46 is a block diagram illustrating a configuration example of the control circuit. The control circuit 10 of this configuration example includes a control unit 11, an internal clock generation unit 12, and a reset unit 13.

  The control unit 11 is a sequencer that operates in synchronization with the internal clock signal LCLK or the external clock signal EXCLK. The control unit 11 detects a specific signal pattern (pulse edge in this configuration example) included in the trigger signal TRIGGER and controls the control target circuit 20. Control signal NVCTL is generated. In addition to the trigger signal TRIGGER, the internal clock signal LCLK, and the external clock signal EXCLK, the control unit 11 includes an internal reset signal RSTN for initializing the control unit 11 and a test operation of the control unit 11. A scan path input signal SCIN and a scan path enable signal SCEN for execution, and a clock selection signal CSEL for selecting whether to operate in synchronization with the internal clock signal LCLK or the external clock signal EXCLK are input. . The control unit 11 outputs an internal clock generation enable signal LCLKEN and a scan path output signal SCOUT.

  The internal clock generation unit 12 starts generating the internal clock signal LCLK necessary for the operation of the control unit 11 when a pulse edge appears in the trigger signal TRIGGER, and at least the control unit 11 completes the generation process of the control signal NVCTL. The generation of the internal clock signal LCLK is continued until the internal clock signal LCLK is generated. That is, the internal clock generation unit 12 generates the internal clock LCLK only when it is necessary to operate the control unit 11. With such a configuration having the internal clock generation unit 12, it is not necessary to provide a clock supply source outside the control circuit 10, so that it is possible to contribute to a reduction in the number of parts in the set and a reduction in cost. Further, with the control circuit 10 of this configuration example, it is not necessary to operate the control unit 11 and the internal clock generation unit 12 unnecessarily, so the power consumption of the control circuit 10 (and thus the power consumption of the entire set) is reduced. It becomes possible to do.

  The reset unit 13 monitors the power supply voltage VDD and generates an internal reset signal RSTN for initializing the control unit 11 and the internal clock generation unit 12.

  FIG. 47 is a timing chart showing an example of the basic operation of the control circuit 10 by the internal clock signal LCLK. In order from the top, the trigger signal TRIGGER, the internal reset signal RSTN, the scan path enable signal SCEN, the clock selection signal CSEL, the external clock The signal EXCLK, the scan path input signal SCIN, the scan path output signal SCOUT, the internal clock generation enable signal LCLKEN, the internal clock signal LCLK, and the control signal NVCTL are depicted.

  In this operation example, the internal reset signal RSTN is always at a high level (reset release state), the scan path enable signal SCEN is always at a low level (scan path invalid state), and the clock selection signal CSEL is always at a low level. Level (internal clock signal selection state). In this operation example, the external clock signal EXCLK, the scan input signal SCIN, and the scan output signal SCOUT are all unquestioned.

  In the period (1) in which the trigger signal TRIGGER is maintained at the low level, the control unit 11 waits for an edge input of the trigger signal TRIGGER and the internal clock signal LCLK. At this time, the control signal NVCTL is maintained at a logic level for setting the control target circuit 20 in a standby state (WAIT), and the internal clock generation enable signal LCLKEN is maintained at a low level (internal clock generation invalid state). The standby state (WAIT) of the control target circuit 20 is a state in which the control target circuit 20 is not executing the process A or the process B described later, and the control target circuit 20 performs a process other than the process A or the process B. You may be running. Further, the internal clock generator 12 waits for an edge input of the trigger signal TRIGGER. At this time, the internal clock signal LCLK is maintained at a low level.

  In period (2), the internal clock generator 12 starts generating the internal clock signal LCLK when the trigger signal TRIGGER is raised to a high level, and the internal clock generation enable signal LCLKEN is lowered to a low level. Sometimes the generation of the internal clock signal LCLK is stopped. Control unit 11 generates control signal NVCTL in synchronization with internal clock signal LCLK. At this time, the control unit 11 recognizes that the trigger signal TRIGGER is at a high level, and generates a control signal NVCTL for causing the control target circuit 20 to execute a predetermined process A. Further, the control unit 11 receives the first pulse of the internal clock signal LCLK, raises the internal clock generation enable signal LCLKEN to a high level (internal clock generation enabled state), and after the sequence operation of the process A is completed, The generation enable signal LCLKEN is lowered to a low level.

  In the period (3) in which the trigger signal TRIGGER is maintained at a high level, the control unit 11 enters a state of waiting for an edge input of the trigger signal TRIGGER and the internal clock signal LCLK. At this time, the control signal NVCTL is maintained at a logic level for setting the control target circuit 20 in a standby state (WAIT), and the internal clock generation enable signal LCLKEN is maintained at a low level. Further, the internal clock generator 12 waits for an edge input of the trigger signal TRIGGER. At this time, the internal clock signal LCLK is maintained at a low level.

  In the period (4), the internal clock generator 12 starts generating the internal clock signal LCLK when the trigger signal TRIGGER falls to the low level, and the internal clock generation enable signal LCLKEN falls to the low level. Sometimes the generation of the internal clock signal LCLK is stopped. Control unit 11 generates control signal NVCTL in synchronization with internal clock signal LCLK. At this time, the control unit 12 recognizes that the trigger signal TRIGGER is at a low level, and generates a control signal NVCTL for causing the control target circuit 20 to execute a predetermined process B. The control unit 11 receives the first pulse of the internal clock signal LCLK, raises the internal clock generation enable signal LCLKEN to a high level, and after the sequence operation of the process B is completed, the control unit 11 sets the internal clock generation enable signal LCLKEN to a low level. To fall.

  In the period (5) in which the trigger signal TRIGGER is maintained at the low level, the control unit 11 enters a state of waiting for an edge input of the trigger signal TRIGGER and the internal clock signal LCLK. At this time, the control signal NVCTL is maintained at a logic level for setting the control target circuit 20 in a standby state (WAIT), and the internal clock generation enable signal LCLKEN is maintained at a low level. Further, the internal clock generator 12 waits for an edge input of the trigger signal TRIGGER. At this time, the internal clock signal LCLK is maintained at a low level.

  As described above, the control unit 11 generates the control signal NVCTL so as to cause the control target circuit 20 to execute different processes A and B according to the rise / fall of the pulse edge appearing in the trigger signal TRIGGER.

  Next, a case where the data save / restore operation of the data holding device is controlled using the control circuit 10 of this configuration example will be described. In this case, the loop structure unit LOOP, the nonvolatile memory unit NVM, the circuit separation unit SEP, and the like described above correspond to the control target circuit 20, and the F reset signal FRST, the control signals E1 and E2, the first plate line PL1, In addition, the second plate line PL2 or the like corresponds to the control signal NVCTL. The trigger signal TRIGGER can be generated by using a general-purpose external reset IC that monitors the power supply voltage VDD. For example, a system reset signal that is high when the power supply voltage VDD is higher than 90% of the standard value and low when it is lower than 90% may be used as the trigger signal TRIGGER.

  When the power supply voltage VDD exceeds 90% of the specified value due to power-on, the trigger signal TRIGGER becomes high level, and generation of the internal clock signal LCLK is started with the rising edge as a trigger. Then, in the control target circuit 20, data restoration processing (= processing A) according to the control signal NVCTL is performed. When the data restoration process is completed, the generation of the internal clock signal LCLK is stopped. Thereafter, a normal logic operation is performed in the control target circuit 20 while the power supply voltage VDD exceeds 90% of the specified value.

  When the power supply voltage VDD falls below 90% of the specified value due to power off, the trigger signal TRIGGER becomes low level, and generation of the internal clock signal LCLK is started with the falling edge as a trigger. Then, in the control target circuit 20, a data saving process (= process B) according to the control signal NVCTL is performed. When the data saving process is completed, the generation of the internal clock signal LCLK is stopped. Thereafter, while the power supply voltage VDD is below 90% of the specified value, the control target circuit 20 holds data by nonvolatile logic.

  FIG. 48 is a timing chart showing an example of the basic operation of the control circuit 10 using the external clock signal EXCLK. In order from the top, the trigger signal TRIGGER, the internal reset signal RSTN, the scan path enable signal SCEN, the clock selection signal CSEL, and the external clock signal. EXCLK, scan path input signal SCIN, scan path output signal SCOUT, internal clock generation enable signal LCLKEN, internal clock signal LCLK, and control signal NVCTL are depicted.

  In this operation example, the internal reset signal RSTN is always at a high level (reset release state), the scan path enable signal SCEN is always at a low level (scan path invalid state), and the clock selection signal CSEL is always high. Level (external clock signal selection state). Further, the internal clock generation enable signal LCLKEN is always at a low level (internal clock generation invalid state), and the external clock signal EXCLK is always input. In this operation example, the scan input signal SCIN and the scan output signal SCOUT are both unquestioned.

  In the period (1) in which the trigger signal TRIGGER is maintained at a low level, the control unit 11 enters an edge input waiting state for the trigger signal TRIGGER. At this time, the control signal NVCTL is maintained at a logic level for setting the control target circuit 20 in a standby state (WAIT). Further, the internal clock generator 12 waits for an edge input of the trigger signal TRIGGER. At this time, the internal clock signal LCLK is maintained at a low level.

  In the period (2), the internal clock generator 12 starts generating the internal clock signal LCLK when the trigger signal TRIGGER is raised to a high level. However, since the internal clock generation enable signal LCLKEN is always maintained at the low level, the generation operation of the internal clock signal LCLK is stopped without being continued. Control unit 11 generates control signal NVCTL in synchronization with external clock signal EXCLK. At this time, the control unit 11 recognizes that the trigger signal TRIGGER is at a high level, and generates a control signal NVCTL for causing the control target circuit 20 to execute the process A.

  In the period (3) in which the trigger signal TRIGGER is maintained at the high level, the control unit 11 enters a state of waiting for an edge input of the trigger signal TRIGGER. At this time, the control signal NVCTL is maintained at a logic level for setting the control target circuit 20 in a standby state (WAIT). Further, the internal clock generator 12 waits for an edge input of the trigger signal TRIGGER. At this time, the internal clock signal LCLK is maintained at a low level.

  In the period (4), the internal clock generator 12 starts generating the internal clock signal LCLK when the trigger signal TRIGGER falls to the low level. However, since the internal clock generation enable signal LCLKEN is always maintained at the low level, the generation operation of the internal clock signal LCLK is stopped without being continued. Control unit 11 generates control signal NVCTL in synchronization with external clock signal EXCLK. At this time, the control unit 11 recognizes that the trigger signal TRIGGER is at a low level, and generates a control signal NVCTL for causing the control target circuit 20 to execute the process B.

  In the period (5) in which the trigger signal TRIGGER is maintained at the low level, the control unit 11 enters a state of waiting for an edge input of the trigger signal TRIGGER. At this time, the control signal NVCTL is maintained at a logic level for setting the control target circuit 20 in a standby state (WAIT). Further, the internal clock generator 12 waits for an edge input of the trigger signal TRIGGER. At this time, the internal clock signal LCLK is maintained at a low level.

  As described above, the control circuit 10 of the present configuration example operates using the external clock signal EXCLK input from the outside in addition to the internal clock signal LCLK. By adopting such a configuration, it becomes possible to arbitrarily select the internal clock signal LCLK and the external clock signal EXCLK according to the user's application. In particular, in order to realize a test operation to be described later, it is an essential requirement to operate in synchronization with the external clock signal EXCLK.

  Further, when the external clock signal EXCLK is selected by the clock selection signal CSEL, the internal reset generation enable signal LCLKEN is always at a low level. Therefore, even if a pulse edge appears in the trigger signal TRIGGER, the internal clock signal LCLK Is not continuously generated. Therefore, it is possible to avoid power consumption of the internal clock generator 12.

  FIG. 49 is a timing chart showing an example of the test operation of the control circuit 10 using the external clock signal EXCLK. In order from the top, the trigger signal TRIGGER, the internal reset signal RSTN, the scan path enable signal SCEN, the clock selection signal CSEL, the external clock The signal EXCLK, the scan path input signal SCIN, the scan path output signal SCOUT, the internal clock generation enable signal LCLKEN, the internal clock signal LCLK, and the control signal NVCTL are depicted.

  In this operation example, the internal reset signal RSTN is always at a high level (reset release state), and the clock selection signal CSEL is always at a high level (external clock signal selection state). Further, the internal clock generation enable signal LCLKEN is always at a low level (internal clock generation invalid state), and the external clock signal EXCLK is always input.

  In the period (1) in which the scan path enable signal SCEN is maintained at the low level, the control unit 11 enters an edge input waiting state for the trigger signal TRIGGER. At this time, the control signal NVCTL is maintained at a logic level for setting the control target circuit 20 in a standby state (WAIT). Further, the internal clock generator 12 waits for an edge input of the trigger signal TRIGGER. At this time, the internal clock signal LCLK is maintained at a low level.

  In the period (2) in which the scan path enable signal SCEN is maintained at the high level, the control unit 11 performs a test operation using the scan path (the scan input signal SCIN and the scan output signal SCOUT are synchronized with the external clock signal EXCLK). Input / output). At this time, the control signal NVCTL is maintained at a logic level for setting the control target circuit 20 in a standby state (WAIT). That is, the control unit 11 has an operation mode (test mode) in which a constant value of the control signal NVCTL is output to the control target circuit 20 regardless of its internal state. With such a configuration, the control target circuit 20 does not operate unexpectedly during the test operation. When the trigger signal TRIGGER is raised to a high level during the test operation, the internal clock generator 12 starts generating the internal clock signal LCLK. However, since the internal clock generation enable signal LCLKEN is always maintained at the low level, the generation operation of the internal clock signal LCLK is stopped without being continued. Therefore, the internal clock generation unit 12 does not perform an unexpected operation during the test operation using the scan path.

  After the above test operation is completed, in the period (3) in which the scan path enable signal SCEN is maintained at the low level, the control unit 11 waits for an edge input of the trigger signal TRIGGER. At this time, the control signal NVCTL is maintained at a logic level for setting the control target circuit 20 in a standby state (WAIT). Further, the internal clock generator 12 waits for an edge input of the trigger signal TRIGGER. At this time, the internal clock signal LCLK is maintained at a low level.

  As described above, the control circuit 10 of this configuration example is provided with the test mode synchronized with the external clock signal EXCLK. With such a configuration, the test of the control circuit 10 can be performed under control synchronized with the external clock signal EXCLK, so that the internal clock generator 12 can be connected without reducing the testability of the control circuit 10. It becomes possible to introduce.

<Internal clock generator>
FIG. 50 is a block diagram illustrating a configuration example of the internal clock generation unit 12. The internal clock generation unit 12 of this configuration example includes a low-pass filter 121, a latch unit 122, a pulse generation unit 123, a clock generation unit 124, and an OR calculator 125.

  The low pass filter 121 removes a high frequency component (noise component) superimposed on the trigger signal TRIGGER and generates an element signal NA. With the configuration having such a low-pass filter 121, it is possible to reduce malfunctions caused by noise components. The low-pass filter 121 has a function of initializing its operation state in response to the internal reset signal RSTN.

  When the internal clock generation enable signal LCLKEN is at a low level (internal clock generation invalid state), the latch unit 122 passes the element signal NA as it is as the element signal NB, while the internal clock generation enable signal LCLKEN is at a high level (internal clock generation invalid state). In the generation valid state), the element signal NA at the time of the rising edge of the internal clock generation enable signal LCLKEN is latched and output as the element signal NB. That is, the latch unit 122 is used as a signal propagation control circuit that performs propagation control of the trigger signal TRIGGER in the internal clock generation unit 12. With the configuration having such a signal propagation control circuit, even if the pulse edge of the trigger signal TRIGGER arrives during the generation operation of the internal clock signal LCLK, there is no problem in the clock generation operation. Note that the latch unit 122 has a function of initializing its operation state in response to the internal reset signal RSTN. Further, in this configuration example, the configuration using the latch unit 122 is given as an example of the signal propagation control circuit. However, the configuration of the present invention is not limited to this, and is replaced with the above-described latch unit 122. Thus, an OR calculator that generates the element signal NB by the OR operation of the element signal NA and the internal clock generation enable signal LCLKEN may be used.

  The pulse generator 123 generates a one-shot pulse of the first internal clock signal LCLK1 every time a pulse edge of the element signal NB arrives. Further, depending on the circuit configuration of the clock generation unit 124, the pulse generation unit 123 outputs an element signal NC obtained by giving a predetermined delay to the element signal NB to the clock generation unit 124. Note that the pulse generation unit 123 has a function of initializing its operation state in accordance with the internal reset signal RSTN.

  The clock generator 124 receives the internal clock generation enable signal LCLKEN (or the element signal NC) and generates the second internal clock signal LCLK2. The clock generation unit 124 has a function of initializing its operation state in response to the internal reset signal RSTN.

  The logical sum calculator 125 performs a logical sum operation on the first internal clock signal LCLK1 and the second internal clock signal LCLK2 to generate the internal clock signal LCLK.

  FIG. 51 is a timing chart showing an example of the internal clock generation operation. In order from the top, the trigger signal TRIGGER, the element signals NA and NB, the first internal clock signal LCLK1, the second internal clock signal LCLK2, and the internal clock signal LCLK. The internal clock generation enable signal LCLKEN is depicted. In addition, the code | symbol (1) in a figure has shown that the internal clock generation part 12 is in the edge waiting state of the trigger signal TRIGGER, and a code | symbol (2) has the internal clock generation part 12 produced | generated the internal clock signal LCLK. Indicates that it is operating.

  First, the noise component included in the trigger signal TRIGGER is removed by the low-pass filter 121. The rising edge of the trigger signal TRIGGER is propagated to the latch unit 122 as the rising edge of the element signal NA, and further propagated to the pulse generation unit 123 as the rising edge of the element signal NB. Then, the pulse generator 123 generates a one-shot pulse of the first internal clock signal LCLK1 according to the rising edge of the element signal NB. As a result, the first pulse is raised in the internal clock signal LCLK, and the internal clock generation enable signal LCLKEN is set to the high level by the control unit 11. As a result, the latch unit 122 enters a state in which the element signal NA at the time when the rising edge of the internal clock generation enable signal LCLKEN arrives is latched and output as the element signal NB, and thereafter the trigger signal until the generation operation of the internal clock signal LCLK is completed. The TRIGGER pulse edge is ignored.

  On the other hand, the clock generator 124 continues to generate the second internal clock signal LCLK2 (and thus the internal clock signal LCLK) while the internal clock generation enable signal LCLKEN is at the high level. Thereafter, the control unit 11 sets the internal clock generation enable signal LCLKEN to a low level when receiving the last pulse necessary for the predetermined processing. As a result, the clock generation unit 124 stops generating the second internal clock signal LCLK2, and the latch unit 122 returns to the state of passing the element signal NA as the element signal NB, that is, the edge waiting state of the trigger signal TRIGGER. . Therefore, when the falling edge of the trigger signal TRIGGER appears thereafter, the internal clock signal LCLK is generated by the same operation as described above.

  Further, as shown in FIG. 52, during the generation operation of the internal clock signal LCLK corresponding to the rising edge of the trigger signal TRIGGER (that is, during the high level period of the internal clock generation enable signal LCLKEN), the fall of the trigger signal TRIGGER When the edge arrives and the trigger signal TRIGGER (and element signal NA) is maintained at the low level thereafter, the generation operation of the internal clock signal LCLK is completed and the internal clock generation enable signal LCLKEN is set to the low level. At the time of falling, a falling edge occurs in the element signal NB almost without delay. Therefore, after the generation operation of the internal clock signal LCLK corresponding to the rising edge of the trigger signal TRIGGER is completed, the generation operation of the internal clock signal LCLK corresponding to the falling edge of the trigger signal TRIGGER is performed with almost no interval. It will be.

<Low-pass filter>
53A is a circuit diagram showing a first configuration example of the low-pass filter 121. As shown in FIG. The low-pass filter 121 of this configuration example is a passive low-pass filter including a resistor 121a, a capacitor 121b, a Schmitt trigger 121c, an N-channel field effect transistor 121d, and an inverter 121e. Note that when the internal reset signal RSTN is at a low level, the transistor 121d is turned on, so that the capacitor 121b is discharged and the operating state of the low-pass filter 121 is initialized.

  FIG. 53B is a circuit diagram illustrating a second configuration example of the low-pass filter 121. The low-pass filter 121 of this configuration example has substantially the same configuration as that of the first configuration example, and includes a ferroelectric capacitor 121f having a large capacitance per unit area instead of the capacitor 121b. With such a configuration, it is possible to reduce the capacitor occupation area in the low-pass filter 121.

  FIG. 54A is a circuit diagram illustrating a third configuration example of the low-pass filter 121. The low-pass filter 121 of this configuration example is an active low-pass filter including an operational amplifier 121A, resistors 121B and 121C, a capacitor 121D, a Schmitt trigger 121E, an N-channel field effect transistor 121F, and an inverter 121G.

  FIG. 54B is a circuit diagram illustrating a fourth configuration example of the low-pass filter 121. The low-pass filter 121 of this configuration example has substantially the same configuration as that of the third configuration example, and includes a ferroelectric capacitor 121H having a large capacitance per unit area instead of the capacitor 121D. With such a configuration, it is possible to reduce the capacitor occupation area in the low-pass filter 121.

<Pulse generator>
FIG. 55 is a block diagram illustrating a configuration example of the pulse generation unit 123. The pulse generation unit 123 of this configuration example includes delay stages 123a and 123b and an exclusive OR calculator 123c. The delay stage 123a generates a component signal ND by giving a predetermined delay to the component signal NB. The delay stage 123b gives a predetermined delay to the element signal ND to generate the element signal NC. The exclusive OR calculator 123c generates the first internal clock signal LCLK1 by performing an exclusive OR operation of the element signal ND and the element signal NC.

  When the pulse edge of the element signal NB is propagated through the delay stages 123a and 123b, the logic levels of the element signal ND and the element signal NC temporarily become inconsistent, and a pulse is generated in the first internal clock signal LCLK1 (FIG. 56). That is, when the pulse edge of the element signal NB (and hence the trigger signal TRIGGER) is propagated to the pulse generator 123, a one-shot pulse is generated in the first internal clock signal LCLK1. Thus, if the configuration is such that the first internal clock signal LCLK1 is generated using the propagation delay of the pulse edge appearing in the element signal NB (and thus the trigger signal TRIGGER), the operation of generating the internal clock signal CLK is performed. No separate clock signal is required to start.

  The pulse width (frequency) of the first internal clock signal LCLK1 can be appropriately adjusted according to the number of connection stages (delay time) of the buffers forming the delay stages 123a and 123b. In addition, a logical product operator for performing a logical product operation of the buffer output signal and the internal reset signal RSTN is appropriately inserted in the delay stages 123a and 123b. With such a configuration, the operation state of the pulse generation unit 123 can be initialized by setting the internal reset signal RSTN to a low level.

<Clock generator>
FIG. 57 is a block diagram illustrating a first configuration example of the clock generation unit 124. The clock generation unit 124 of this configuration example includes n-stage pulse generation units 124a-1 to 124a-n and an OR operation unit 124b. The n-stage pulse generation units 124a-1 to 124a-n may have the same configuration as the previous pulse generation unit 123. As described above, when the second internal clock signal CLK2 is generated, if the multi-stage connection structure of the logic elements (here, n-stage pulse generation units 124a-1 to 124a-n) is used, the second internal clock signal CLK2 having the desired number of pulses is generated. The clock signal LCLK2 can be easily generated. The number of pulses n of the second internal clock signal LCLK2 is determined according to the number n of connection stages of the pulse generators 124a-1 to 124a-n. Therefore, it can be said that the pulse generation unit 124 of this configuration example is effective when the number of pulses of the internal clock signal LCLK necessary for the operation of the control unit 11 is small. The pulse width (frequency) of the second internal clock signal LCLK2 can be appropriately adjusted according to the number of connection stages (delay time) of the buffers forming the delay stage, as described above.

  FIG. 58 is a block diagram illustrating a second configuration example of the clock generation unit 124. The clock generation unit 124 of this configuration example includes a pulse generation unit 124c, an inverter 124d, and a selector 124e. The pulse generator 124 c has the same configuration as the previous pulse generator 123. That is, in the pulse generation unit 124c, when the logic level of the element signal S2 obtained by delaying the element signal S1 input from the selector 124e does not match the logic level of the element signal S3 obtained by further delaying the element signal S2. (See FIG. 59 for generating a pulse in the second internal clock signal LCLK2.) The inverter 124d generates an element signal S4 obtained by logically inverting the element signal S3. The selector 124e loops the element signal S4 as the element signal S1 when the internal clock generation enable signal LCLKEN is at the high level, and fixes the element signal S1 at the low level when the internal clock generation enable signal LCLKEN is at the low level. . As described above, when the second internal clock signal CLK2 is generated, the second internal clock signal LCLK2 having a desired number of pulses can be generated with a small circuit configuration by using the loop structure of the logic element.

  The pulse width (frequency) of the second internal clock signal LCLK2 can be appropriately adjusted according to the number of connection stages (delay time) of the buffers forming the delay stage of the pulse generator 124c. The number of pulses of the second internal clock signal LCLK2 is determined according to the high level period of the internal clock generation enable signal LCLKEN.

  The number of generated pulses of the second internal clock LCLK2 will be described in detail. When the internal clock generation enable signal LCLKEN falls (see <MODE1> in FIG. 59) triggered by the generation of an even-numbered (α-numbered) pulse in the second internal clock signal LCLK2. The element signal S1 (= element signal S4) is originally at the low level when the loop is interrupted by 124e (when the falling edge of the internal clock generation enable signal LCLKEN arrives). Therefore, even if the element signal S1 is fixed to the low level by the selector 124e, no pulse edge occurs in the element signal S1, and no additional pulse is generated in the second internal clock signal LCLK2. The number of generated pulses is even (α).

  On the other hand, when the internal clock generation enable signal LCLKEN is lowered triggered by the generation of an odd number (β generation) pulse in the second internal clock signal LCLK2 (see <MODE2> in FIG. 59). The element signal S1 (= element signal S4) is at the high level when the selector 124e cuts off the loop. Therefore, when the element signal S1 is fixed at the low level by the selector 124e, a pulse edge (falling edge) occurs in the element signal S1, and one additional pulse is generated in the second internal clock signal LCLK2. Therefore, the final number of generated pulses is an even number ((β + 1)).

  That is, the clock generation unit 124 of this configuration example can be applied when the desired number of pulses of the second internal clock signal LCLK2 is an even number or when the input of the additional pulse is not regarded as a problem in the control unit 11. .

  FIG. 60 is a block diagram illustrating a third configuration example of the clock generation unit 124. The clock generation unit 124 of this configuration example has substantially the same configuration as the second configuration example described above. However, when the internal clock generation enable signal LCLKEN is at a low level in the selector 124e, the element signal S1 is fixed at a low level. Instead, the element signal S3 is looped as the element signal S1. Also in the clock generation unit 124 of the third configuration example, the number of pulses of the second internal clock signal LCLK2 is determined according to the high level period of the internal clock generation enable signal LCLKEN, and the behavior thereof is the second configuration example described above. Is different.

  The number of generated pulses of the second internal clock LCLK2 will be described in detail. When the internal clock generation enable signal LCLKEN is lowered (see <MODE1> in FIG. 61) triggered by the generation of an even-numbered (α-numbered) pulse in the second internal clock signal LCLK2 (see <MODE1> in FIG. 61). The state is switched from the state where the level element signal S4 is looped as the element signal S1 to the state where the high level element signal S3 is looped as the element signal S1. Accordingly, a pulse edge (rising edge) occurs in the element signal S1, and one additional pulse is generated in the second internal clock signal LCLK2, so that the final number of generated pulses is an odd number ((α + 1)). Departure).

  On the other hand, when the internal clock generation enable signal LCLKEN is triggered by the generation of an odd number (β generation) pulse in the second internal clock signal LCLK2 (see <MODE2> in FIG. 61). The state in which the high level element signal S4 is looped as the element signal S1 is switched to the state in which the low level element signal S3 is looped as the element signal S1. Accordingly, a pulse edge (falling edge) occurs in the element signal S1, and one additional pulse is generated in the second internal clock signal LCLK2, so that the final number of generated pulses is an even number ((β + 1) ))).

  That is, the clock generation unit 124 of this configuration example can be applied without any problem even if the desired number of pulses of the second internal clock signal LCLK2 is an even number or an odd number.

<POLH circuit>
Next, for example, a power-on low hold circuit (hereinafter referred to as a power-on reset circuit that can be suitably used as a power-on reset circuit (such as the reset unit 13 described above) that generates a reset signal for initializing an electronic circuit when the power is turned off. Now, a detailed description will be given of a POLH [Power On Low Hold] circuit).

  The power-on reset circuit includes a period from when the power supply voltage VDD reaches the operable voltage of the CMOS circuit (a value determined by the threshold value of the MOS transistor, for example, 0.4 to 0.7 V) until the initialization of the CMOS circuit is completed. The reset signal is required to be switched to high level before the power supply voltage VDD reaches the actual operating voltage while keeping the reset signal at low level. Therefore, the conventional power-on reset circuit is configured to switch the logic level of the reset signal by comparing the power supply voltage VDD with a predetermined reference voltage Vref. However, in the conventional power-on reset circuit, it is necessary to use a comparator to compare the power supply voltage VDD and the reference voltage Vref, and there is a problem that a circuit area and power consumption are large.

  In searching for a solution to the above problem, the inventors of the present application do not necessarily need to compare the power supply voltage VDD and the reference voltage Vref in order to realize the characteristics required for the power-on reset circuit. As a result of intensive research, we have created the following POLH circuit.

  FIG. 62 is a circuit diagram showing a configuration example of the POLH circuit. The POLH circuit 30 of this configuration example includes an inverter 31, P-channel field effect transistors 32 and 33, an N-channel field effect transistor 34, a capacitor 35, and a buffer 36.

  The input end of the inverter 31 is connected to the input end of the input signal IN. The output terminal of the inverter 31 is connected to the gates of the transistors 32 and 34. The source of the transistor 32 is connected to the application terminal of the power supply voltage VDD. The drain of the transistor 32 is connected to the source and gate of the transistor 33. Each drain of the transistors 33 and 34 is connected to the output terminal of the output signal OUT via the buffer 36. The source of the transistor 34 is connected to the ground terminal. The capacitor 35 is connected between the input terminal of the buffer 36 and the ground terminal.

  That is, it can be said that the POLH circuit 30 of this configuration example has a configuration in which the diode-connected transistor 33 is inserted between the transistor 32 and the transistor 34 forming the buffer stage. Note that a diode may be used instead of the transistor 33.

  FIG. 63 is a diagram for explaining a first application example of the POLH circuit 30. In the first application example, the power supply voltage VDD is input as the input signal IN, and the reset signal RSTN is output as the output signal OUT. The node voltage net1 applied to the input terminal of the buffer 36 has a voltage value lower than the power supply voltage VDD by the forward drop voltage Vf of the transistor 33. Accordingly, when the power supply voltage VDD rises, there is a period in which the buffer 36 continues to output a low level even after the power supply voltage VDD reaches the operable voltage of the CMOS circuit. Therefore, this low level output period is used as the reset signal RSTN. By using it, it is possible to realize the characteristics required for the power-on reset circuit without using a comparator.

  In the low-level output period, the input terminal of the buffer 36 is in a high impedance state. In the POLH circuit 30 of this configuration example, the capacitor 35 is provided between the input terminal of the buffer 36 and the ground terminal. Therefore, the influence of external noise can be reduced and the reset signal RSTN can be kept at a low level. The low-level output period can be appropriately adjusted according to the number of stages of the diode-connected transistor 33 and the capacitance value of the capacitor 35.

  In addition, since the POLH circuit 30 of this configuration example operates as a normal buffer after the low-level output period has elapsed, various application examples can be considered besides inputting the power supply voltage VDD as the input signal IN. It is done.

  FIG. 64 is a diagram for explaining a second application example of the POLH circuit 30. In the second application example, the first reset signal RSTN1 generated by the electronic circuit is input as the input signal IN, and the second reset signal RSTN2 is output as the output signal OUT. That is, it can be said that the POLH circuit 30 is inserted on the signal transmission path of the first reset signal RSTN1. With such a configuration, when the power supply voltage VDD is raised, the second reset signal RSTN2 is set until the predetermined low level output period elapses without depending on the logic level of the first reset signal RSTN1. While maintaining the low level, after the low level output period has elapsed, the first reset signal RSTN1 is output as the second reset signal RSTN2, thereby enabling an arbitrary reset operation by the electronic circuit to be realized.

  FIG. 65 is a diagram for explaining a third application example of the POLH circuit 30. In the third application example, the reset control signal RSTN_CTRL generated by the electronic circuit is input as the input signal IN, and the reset signal RSTN for initializing the electronic circuit is output as the output signal OUT. When the power supply voltage VDD rises, the electronic circuit is in an operation indefinite state from when the power supply voltage VDD reaches the operable voltage of the electronic circuit until the initialization of the electronic circuit is completed, and the reset control signal RSTN_CTRL Becomes indefinite (see the hatched part in the figure). Thereafter, when the initialization of the electronic circuit is completed by the reset signal RSTN (low level) output from the POLH circuit 30, the reset control signal RSTN_CTRL is set to an initial value (high level). As described above, since the POLH circuit 30 operates as a buffer after the low level output period has elapsed, the reset control signal RSTN_CTRL is directly reflected as the reset signal RSTN. Thus, for example, after the processing of the electronic circuit is completed, the electronic circuit can initialize itself by lowering the reset signal RSTN to low level by lowering the reset control signal RSTN_CTRL to low level. It becomes possible.

  FIG. 66 is a diagram for explaining a fourth application example of the POLH circuit 30. In the fourth application example, a logical product signal RSTN2 of the first reset signal RSTN1 generated by the first electronic circuit and the reset control signal RSTN_CTRL generated by the second electronic circuit is input as the input signal IN. A reset signal RSTN3 for initializing the second electronic circuit is output as an output signal OUT. That is, it can be said that the fourth application example is a configuration in which the second application example and the third application example described above are combined. With such a configuration, as the reset operation of the second electronic circuit, a power-on reset at the rise of the power supply voltage VDD, an arbitrary reset by the first electronic circuit, and the second electronic circuit itself An arbitrary reset can be performed.

<Eighth Modification>
FIG. 67 is a circuit diagram showing an eighth modification of the data holding device according to the present invention. This modified example has substantially the same configuration as the fifth modified example (FIG. 26), but changes are made to the configuration of the nonvolatile storage unit NVM, the circuit separating unit SEP, and the test circuit unit TEST. And a power-on high hold circuit 40 (hereinafter referred to as a POHH [Power On High Hold] circuit 40) for generating a protection signal LRSTNL for protecting data stored in the nonvolatile storage unit NVM. It is characterized in that

  The nonvolatile memory unit NVM includes path switches S1a, S1b, S2a, and S2b instead of the transistors Q1a, Q1b, Q2a, and Q2b described above. By making such a change, it becomes possible to short-circuit both ends of the ferroelectric elements CL1a, CL1b, CL2a, and CL2b to protect the stored data.

  The nonvolatile memory unit NVM is turned on / off based on the protection signal LRSTNL input to each gate, and the ferroelectric elements CL1a, CL1b, CL2a, and CL2b are turned on when the data holding device is turned on / off. N-channel field effect transistors Q3a, Q3b, Q3c, Q4a, Q4b, and Q4c that short-circuit both ends to the ground terminal are included. By making such a change, it becomes possible to further strengthen the protection of stored data in combination with the short-circuit between both ends of the ferroelectric elements CL1a, CL1b, CL2a, and CL2b.

  The circuit separation unit SEP includes three-state negation OR circuits NOR1 and NOR2 instead of the above-described three-state inverters INV9 and INV10. The NOR circuit NOR1 and NOR2 output a NOR signal of the data stored in the loop structure unit LOOP and the protection signal LRSTNL. Further, the output terminals of the NOR circuit NOR1 and NOR2 are set to a high impedance state in accordance with the control signal E1.

  The test circuit unit TEST includes three-state negation OR circuits NOR3 to NOR6 instead of the above-described three-state inverters INV11 to INV14. The NOR circuits NOR3 and NOR4 output a NOR signal of the digital signal applied to the first digital plate line PL1_DN and the protection signal LRSTNL. The NOR circuit NOR5 and NOR6 output a negative OR signal of the digital signal applied to the second digital plate line PL2_DN and the protection signal LRSTNL. In addition, each of the output terminals of the NOR circuit NOR3 to NOR6 is set to a high impedance state in response to the inverted analog enable signal TESTUB of the U system or the inverted analog enable signal TESTDB of the D system.

<POHH circuit>
FIG. 68 is a circuit diagram showing a configuration example of the POHH circuit 40. The POHH circuit 40 of this configuration example includes a P-channel field effect transistor 41 and an N-channel field effect transistor 42.

  The source of the transistor 41 is connected to the application terminal of the power supply voltage VDD. Each drain of the transistors 41 and 42 is connected to the output terminal of the protection signal LRSTNL. The source of the transistor 42 is connected to the ground terminal. Each gate of the transistors 41 and 42 is connected to the input terminal of the internal reset signal LRSTN. That is, the basic circuit configuration of the POHH circuit 40 is the same as that of a general inverter stage.

  The POHH circuit 40 is required to ensure that the protection signal LRSTNL is at a high level even when the internal reset signal LRSTN is at a high level (VDD) when the power supply voltage VDD is raised.

  Therefore, the POHH circuit 40 of this configuration example is designed such that the on-resistance value RonP of the transistor 41 is smaller than the on-resistance value RonN of the transistor 42. As a specific design example, the gate width of the transistor 41 is designed to be about five times the gate width of the transistor 42. The gate length is the same for the transistor 41 and the transistor 42.

  By performing such a design, the power supply voltage VDD reaches a predetermined value even in a state where the power supply voltage VDD is applied to the gates of the transistors 41 and 42 (that is, the worst case when the power supply is turned on). In the transitional period up to this point, the current Ip flowing through the transistor 41 is larger than the current In flowing through the transistor 42 (see FIG. 69). Therefore, in the case of the POHH circuit 40 of the present configuration example, by appropriately designing the on-resistance values of the transistors 41 and 42, the internal reset signal LRSTN until the power supply voltage VDD reaches at least the operable voltage of the CMOS circuit. The protection signal LRSTNL can be held at a high level without depending on the logic level (see FIG. 70).

  Note that after the rise of the power supply voltage VDD is completed, the POHH circuit 40 operates as a normal inverter. Accordingly, when the stored data is protected when the power is turned off, the internal reset signal LRSTN is set to a low level so that the protection signal LRSTNL is set to a high level.

<Other variations>
The configuration of the present invention can be variously modified in addition to the above-described embodiment without departing from the gist of the invention. That is, the above-described embodiment is an example in all respects and should not be considered as limiting, and the technical scope of the present invention is not the description of the above-described embodiment, but the claims. It should be understood that all modifications that come within the meaning and range of equivalents of the claims are included.

  For example, in the above embodiment, the configuration using an inverter or a NAND operator as the logic gate forming the loop structure portion LOOP has been described as an example, but the configuration of the present invention is limited to this. It is also possible to use other logic gates such as a NOT OR operator.

  In addition, in FIG. 1 and the like, a configuration using a combination of inverters INV6 and INV7 and path switches SW3 and SW4 as components of a circuit isolation unit SEP that electrically isolates the loop structure unit LOOP and the nonvolatile storage unit NVM. Although the description has been given by way of example, the configuration of the present invention is not limited to this, and as illustrated in FIG. 7 and the like, as a component of the circuit separation unit SEP, three-state inverters INV6 ′ and INV7 '(Inverter capable of floating output) may be used.

  The point of the circuit separation unit SEP is that voltage can be prevented from being applied to the ferroelectric element during normal operation, and the configuration illustrated in the above embodiment (that is, the ferroelectric material during normal operation). In addition to the configuration in which the voltage applied to the element is kept constant, a configuration in which at least one of the voltage application electrodes of the ferroelectric element is kept in a floating state is conceivable. As a specific example, in FIG. 1, during normal operation, the first plate line PL1 and the second plate line PL2 may be in a floating state while the transistors Q1a, Q1b, Q2a, and Q2b are turned off. If the circuit configuration itself is to be changed, a new connection is made between the ferroelectric element and the extraction end of the node voltage V1 (V2), or between the ferroelectric element and the plate line PL1 (PL2). A transistor may be added and the on / off control may be performed.

  In addition, when the voltage applied to the ferroelectric element is kept constant during normal operation or data reading operation, the transistor connected between both ends of the ferroelectric element may be turned on. The voltage of the line is not necessarily low level.

  Further, in FIG. 1 and the like, a configuration in which the second power supply voltage VDD2 supplied to the nonvolatile storage unit NVM is higher in voltage level than the first power supply voltage VDD1 supplied to the loop structure unit LOOP will be described as an example. However, the configuration of the present invention is not limited to this, and a configuration in which the second power supply voltage VDD2 is lower than the first power supply voltage VDD1 is also conceivable.

  As described above, in the non-volatile logic technology, the ferroelectric element is driven when the power is turned off / on to save / restore the register data. Here, the nonvolatile logic technique is used for driving the ferroelectric element. If the voltage level can be lowered as much as possible, it is possible to reduce the power consumed when driving the ferroelectric element.

  For example, when the loop structure unit LOOP is driven by the first power supply voltage VDD1 of 3.3 [V], the nonvolatile memory unit NVM is driven using the second power supply voltage VDD2 of 1.5 [V]. Then, it is not necessary to consume unnecessarily large power when driving the ferroelectric element.

  As described above, when the loop structure portion LOOP is driven at a high voltage and the nonvolatile memory portion NVM is driven at a low voltage, the inverters INV6 and INV7 forming the circuit separation unit SEP have a level shifter function ( 2 and FIG. 8), it is possible to use a simple inverter that is driven by the second power supply voltage VDD2 lower than the first power supply voltage VDD1, as shown in FIG.

  Also, a person skilled in the art can easily conceive of obtaining a new configuration by arbitrarily combining the various embodiments described above. Of course, such a configuration is not limited to the present invention. Should be construed as belonging to the technical scope of

  The present invention is a useful technique for realizing non-volatility of a data holding device mounted on a logic operation circuit, a logic operation device, a processor such as a CPU, MPU, or DSP, or a portable device.

INV1 to INV5, INV5 ', INV10' Inverter INV6, INV7 Inverter (with level shift function)
INV6 ', INV7' Inverter (with level shift function, 3 states)
INV8, INV8 ', INV9 to INV14 Inverter (3 states)
SW1 to SW10 Path switch MUX1, MUX2, MUX3, MUX4 Multiplexer DeMUX1, DeMUX2 Demultiplexer Q1a, Q1b, Q2a, Q2b N-channel field effect transistors Q11a, Q12a,..., Q1ma N-channel field effect transistors Q11b, Q12, Q1mb N-channel field effect transistors Q21a, Q22a,..., Q2ma N-channel field effect transistors Q21b, Q22b,..., Q2mb N-channel field effect transistors CL1a, CL1b, CL2a, CL2b Ferroelectric elements CL11a, CL12a,. CL1ma ferroelectric elements CL11b, QL12b,..., CL1mb ferroelectric elements CL21a, CL22a,..., CL2ma ferroelectric elements CL21b CL22b,..., CL2mb Ferroelectric elements C1, C2 Capacitance elements NAND1-NAND5 NAND operator LOOP Loop structure unit NVM Non-volatile memory unit SEP Circuit isolation unit P1-P3 P-channel MOS field effect transistor N1-N3 N-channel Type MOS field effect transistor SRC set / reset controller SA sense amplifier (differential amplifier)
P1 to P4 P channel type field effect transistor N1 to N5 N channel type field effect transistor AND1, AND2 AND operation unit TEST Test circuit unit CPC clock pulse control unit NOR1 to NOR6 NOR operation unit (3 states)
Q3a, Q3b, Q3c N-channel field effect transistor Q4a, Q4b, Q4c N-channel field effect transistor S1a, S1b, S2a, S2b Pass switch 1 Arithmetic unit 2 Tester (sequencer)
REG1 to REGx registers (data holding device)
10 Control circuit 11 Control unit (sequencer)
12 internal clock generator 121 low-pass filter 121a resistor 121b capacitor 121c Schmitt trigger 121d N-channel field effect transistor 121e inverter 121f ferroelectric capacitor 121A operational amplifier 121B, C resistor 121D capacitor 121E Schmitt trigger 121F N-channel field effect transistor 121G inverter 121H Ferroelectric capacitor 122 Latch unit 123 Pulse generation unit 123a, b Delay stage 123c Exclusive OR operator 124 Clock generation unit 124a-1 to 124a-n Pulse generation unit 124b OR operation unit 124c Pulse generation unit 124d Inverter 124e Selector 125 OR operator 13 Reset unit 20 Control target circuit 30 Power on low hold circuit ( OLH circuit)
31 Inverter 32, 33 P-channel field effect transistor 34 N-channel field effect transistor 35 Capacitor 36 Buffer 40 Power-on high hold circuit (POHH circuit)
41 P-channel field effect transistor 42 N-channel field effect transistor

Claims (5)

  The first MOS transistor and the first MOS transistor have the same channel type and are connected in series with a diode-connected second MOS transistor, and the first MOS transistor has a different channel type and is connected in series with the second MOS transistor. A third MOS transistor connected between a power supply voltage application end side and a ground end side, and an input signal is input to the gates of the first MOS transistor and the third MOS transistor, and the second MOS transistor A reset circuit which outputs an output signal from a connection point between a transistor and the third MOS transistor.   The reset circuit according to claim 1, wherein a capacitor is connected between the connection point and the ground end side.   3. The reset circuit according to claim 1, wherein a first reset signal generated by an electronic circuit is input as the input signal, and a second reset signal is output as the output signal. 4. .   The reset control signal generated by an electronic circuit is input as the input signal, and a reset signal for initializing the electronic circuit is output as the output signal. 3. The reset circuit according to 2.   A logical operation signal of a first reset signal generated by the first electronic circuit and a reset control signal generated by the second electronic circuit is input as the input signal, and for initializing the second electronic circuit The reset circuit according to claim 1, wherein a reset signal is output as the output signal.

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