JPH07153259A - Power-on reset circuit, semiconductor storage and data processing system - Google Patents

Abstract

PURPOSE:To provide a technique for precisely resetting when power source is applied. CONSTITUTION:This device is provided with a first power-on reset circuit 60A for resetting an input buffer circuit 55A by supplying a first reset signal INT1 to the circuit 55A and a second power-on reset circuit 60B for resetting a register in a timing controller 55B after the output logic of the input buffer circuit 55A is decided by the resetting by the reset circuit 60A. Then, before the register in the timing controller 55B is reset, by deciding the output logic of the prestage circuit, the reset operation when power source is applied is performed precisely.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power-on / reset technique for performing a reset (power-on / reset) at the time of power-on of a circuit, for example, a technique effective when applied to a semiconductor memory device.

[0002]

2. Description of the Related Art For example, "LSI Handbook" No. 4 issued from Ohm Co., Ltd. on November 30, 1984
As described on page 86, in a semiconductor memory device, a timing generator for controlling operations for writing data to a memory cell array and reading data from the memory cell according to an external control signal, etc. Control system is provided. In such a control system, if the logical state of each part immediately after the power is turned on is uncertain, the subsequent operation will be hindered, so that it is automatically reset immediately after the power is turned on. . This reset is called a power-on reset or an initial reset, and is distinguished from the reset after the normal operation of the circuit is started.

[0003]

However, the present inventor has examined the conventional reset at the time of turning on the power supply, and when all the circuits are simultaneously reset by the pulse generated at the time of turning on the power supply, the input first stage system is Propagation to the subsequent stage circuit of the logic signal that is determined by resetting the circuit,
It has been found that there is a possibility that the latter-stage circuit may malfunction due to a timing mismatch with the reset of the latter-stage circuit. For example, in a circuit having a register, if the register is reset before the logic of the preceding circuit of the register is determined, after resetting the register,
It is conceivable that the output logic of the preceding stage circuit may change, and in such a case, the output of the register becomes an undesired logic, which may cause malfunction of the succeeding stage circuit.

An object of the present invention is to provide a technique for accurately performing a reset when the power is turned on.

Another object of the present invention is to provide a semiconductor memory device whose operation is stabilized by an accurate power-on reset.

Still another object of the present invention is to provide a data processing system including such a semiconductor memory device.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0008]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, the first reset means for resetting the input initial stage system circuit by supplying the pulse signal obtained by detecting the rise of the power supply voltage to the input initial stage system circuit, and the reset by the first reset means A power-on reset circuit is configured to include second reset means for resetting the latter-stage system circuit after the output logic of the input-first-stage system circuit is determined.

Further, the register is reset based on the pulse signal obtained by detecting the rise of the power supply voltage, and the logic circuit arranged in the preceding stage of the register is reset at a timing earlier than the reset timing of the register. A semiconductor memory device is configured to include a power-on reset circuit for the purpose.

Then, a first reset means for resetting the input first stage system circuit by supplying a pulse signal obtained by detecting the rise of the power supply voltage to the buffer circuit, and the input by the reset by the first reset means. The semiconductor memory device is provided with a power-on reset circuit including a second reset means for resetting the timing controller after the output logic of the first-stage system circuit is determined. At this time, when the register is included in the timing controller and the register is reset by the second reset means, the output logic of the logic circuit arranged in the previous stage of the register is determined before the reset of the register. Can be configured as.

Further, a data processing system is constituted by including the semiconductor memory device having the above structure and a processor which enables access to the semiconductor memory device.

[0013]

According to the above-mentioned means, the first reset means resets the input initial stage system circuit, and after the reset determines the output logic state of the input initial stage system circuit, the second reset means sets the Reset the subsequent circuit. Staggering the reset timing in this way achieves accurate reset operation at power-on.

When the semiconductor memory device includes a register, the power-on / reset circuit resets the register based on the pulse signal obtained by detecting the rise of the power supply voltage, and the reset timing of the register. The logic circuit arranged in the preceding stage of the register is reset at an early timing. This is
It eliminates undesired logic output after register reset and achieves accurate reset operation at power-on.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows the overall structure of a DRAM which is an embodiment of the present invention.

Although not particularly limited, the DRAM shown in FIG. 1 is formed on one semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique. 54
Is a memory cell array in which a plurality of dynamic memory cells are arranged in a matrix. Select terminals of the memory cells are connected to word lines in each row direction, and data input terminals of the memory cells are connected to complementary data lines in each column direction. Be combined. Each complementary data line is commonly connected to the complementary common data line via a Y selection switch circuit 57 including a plurality of column selection switches which are coupled to the complementary data line in a one-to-one relationship. Although not particularly limited, the address multiplex method is adopted, and the row and column address input signals are fetched from a common address terminal by shifting their timings. That is, X
An address multiplexer 51 is arranged in the preceding stage of the address latch and X decoder 52 and the Y address latch and Y decoder 56, and an address signal taken in through the address buffer 50 is converted into an X address latch and X decoder by the address multiplexer 51. 52 and Y address latch and Y decoder 56. To smoothly perform such address input, a row address strobe signal RAS * (* means low active or signal inversion) and a column address strobe signal CAS.
* Two kinds of clock signals are given from the outside. Since only one operation of reading or writing is possible in one memory cycle (one cycle of the row address strobe signal RAS *), the row address is changed to the column address strobe signal when the row address strobe signal RAS * falls. The column address is taken into the internal circuit at the time of the fall of CAS *, and it is possible to judge whether the relevant cycle is a write cycle or a read cycle depending on the state of the write enable signal WE *. The control unit 55 performs such determination and operation control of each unit. The control unit 55 is not particularly limited, but the row address strobe signal RAS *, the column address strobe signal CAS *, and the write enable signal WE *.
An input buffer circuit 55A for taking in various control signals such as from the outside of the chip, and a timing controller 55 for performing operation timing control of each part based on the various control signals taken in via the input buffer circuit 55A.
Including B and. In such a control unit 55, the input buffer circuit 55A is an input initial stage system circuit for various control signals, and the timing control circuit 55B is a latter stage system circuit coupled to the input initial stage system circuit 55A.

The word driver 53 drives the word line to the selection level based on the decoding of the X address latch and the X decoder arranged in the preceding stage. Then, the Y selection switch circuit 57 is driven based on the Y address latch and the decoded output of the Y decoder 56, thereby enabling data read or data write from the memory cell specified.

A sense amplifier circuit 59 is coupled to the memory cell array 54 so that the memory cell information is amplified by this sense amplifier. in this case,
The data input / output circuit 58 includes a main amplifier and the like,
The read data can be transmitted to the outside through the main amplifier.

In this embodiment, this embodiment D
A power-on / reset circuit 60 for resetting the control unit 55 when the power of the RAM is turned on is provided.
The power-on / reset circuit 60 resets the input buffer circuit 55A by supplying the first reset signal INT1 to the input buffer 55A, and the timing controller 55B receives the first reset signal INT1. The timing controller 55B is reset by supplying the 2 reset signal INT2. Here, the first reset signal INT1 is a pulse signal generated immediately after the power is turned on, and the second reset signal I
NT2 is a pulse signal generated later in time than the first reset signal INT1. The input buffer circuit 55A and the timing controller 5 are controlled by the two reset signals having a predetermined time difference.
By resetting each of 5B, the timing controller 55B is reset after the output logical state of the input buffer circuit 55A is determined.
Next, the detailed configuration of the power-on reset circuit 60 will be described.

FIG. 2 shows the relationship between the configuration of the controller 55 and the reset signal.

The input buffer circuit 55A is not particularly limited, but a NAND (nand) circuit 61 for taking in the row address strobe signal RAS *, a NAND circuit 63 for taking in the column address strobe signal CAS *, and a write enable. NA for capturing signal WE *
An ND circuit 65 is included. The NAND circuits 61, 63, 6
Inverters 62 and 6 are connected to the other input terminals of
The first reset signal INT1 is input via 4, 66. In this circuit configuration, when the first reset signal INT1 is temporarily asserted to the high level, the NAND circuits 61, 63, and 65 are inactivated to reset the input buffer circuit 55A. It has become.

Further, the above timing controller 55B
Is not particularly limited, but the input buffer circuit 55A is
Logic circuits 67, 68 and 69 for obtaining the predetermined logic by taking in the output signal of
Includes registers 70, 71, 72 for holding 8, 69. In this configuration, the registers 70, 71, 72 are reset by the second reset signal INT2.

Here, according to the prior art, the one-system power-on / reset signal generated when the power is turned on is supplied to each part at the same timing. In other words, the inverters 62, 64, 66 are provided. Since the reset signal applied to the registers 70, 71 and 72 has the same timing as the reset signal applied to the registers 70, 71 and 72, the propagation of the signal A determined by the reset of the input first stage and the registers 70 and 7
Due to the timing mismatch with the reset of 1,72, the internal signal B may not be in the desired logical state, which may cause the subsequent circuit to malfunction. However, in the present embodiment,
First generated by power-on reset circuit 60
A second reset signal INT2 delayed from the first reset signal INT1 after the reset signal INT1 is asserted to a high level and the input initial stage system circuit is reset.
By resetting the registers 70, 71, 72, the timing of the reset operation is optimized. That is, before resetting the registers 70, 71, 72, the reset operation is optimized by determining the logic state of the logic circuit arranged in the preceding stage to the desired logic state.

FIG. 3 shows the power-on reset circuit 6 described above.
A configuration example of 0 is shown.

As shown in FIG. 3, the power-on reset circuit 60 outputs the first power-on reset circuit 60A for generating the first reset signal INT1 and the first reset signal INT1 generated thereby. A second power-on reset circuit 60B for generating the second reset signal INT2 by delaying.

The first power-on reset circuit 60A
Is not particularly limited, but the p-channel type MOS transistors 81 and 82 and the n-channel type MOS transistor 82 are connected in series to each other.
An n-channel type MOS transistor 84 is connected in parallel to the transistor 82, an inverter 85 is coupled to a serial connection point (node N1) of the p-channel type MOS transistor 81 and the n-channel type MOS transistor 82, and an inverter 86 is provided at the subsequent stage thereof. Are arranged.

The voltage level of the high potential side power supply Vcc is shown in FIG.
As shown in (4), after the power is turned on, it rises sharply and eventually reaches a stable state.
In the rising period of the c level, the voltage level of the node N1 is increased by deepening the on-state of the p-channel type MOS transistors 80 and 81, and the n-channel type MOS transistor 84 is turned on in time, whereby the voltage level of the node N1 is changed. Be lowered. As a result, the first reset signal INT1 as shown in FIG. 4 is generated during the rising period of the high-potential-side power supply Vcc level. The first reset signal INT1 is generated only during the rising period of the high-potential-side power supply Vcc level,
As long as the power supply voltage is stable, it will never be generated again.

The second power-on / reset circuit 60B is basically composed of a delay circuit. That is, the inverter 87 for inverting the logic of the first reset signal INT1 is provided, and the delay stage is provided after the inverter 87. This delay stage has a plurality of 2-input NAs.
It is formed by coupling the ND circuit and the inverter. Although not particularly limited, an inverter 88 for inverting the output logic of the inverter 87 is provided, and the inverter 8 for inverting the logic output of the inverter 88 is provided.
9 is provided. N for obtaining the NAND logic between the logic output of the inverter 89 and the output of the inverter 87
An AND circuit 90 is provided, a NAND circuit 92 for inverting the output logic of this NAND circuit is provided, an inverter 91 for inverting the output logic of this NAND circuit 90 is provided, and the logic output of this inverter 91 is provided. And N to obtain the NAND logic of the logic output of the inverter 87
An AND circuit 92 is provided. An inverter 93 for inverting the output of the NAND circuit 92 is provided, and a NAND circuit 94 for obtaining a NAND logic between the output of the inverter 93 and the output of the inverter 87 is provided. The output of the NAND circuit 94 is inverted. An inverter 95 is provided and an inverter 96 for inverting its output is provided. A NOR circuit 9 for obtaining a NOR logic of the output of the inverter 96 and the output of the inverter 87.
7 is provided, and an inverter 9 for inverting its output
8 are provided. The output of the inverter 98 is used as the reset signal INT2.

According to the above embodiment, the following operational effects can be obtained.

By supplying the first reset signal INT1 obtained by detecting the rise of the power supply voltage to the input buffer circuit 55A as the input first stage system circuit, the circuit 55 is concerned.
A first power-on reset circuit 60A for resetting A, and a register 7 in the timing controller 55B after the output logic of the input buffer circuit 55A is fixed by the reset by the reset circuit 60A.
Second power-on to reset 0, 71, 72
By providing the reset circuit 60B, the registers 70, 71, 72 in the timing controller 55B are provided.
Since the output logic of the circuit at the preceding stage can be determined before the resetting, the reset operation at the time of turning on the power can be ensured.

Next, another embodiment will be described.

Although not particularly limited, if the dummy cycle is activated after the power supply voltage level is determined, this dummy cycle can be used. For example, in DRAM, the column address strobe signal CAS * is provided before the row address strobe signal RAS *.
When the refresh cycle is activated by asserting the low level, the basic pulse in the refresh cycle can be used as the reset signal.

That is, as shown in FIG. 5, the reset signal IN from the first power-on reset circuit 60A is input.
Flip-flop FF set based on T1 and reset based on the clock of the dummy cycle
Is provided and the reset signal DINT is obtained by delaying the output signal of the flip-flop FF. The flip-flop FF is a 2-input NAND circuit 122, 1
23 is connected. Such a flip-flop F
The reset signal INT1 from the first power-on / reset circuit 60A is transmitted to the set terminal S of F through the inverter 120, and the reset terminal R is
Dummy cycle clock D via inverter 121
CLK is transmitted. The flip-flop FF set by the reset signal INT1 is reset by the clock of the dummy cycle. A pulse signal is obtained from the flip-flop FF by the set and reset operations. Moreover, since the reset signal INT1 is generated only once during the rising period of the high-potential-side power supply Vcc,
The set operation of the flip-flop FF is correspondingly performed only once. In other words, 1 for power-on reset
A pulse can be generated.

The output terminal of the flip-flop FF has a delay circuit 125 and a 2-input NA via an inverter 124.
It is coupled to the ND circuit 127. The delay circuit 125 is
Although not particularly limited, a device formed by connecting a plurality of inverters in series is applied. The output signal of such a delay circuit is input to the NAND circuit 127 via the inverter 126 in the subsequent stage, whereby a signal obtained by delaying the output of the flip-flop FF is obtained. This delay signal is converted into a reset signal DINT by passing through the inverter 128, and as shown in FIG.
It is behind in timing with respect to NT1. Then, such a reset signal DINT is, for example, replaced by the reset signal INT2 from the second power-on reset circuit 60B shown in FIG.
It is supplied to 71, 72 and the like.

Even if a dummy cycle is used in addition to the pulse signal obtained by detecting the rise of the high potential side power source Vcc in this way, the same effect as that of the above embodiment can be obtained.

FIG. 6 shows a data processing system to which the semiconductor memory device according to the present invention is applied.

This system includes a CPU (central processing unit) 100, a DRAM control unit 103, an SRAM (static random access memory) 106, a ROM (read only memory) via a system bus 100.
105, peripheral device control unit 107, display system 110, etc.
By being communicatively coupled to each other,
It is configured as a computer system that performs predetermined data processing according to a predetermined program.

The CPU 101 is the logical core of the present system, and mainly addresses, information reading and writing, data operation, instruction sequence, interrupt acceptance, and information exchange between storage device and input / output device. It has a function of activating, etc., and is composed of various units such as an arithmetic control unit, a bus control unit, and a memory access control unit.

As the internal storage device, the DRAM 102 or SRAM controlled by the DRAM control unit 103 is used.
106, a backup control unit 104 for controlling the backup of the SRAM 106, and a ROM 105. The RAM 102 and the SRAM 106 are the CPU 10
Programs and data required for calculation and control in 1 are stored. Since the ROM 105 is read-only, it usually stores a program that does not need to be changed.

The peripheral device control section 107 is not particularly limited, but the external storage device 10 is exemplified by a magnetic storage device.
8 and a peripheral device such as an input device such as a keyboard (KB) as an interface.

The display system 110 is a VRAM (video.
Random access memory) and its control circuit, and the display data transferred via the system bus 100 is output to the display device 112 in synchronization with the CRT display device 112. Further, a power supply unit 111 is provided, and various voltages generated here are supplied to each unit of the present system.

Here, the DRAM according to the above-described embodiment is applied to the DRAM 102 which is a storage means accessible by the CPU 101. That is, as shown in FIG. 1, the function of resetting the circuit 55A by supplying the first reset signal INT1 obtained by detecting the rising of the power supply voltage to the input buffer circuit 55A, and the function of resetting the circuit 55A. The input buffer circuit 55
The semiconductor memory device including the power-on reset circuit 60 having a function of resetting the register in the timing controller 55B after the output logic of A is determined is applied to the DRAM 102 of FIG. As a result, the power-on / reset of the DRAM 102 is accurately performed, and the stable operation of the DRAM 102 is enabled. Therefore, stable operation of the entire system including the DRAM 102 can be expected.

The SRAM 106 and the VRAM 110A
Also, although the control signal input from the outside is different,
Like the DRAM shown in FIG. 1, a timing controller or control unit for generating operation timing signals for each unit is provided, and even in that case, the power-on / reset circuit 60 as described in the above embodiment is provided. Can be provided. Therefore, SRAM 106 and VRA
By providing the power-on / reset circuit 60 in the M110A, the power-on / reset of each memory can be accurately performed, which is effective in achieving stable operation of the entire system.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and needless to say, various modifications can be made without departing from the scope of the invention. Yes.

For example, in the above embodiment, the output signal INT1 of the first power-on reset circuit 60A is supplied to the input terminal of the inverter 120 shown in FIG. 5, but the first power-on reset circuit 60A is also provided. 2 instead of the output signal INT1 of
The output signal INT2 of the reset circuit 60B may be supplied. Further, in the above-described embodiment, the power-on reset is performed by the pulse signals of two systems whose assert timings are different from each other, but the power-on reset of the circuit is performed by the pulse signals of three systems or more whose timings are different from each other. You may do it.

In the above description, the invention made mainly by the present inventor is the field of application behind which DRA is applied.
However, the present invention is not limited to this, and SRAMs, VRAMs, various semiconductor memory devices such as synchronous DRAMs and synchronous SRAMs, and logic circuits requiring power-on reset are also described. It can be applied to various semiconductor integrated circuits having.

The present invention can be applied on condition that it includes at least a logic circuit.

[0048]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, first reset means for resetting the input initial stage system circuit by supplying the pulse signal obtained by detecting the rise of the power supply voltage to the input first stage system circuit,
Since the reset timing can be shifted by providing the second reset means for resetting the subsequent-stage system circuit after the output logic of the input first-stage system circuit is determined by the reset by the first reset means, the power is turned on. The reset operation at the time can be made accurate.

In the case where a semiconductor memory device is configured with a power-on / reset circuit for resetting a logic circuit including a register when the power is turned on, a pulse signal obtained by detecting a rise of a power supply voltage is used. By resetting the register based on the above, and by providing a power-on reset circuit for resetting the logic circuit arranged in the preceding stage of the register at a timing earlier than the reset timing of the register, It is possible to eliminate the undesired logic output and to ensure the accuracy of the reset operation when the power is turned on, and thus the stable operation of the semiconductor memory device can be achieved.

In the semiconductor memory device including the power-on reset circuit, the power-on reset circuit supplies the pulse signal obtained by detecting the rising of the power supply voltage to the buffer circuit to input the first stage system circuit. And a second resetting means for resetting the timing controller after the output logic of the input initial stage system circuit is fixed by the resetting by the first resetting means. By configuring the power-on reset circuit,
As in the case described above, it is possible to eliminate the undesired logic output after the reset of the register and to ensure the reset operation at power-on, thereby achieving a stable operation of the semiconductor memory device. it can.

Further, by configuring the data processing system including the semiconductor memory device and the processor accessible to the semiconductor memory device, the reset operation at power-on of the semiconductor memory device can be accurately performed. The stable operation of the entire system can be achieved.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of a DRAM which is an embodiment of the present invention.

FIG. 2 is a block diagram of a configuration example of a control unit included in the DRAM.

FIG. 3 is a block diagram of a configuration example of a power-on reset circuit included in the DRAM.

FIG. 4 is an operation waveform diagram of a power-on reset circuit included in the DRAM.

FIG. 5 is a circuit diagram of another configuration example of the power-on reset circuit.

FIG. 6 is a configuration block diagram of a data processing system to which the DRAM is applied.

[Explanation of symbols]

 50 address buffer 51 address multiplexer 52 X address latch and X decoder 53 word driver 54 memory cell array 55A input buffer 55B timing controller 60 power-on reset circuit 60A first power-on reset circuit 60B second power-on reset circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masahiro Ogata 5-20-1 Kamimizumotocho, Kodaira-shi, Tokyo Hitate Cho El SII Engineering Co., Ltd.

Claims (7)

[Claims] 1. A power-on reset circuit for performing a reset at the time of power-on of a semiconductor integrated circuit including an input first-stage system circuit and a latter-stage system circuit arranged after the input first-stage system circuit. First reset means for resetting the input first stage system circuit by supplying a pulse signal obtained by detecting the rising edge of
A power-on reset circuit, comprising: second reset means for resetting the latter-stage related circuit after the output logic of the input first-stage related circuit is fixed by the reset by the first resetting means. 2. A semiconductor memory device having a power-on reset circuit for resetting a logic circuit including a register when power is turned on, wherein the register is based on a pulse signal obtained by detecting a rise of a power supply voltage. And a power-on reset circuit for resetting the logic circuit arranged in the previous stage of the register at a timing earlier than the reset timing of the register. 3. A memory cell array for storing data, a buffer circuit for receiving a control signal,
A timing controller for controlling a write operation to the memory cell and a data read operation from the memory according to a control signal fetched through the buffer circuit, and the buffer circuit and the timing controller when the power is turned on. In a semiconductor memory device including a power-on reset circuit for resetting, the power-on reset circuit supplies a pulse signal obtained by detecting a rise of a power supply voltage to the buffer circuit, thereby input first stage system circuit. And a second resetting means for resetting the timing controller after the output logic of the input initial stage system circuit is fixed by the resetting by the first resetting means. A semiconductor memory device characterized by the above. 4. The timing controller includes a register, and when the register is reset by the second reset means, the output logic of the logic circuit arranged in the preceding stage of the register is determined before the reset of the register. The semiconductor memory device according to claim 3, wherein the semiconductor memory device is formed as described above. 5. The semiconductor memory device according to claim 3, wherein the second reset means includes a delay circuit that delays a reset signal for resetting the buffer circuit to generate a reset signal for resetting the timing controller. . 6. The second reset means is a flip-flop that is set on the basis of a pulse signal obtained by detecting a rise of a power supply voltage and is reset by a clock of a dummy cycle, and an output signal of the flip-flop. 5. The semiconductor memory device according to claim 3, further comprising a delay circuit for delaying the. 7. A data processing system including the semiconductor memory device according to claim 2 and a processor capable of accessing the semiconductor memory device.