KR100583611B1 - Circuit and method for power-on reset - Google Patents

Abstract

Disclosed are a power-on reset circuit and a power-on reset method insensitive to changes in ambient temperature. The power-on reset circuit includes a first power-on reset section, a second power-on reset section, and an OR gate. The first power-on reset unit transitions at a first level of the power supply voltage at a first temperature, and transitions at a second level of the power supply voltage higher than a first level of the power supply voltage at a second temperature lower than the first temperature. Generates an on reset signal. The second power-on reset section generates a second power-on reset signal that transitions near the second level of the power supply voltage at the first temperature and transitions near the first level of the power supply voltage at the second temperature. The OR gate performs an OR operation on the first power-on reset signal and the second power-on reset signal. Therefore, the power-on reset circuit can reduce the fluctuation of the power supply voltage to which the power-on reset signal transitions even when the ambient temperature and the process condition of the semiconductor device change.

Description

Power-on reset circuit and power-on reset method {CIRCUIT AND METHOD FOR POWER-ON RESET}

1 is a view showing an example of a power-on reset circuit according to the prior art.

FIG. 2 is a graph showing an output waveform of the conventional power-on reset circuit shown in FIG. 1 at high and low temperatures.

3 is a circuit diagram illustrating a power-on reset circuit according to a first embodiment of the present invention.

4 is a diagram illustrating an example of a first power-on reset unit in the power-on reset circuit of FIG. 3.

FIG. 5 is a diagram illustrating an example of a second power-on reset unit in the power-on reset circuit of FIG. 3.

FIG. 6A illustrates an output waveform of the first power-on reset unit illustrated in FIG. 4.

FIG. 6B is a diagram illustrating an output waveform of the second power-on reset unit illustrated in FIG. 5.

FIG. 6C is a diagram illustrating an output waveform of the power-on reset circuit shown in FIG. 3.

7 is a circuit diagram illustrating a power-on reset circuit according to a second embodiment of the present invention.

FIG. 8A is a diagram illustrating an output waveform of a first power-on reset unit in the power-on reset circuit shown in FIG. 7.

FIG. 8B is a diagram illustrating an output waveform of a second power-on reset unit in the power-on reset circuit shown in FIG. 7.

FIG. 8C is a diagram illustrating an output waveform of the power-on reset circuit shown in FIG. 7.

Explanation of symbols on the main parts of the drawings

100: first power-on reset unit

110, 210: Voltage divider

120, 220: first amplifier

130, 230: second amplifier

140, 240: buffer

200: second power-on reset unit

The present invention relates to a power-on reset circuit and a power-on reset method, and more particularly, to a power-on reset circuit and a power-on reset method insensitive to ambient temperature.

In general, a complementary metal oxide semiconductor (CMOS) semiconductor device includes a power-on reset circuit. The power-on reset circuit has a function of activating circuits such as a latch circuit, a flip-flop, and the like in the semiconductor device after the power supply voltage supplied to the inside of the semiconductor device is stabilized. The power-on reset circuit generates a power-on reset signal that transitions to a "high" level when the power supply voltage supplied to the inside of the semiconductor device reaches a preset value after power-on.

Recently, with the development of electronic devices operating using a low power supply voltage, the design of a power-on reset circuit for a semiconductor device operating at a low power supply voltage has emerged as an important problem.

1 is a view showing an example of a power-on reset circuit according to the prior art, Figure 2 is a graph showing the output waveform of the conventional power-on reset circuit shown in Figure 1 at high and low temperatures. The power-on reset circuit of FIG. 1 is disclosed in Korean Patent Laid-Open No. 2004-0031861 filed by the applicant of the present invention. Referring to FIG. 1, a power-on reset circuit includes a voltage divider 10, a first amplifier 20, and a second amplifier 30.

The voltage divider 10 including the resistors R1 and R2 adjusts the value of the power supply voltage VDD to which the power-on reset signal POR transitions. The voltage divided by the voltage divider 10 is amplified and inverted by the first amplifier 20. The output voltage AOUT of the first amplifier 20 is amplified and inverted by the second amplifier 30 and output as a power-on reset signal POR.

However, when the ambient temperature of the semiconductor device is low and high, the value of the power supply voltage VDD to which the power-on reset signal POR transitions may vary. Referring to FIG. 2, the power supply voltage VDD to which the power-on reset signal PORH transitions when the ambient temperature is high is higher than the power supply voltage VDD to which the power-on reset signal PORL transitions when the ambient temperature is low. Can be low. Unlike the graph shown in FIG. 2, the power supply voltage transitioned by the power-on reset signal when the ambient temperature is high may be higher than the power supply voltage transitioned by the power-on reset signal when the ambient temperature is low.

Therefore, there is a need for a power-on reset circuit having a small variation in the value of the power supply voltage to which the power-on reset signal transitions even when the ambient temperature of the semiconductor device changes. In particular, in semiconductor devices operating at a low power supply voltage, the margin of the operating voltage is not so great, so it is necessary to design a power-on reset circuit insensitive to changes in ambient temperature.

An object of the present invention for solving the above problems is to provide a power-on reset circuit that can reduce the variation in the value of the power supply voltage transitioned by the power-on reset signal even if the ambient temperature of the semiconductor device changes.

Another object of the present invention is to provide a power-on reset method capable of reducing the variation in the value of the power supply voltage to which the power-on reset signal transitions even when the ambient temperature of the semiconductor device changes.

In order to achieve the above object, the power-on reset circuit according to the first embodiment of the present invention includes a first power-on reset unit, a second power-on reset unit, and an OR gate.

The first power-on reset unit transitions at a first level of the power supply voltage at a first temperature, and transitions at a second level of the power supply voltage higher than the first level of the power supply voltage at a second temperature lower than the first temperature. Generates a first power-on reset signal.

The second power-on reset unit generates a second power-on reset signal that transitions near the second level of the power supply voltage at a first temperature and transitions near the first level of the power supply voltage at the second temperature. Let's do it.

The OR gate performs an OR operation on the first power-on reset signal and the second power-on reset signal and generates a third power-on reset signal.

In the power-on reset circuit according to the first embodiment of the present invention, a time point at which the first power-on reset signal transitions at the first temperature is a time point at which the second power-on reset signal transitions at the second temperature. It may be designed to be substantially the same as.

In the power-on reset circuit according to the first embodiment of the present invention, the third power-on reset signal can be activated at about the same time at the first temperature or at the second temperature.

In the power-on reset circuit according to the first embodiment of the present invention, when the first power-on reset signal transitions at the first temperature, the third power-on reset signal transitions, and at the second temperature, The third power-on reset signal may transition when the second power-on reset signal transitions.

The power-on reset circuit according to the second embodiment of the present invention includes a first power-on reset section, a second power-on reset section, and an AND gate.

The first power-on reset unit transitions at a first level of the power supply voltage at a first temperature, and at a second level of the power supply voltage higher than the first level of the power supply voltage at a second temperature lower than the first temperature. Transitioning generates a first power-on reset signal.

The second power-on reset unit generates a second power-on reset signal that transitions near the second level of the power supply voltage at a first temperature and transitions near the first level of the power supply voltage at the second temperature. Let's do it.

The AND gate performs an AND operation on the first power-on reset signal and the second power-on reset signal and generates a third power-on reset signal.

In the power-on reset circuit according to the second embodiment of the present invention, a time point at which the first power-on reset signal transitions at the second temperature is a time point at which the second power-on reset signal transitions at the first temperature. It may be designed to be substantially the same as.

In the power-on reset circuit according to the second embodiment of the present invention, the third power-on reset signal can be activated at the same time at the first temperature or at the second temperature.

In the power-on reset circuit according to the second embodiment of the present invention, when the first power-on reset signal transitions at the second temperature, the third power-on reset signal transitions, and at the first temperature The third power-on reset signal may transition when the second power-on reset signal transitions.

The power-on reset method according to the first embodiment of the present invention transitions at a first level of a power supply voltage at a first temperature and is higher than the first level of the power supply voltage at a second temperature lower than the first temperature. Generating a first power-on reset signal that transitions at a second level of the power supply voltage; Generating a second power-on reset signal that transitions near the second level of the power supply voltage at a first temperature and transitions near the first level of the power supply voltage at the second temperature; And performing an OR operation on the first power-on reset signal and the second power-on reset signal and generating a third power-on reset signal.

In the power-on reset method according to the first embodiment of the present invention, a time point at which the first power-on reset signal transitions at the first temperature is a time point at which the second power-on reset signal transitions at the second temperature. And may be substantially the same as

In the power-on reset method according to the first embodiment of the present invention, the third power-on reset signal can be activated at about the same time at the first temperature or at the second temperature.

In the power-on reset method according to the first embodiment of the present invention, the third power-on reset signal transitions when the first power-on reset signal transitions at the first temperature, and at the second temperature. The third power-on reset signal may transition when the second power-on reset signal transitions.

The power-on reset method according to the second embodiment of the present invention transitions at a first level of a power supply voltage at a first temperature and is higher than the first level of the power supply voltage at a second temperature lower than the first temperature. Generating a first power-on reset signal that transitions at a second level of the power supply voltage; Generating a second power-on reset signal that transitions near the second level of the power supply voltage at a first temperature and transitions near the first level of the power supply voltage at the second temperature; And performing an AND operation on the first power-on reset signal and the second power-on reset signal and generating a third power-on reset signal.

In the power-on reset method according to the second embodiment of the present invention, a time point at which the first power-on reset signal transitions at the second temperature is a time point at which the second power-on reset signal transitions at the first temperature. And may be substantially the same as

In the power-on reset method according to the second embodiment of the present invention, the third power-on reset signal can be activated at about the same time as at the first temperature or at the second temperature.

In the power-on reset method according to the second embodiment of the present invention, when the first power-on reset signal transitions at the second temperature, the third power-on reset signal transitions, and at the first temperature The third power-on reset signal may transition when the second power-on reset signal transitions.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

3 is a circuit diagram illustrating a power-on reset circuit according to a first embodiment of the present invention. Referring to FIG. 3, the power-on reset circuit includes a first power-on reset unit 100, a second power-on reset unit 200, a NOR gate 300, and an inverter 350.

The first power-on reset unit 100 transitions at the first level of the power supply voltage at the first temperature, and transitions at the second level of the power supply voltage higher than the first level of the power supply voltage at the second temperature lower than the first temperature. Generates a first power-on reset signal VCCH1. Wherein the first temperature may be a high temperature, for example 100 ℃, the second temperature may be a low temperature, for example -5 ℃. The second power-on reset unit 200 transitions near the second level of the power supply voltage at the first temperature and transitions near the first level of the power supply voltage at the second temperature. The second power-on reset signal VCCH2 Generates. The NOR gate 300 performs a non-logical operation on the first power-on reset signal VCCH1 and the second power-on reset signal VCCH2. The inverter 350 inverts the output signal of the NOR gate 300.

The power-on reset circuit includes a time taken for the first power-on reset signal VCCH1 to transition at a first temperature after the power supply voltage is powered on and a second power-on reset signal VCCH2 at a second temperature. The time it takes to transition is substantially the same.

4 illustrates an example of the first power-on reset unit 100 in the power-on reset circuit of FIG. 3. Referring to FIG. 4, the first power-on reset unit 100 includes a voltage divider 110, a first amplifier 120, a second amplifier 130, a buffer 140, and an inverter 150. .

The voltage divider 110 divides the power supply voltage and outputs the divided voltage to the first node N1. The first amplifier 120 amplifies the voltage signal of the first node N1 and outputs it to the second node N2. The second amplifier 120 amplifies the voltage signal of the second node N2 and outputs it to the third node. The buffer 140 inverts the voltage signal of the third node N3 and increases the current driving capability. The inverter 150 inverts the output signal of the buffer 140 and outputs the first power-on reset signal VCCH1.

The voltage divider 110 includes a first resistor R4, a second resistor R5, a third resistor R6, and an NMOS transistor MN5. The first resistor R4 is connected between the power supply voltage VDD and the first node N1. The second resistor R5 is connected between the first node N1 and the ground voltage GND. The third resistor R6 is connected between the second resistor R5 and the ground voltage GND. The NMOS transistor MN5 is connected across the third resistor R6 and controlled by the output signal of the buffer 140.

The first amplifier 120 includes an NMOS transistor MN3, a resistor R7, a resistor R8, and a PMOS transistor MP2.

The NMOS transistor MN3 has a gate connected to the first node N1, a source connected to the ground voltage GND, and a drain connected to the second node N2. The resistor R7 has a first terminal connected to the drain of the NMOS transistor MN3, and the resistor R8 is connected to the power supply voltage VDD and the second terminal of the resistor R7. The PMOS transistor MP2 is connected across the resistor R8 and controlled by the output signal of the inverter 150.

The second amplifier 130 includes a PMOS transistor MP3, an NMOS transistor MN4, a resistor R9, and an NMOS transistor MN6.

The PMOS transistor MP3 has a source connected to the power supply voltage VDD, a drain connected to the third node N3, and a gate connected to the second node N2. The NMOS transistor MN4 has a drain connected to the third node N3 and a gate connected to the second node N2. The resistor R9 is connected between the source of the NMOS transistor MN4 and the ground voltage GND. The NMOS transistor MN6 is connected across the resistor R9 and controlled by the output signal of the buffer 140.

The buffer 140 is composed of an odd number of inverters 141, 142, and 143.

Hereinafter, the operation of the first power-on reset unit 100 shown in FIG. 4 will be described.

When the power supply voltage VDD starts to increase from 0V at first, the voltage of the node N2 increases through the resistors R7 and R8. When the NMOS transistor MN4 is turned on by the voltage of the node N2, the node N3 becomes logic "low", and the output signal of the buffer 140 becomes logic "high". In addition, the first power-on reset signal VCCH1, which is an output signal of the inverter 150, becomes a logic “low”. When the power supply voltage VDD increases further and the NMOS transistor MN3 is turned on by the voltage of the node N1, the node N2 becomes a logic "low". When the PMOS transistor MP3 is turned on by the voltage of the node N2, the node N3 becomes logic "high" and the output signal of the buffer 140 becomes logic "low". The first power-on reset signal VCCH1, which is an output signal of the inverter 150, becomes a logic " high ". When the first power-on reset signal VCCH1 becomes logic " high ", circuits such as latch circuits, flip-flops, etc. in the semiconductor integrated circuit are activated. Since the power supply voltage VDD is expressed by the formula VDD = V (N1) x (R4 + R5 + R6) / (R5 + R6), the first power-on reset signal VCCH1 transitions to a logic " high " The value of the power supply voltage is largely determined by the values of the resistors R4, R5 and R6.

The NMOS transistors NM5 and MN6 and the PMOS transistor MP2 function to allow the output signal of the first power-on reset unit 100 to have hysteresis. The output signal of the buffer 140, that is, the inverted signal of the first power-on reset signal VCCH1 is fed back to the gates of the NMOS transistors MN5 and MN6, and the first power-on reset signal VCCH1 is fed back into the PMOS. The hysteresis characteristic is generated by feeding back to the transistor MP2. Therefore, the value of the power supply voltage to which the first power-on reset signal VCCH1 transitions is lower than that of the power-on, so that even if a power dip or the like occurs in the power supply voltage VDD, the first power- Incorrect variation of the on reset signal VCCH1 can be prevented.

Operation characteristics of the first power-on reset unit 100 according to temperature change are mainly determined by the first amplifier 120 and the voltage divider 110. Accordingly, the first power-on having different characteristics at high and low temperatures by appropriately adjusting the size (width / length: W / L) of the NMOS transistor MN3 and the values of the resistors R4, R5, R6, R7, and R8. The reset signal VCCH1 can be obtained.

FIG. 5 shows an example of the second power-on reset unit 200 in the power-on reset circuit of FIG. 3, and the circuit configuration is the same as that of the first power-on reset unit 100 shown in FIG. 4. Do. However, in order to have a temperature characteristic opposite to that of the first power-on reset unit 100 shown in FIG. 4, the value of each element in the second power-on reset unit 200 shown in FIG. It is designed to be different from the values of the corresponding elements in the one power-on reset unit 100. In particular, the values of the elements in the voltage divider 210 and the values of the elements in the first amplifier 220 greatly affect the temperature characteristics of the circuit. Accordingly, the second power-on reset unit 200 having a temperature characteristic opposite to that of the first power-on reset unit 100 may be designed by adjusting values of these devices.

Referring to FIG. 5, the second power-on reset unit 200 includes a voltage divider 210, a first amplifier 220, a second amplifier 230, a buffer 240, and an inverter 250. .

The voltage divider 210 divides the power supply voltage and outputs the divided voltage to the first node N1. The first amplifier 220 amplifies the voltage signal of the first node N1 and outputs it to the second node N2. The second amplifier 220 amplifies the voltage signal of the second node N2 and outputs it to the third node N3. The buffer 240 inverts the voltage signal of the third node N3 and increases the current driving capability. The inverter 250 inverts the output signal of the buffer 240 and outputs the second power-on reset signal VCCH2.

Since the operation of the second power-on reset unit 200 shown in FIG. 5 is substantially the same as the operation of the first power-on reset unit 200 shown in FIG. 4, the description thereof is omitted here.

FIG. 6A illustrates an output waveform of the first power-on reset unit illustrated in FIG. 4, and FIG. 6B illustrates an output waveform of the second power-on reset unit illustrated in FIG. 5. FIG. 6C illustrates a time when the first power-on reset signal VCCH1 transitions from the high temperature HOT TEMP in the power-on reset circuit of FIG. 3 at the low temperature COLD TEMP. A diagram showing an output waveform of a power-on reset circuit when designed to be substantially the same as the time of transition.

3 to 6C, the operation of the power-on reset circuit according to the first embodiment of the present invention will be described.

 6A to 6C are waveform diagrams showing simulation results under the following conditions.

<Simulation condition>

1) High temperature (HOT TEMP) = 100 ℃, Low temperature (COLD TEMP) = -5 ℃

1) First power-on reset unit of FIG.

   W / L = 2/1 of MN3, R4 = 165 ㏀, R5 = 200 ㏀, R7 = 300 ㏀

   R6 = R8 = 0 Ω (short), MN5 and MP2 are not connected to the circuit.

2) second power-on reset unit of FIG.

   W / L = 2/6 of MN13, R14 = 40 μs, R15 = 800 μs, R17 = 100 μs

   R16 = R18 = 0 Ω (short), MN15 and MP12 are not connected to the circuit.

Referring to FIG. 6A, the power voltage VDD to which the first power-on reset signal VCCH1 transitions at a high temperature HOT TEMP, that is, 100 ° C., is a low temperature COLD TEMP, that is, a first power − at −5 ° C. FIG. The on reset signal VCCH1 is lower than the power supply voltage VDD to which it transitions. In addition, it can be seen that the first power-on reset signal VCCH1 transitions faster at a high temperature HOT TEMP than at a low temperature COLD TEMP. In the example of FIG. 6A, the power supply voltage VDD to which the first power-on reset signal VCCH1 transitions at high temperature HOT TEMP is 0.668V, and the first power-on reset signal VCCH1 at low temperature COLD TEMP. Power supply voltage VDD transitions to 0.720V.

Referring to FIG. 6B, the power supply voltage VDD to which the first power-on reset signal VCCH1 transitions at a high temperature HOT TEMP, that is, 100 ° C., is a low temperature COLD TEMP, that is, a first power − at −5 ° C. FIG. The on reset signal VCCH1 is higher than the power supply voltage VDD to which it transitions. Also, it can be seen that the first power-on reset signal VCCH1 transitions faster at low temperature COLD TEMP than at high temperature HOT TEMP. In the example of FIG. 6B, the power supply voltage VDD to which the first power-on reset signal VCCH1 transitions at high temperature HOT TEMP is 0.732V, and the first power-on reset signal VCCH1 at low temperature COLD TEMP. Power supply voltage (VDD) is 0.670V.

Referring to FIG. 6C, it can be seen that the power-on reset signal POR transitions at about the same time as at high temperature (HOT TEMP) or at low temperature (COLD TEMP). In the power-on reset circuit of FIG. 3, a time point at which the first power-on reset signal VCCH1 transitions at a high temperature HOT TEMP is a time point at which the second power-on reset signal VCCH2 transitions at a low temperature COLD TEMP. It is designed to be substantially the same as. In addition, in the power-on reset circuit of FIG. 3, the output signal of the first power-on reset signal VCCH1, which is an output signal of the first power-on reset unit 100, and the second power-on reset unit 200, is an output signal. The second power-on reset signal VCCH2 is logically outputted through the NOR gate 300 and the inverter 350.

Therefore, at a high temperature HOT TEMP, when the first power-on reset signal VCCH1, which is an output signal of the first power-on reset unit 100, transitions to a logic " high " The power-on reset signal POR, which is an output signal, transitions to logic “high”, and at a low temperature COLD TEMP, the second power-on reset signal VCCH2, which is an output signal of the second power-on reset unit 200, is output. Transitions to logic "high", the power-on reset signal POR, which is the output signal of the power-on reset circuit of FIG. 3, transitions to logic "high". In addition, in the power-on reset circuit of FIG. 3, when the first power-on reset signal VCCH1 transitions at a high temperature HOT TEMP, the second power-on reset signal VCCH2 transitions at a low temperature COLD TEMP. In this case, the power-on reset signal POR, which is the output signal of the power-on reset circuit of FIG. High ".

7 is a circuit diagram illustrating a power-on reset circuit according to a second embodiment of the present invention. Referring to FIG. 7, the power-on reset circuit includes a first power-on reset unit 100, a second power-on reset unit 200, a NAND gate 400, and an inverter 450. The first power-on reset unit 100 and the second power-on reset unit 200 in the power-on reset circuit of FIG. 7 may be formed of the first power-on reset unit shown in FIGS. 4 and 5, respectively. 100 and the same configuration as the second power-on reset unit 200.

The first power-on reset unit 100 transitions at the first level of the power supply voltage at the first temperature, and transitions at the second level of the power supply voltage higher than the first level of the power supply voltage at the second temperature lower than the first temperature. Generates a first power-on reset signal. Here, the first temperature may be a high temperature, for example 100 ° C., and the second temperature may be a low temperature, for example, −5 ° C. The second power-on reset unit 200 transitions near the second level of the power supply voltage at a first temperature and transitions near the first level of the power supply voltage at the second temperature. Generates. The NAND gate 400 performs a non-logical operation on the first power-on reset signal VCCH1 and the second power-on reset signal VCCH2. The inverter 450 inverts the output signal of the NAND gate 400.

In the power-on reset circuit according to the second embodiment of the present invention, a time taken for the first power-on reset signal VCCH1 to transition at a second temperature after the power supply voltage is turned on and at a second temperature at a first temperature The time taken for the power-on reset signal VCCH2 to transition is substantially the same.

The power-on reset circuit according to the second embodiment of the present invention shown in FIG. 7 is different from the power-on reset circuit according to the second embodiment of the present invention shown in FIG. 3. The first power-on reset signal VCCH1, which is an output signal of 100, and the second power-on reset signal VCCH2, which is an output signal of the second power-on reset unit 200, are converted to the NAND gate 400 and the inverter ( 450) to perform the AND operation.

FIG. 8A illustrates an output waveform of the first power-on reset unit in the power-on reset circuit shown in FIG. 7, and FIG. 8B illustrates an output waveform of the second power-on reset unit in the power-on reset circuit shown in FIG. 7. Indicates a waveform.

FIG. 8C illustrates the second power-on reset signal VCCH1 at the high temperature HOT TEMP when the first power-on reset signal VCCH1 transitions from the low temperature COLD TEMP within the power-on reset circuit of FIG. 3. Is a diagram showing an output waveform of a power-on reset circuit when it is designed to be substantially the same as the transition point.

 8A to 8C show simulation waveform diagrams when the values of the main elements in FIGS. 4 and 5 are the same as the values used in the first embodiment of the present invention. And, the simulation was carried out under the conditions of high temperature (HOT TEMP) is 100 ℃ and low temperature (COLD TEMP) -5 ℃.

7 to 8C, the operation of the power-on reset circuit according to the second embodiment of the present invention will be described.

Referring to FIG. 8A, the power supply voltage VDD to which the first power-on reset signal VCCH1 transitions at a high temperature HOT TEMP, that is, 100 ° C., is a low temperature COLD TEMP, that is, a first power − at −5 ° C. FIG. The on reset signal VCCH1 is lower than the power supply voltage VDD to which it transitions. In addition, it can be seen that the first power-on reset signal VCCH1 transitions faster at a high temperature HOT TEMP than at a low temperature COLD TEMP. In the example of FIG. 8A, the power supply voltage VDD to which the first power-on reset signal VCCH1 transitions at high temperature HOT TEMP is 0.674V, and the first power-on reset signal VCCH1 at low temperature COLD TEMP. Power supply voltage VDD transitions to 0.745V.

Referring to FIG. 8B, the power supply voltage VDD to which the first power-on reset signal VCCH1 transitions at a high temperature HOT TEMP, that is, 100 ° C., is a low temperature COLD TEMP, that is, a first power − at −5 ° C. FIG. The on reset signal VCCH1 is higher than the power supply voltage VDD to which it transitions. Also, it can be seen that the first power-on reset signal VCCH1 transitions faster at low temperature COLD TEMP than at high temperature HOT TEMP. In the example of FIG. 8A, the power supply voltage VDD to which the first power-on reset signal VCCH1 transitions at high temperature HOT TEMP is 0.745V, and the first power-on reset signal VCCH1 at low temperature COLD TEMP. Power supply voltage VDD transitions to 0.674V.

Referring to FIG. 8C, it can be seen that the power-on reset signal POR transitions at about the same time as at high temperature (HOT TEMP) or at low temperature (COLD TEMP). The power-on reset circuit of FIG. 7 has a time point at which the first power-on reset signal VCCH1 transitions at low temperature COLD and a time point at which the second power-on reset signal VCCH2 transitions at high temperature HOT TEMP. It is designed to be substantially identical. In addition, in the power-on reset circuit of FIG. 7, the output signal of the first power-on reset signal VCCH1 and the second power-on reset unit 200, which are output signals of the first power-on reset unit 100, may be used. The second power-on reset signal VCCH2 is logically output through the NAND gate 400 and the inverter 450 and output.

Therefore, in the low temperature COLD TEMP, when the first power-on reset signal VCCH1, which is the output signal of the first power-on reset unit 100, transitions to logic "high", the power-on reset circuit of FIG. The power-on reset signal POR, which is an output signal, transitions to logic “high”, and at a high temperature COLD TEMP, the second power-on reset signal VCCH2, which is an output signal of the second power-on reset unit 200, is output. Transitions to logic "high", the power-on reset signal POR, which is the output signal of the power-on reset circuit of FIG. 3, transitions to logic "high". In addition, in the power-on reset circuit of FIG. 7, when the first power-on reset signal VCCH1 transitions at low temperature COLD TEMP, the second power-on reset signal VCCH2 transitions at high temperature HOT TEMP. In this case, the power-on reset signal POR, which is the output signal of the power-on reset circuit of FIG. High ".

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

As described above, the power-on reset circuit according to the present invention can reduce the variation in the value of the power supply voltage to which the power-on reset signal transitions even when the ambient temperature and the process condition of the semiconductor device change. In particular, the power-on reset circuit according to the present invention can power-on reset circuit blocks in a semiconductor device operating at a low power supply voltage regardless of ambient temperature.

Claims (36)

A first power-on reset that transitions at a first level of a power supply voltage at a first temperature and transitions at a second level of the power supply voltage that is higher than the first level of the power supply voltage at a second temperature lower than the first temperature A first power-on reset unit for generating a signal; A second power-on that generates a second power-on reset signal that transitions near the second level of the power supply voltage at the first temperature and transitions near the first level of the power supply voltage at the second temperature A reset unit; And And an OR gate for performing an OR operation on the first power-on reset signal and the second power-on reset signal and generating a third power-on reset signal. 2. The circuit of claim 1, wherein the power-on reset circuit is The power-on reset is designed such that a time point at which the first power-on reset signal transitions at the first temperature is substantially the same as a time point at which the second power-on reset signal transitions at the second temperature. Circuit. The method of claim 2, wherein the third power-on reset signal is Power-on reset circuit which is activated at about the same time, either at said first temperature or at said second temperature. 4. The circuit of claim 3, wherein the power-on reset circuit is The third power-on reset signal transitions when the first power-on reset signal transitions at the first temperature, and the third power when the second power-on reset signal transitions at the second temperature. The on-on reset signal transitions. The method of claim 4, wherein the first power-on reset unit A voltage divider for dividing the power voltage and outputting the divided voltage to a first node; A first amplifier amplifying the voltage signal of the first node and outputting the voltage signal to the second node; And And a second amplifier for amplifying the voltage signal of the second node and generating and outputting the first power-on reset signal to a third node. The method of claim 5, wherein the first power-on reset unit A first inverter for inverting the voltage signal of the third node; And And a second inverter for inverting an output signal of the first inverter and outputting the first power-on reset signal. The method of claim 6, wherein the voltage divider A first resistor coupled between the power supply voltage and a first node; And And a second resistor coupled between the first node and a ground voltage. 8. The voltage divider of claim 7, wherein the voltage divider is A third resistor coupled between the second resistor and the ground voltage; And And a transistor connected across said third resistor and controlled by an output signal of said first inverter. The method of claim 6, wherein the first amplifier An NMOS transistor having a gate connected to the first node, a source connected to a ground voltage, and a drain connected to a second node; And And a first resistor coupled between the second node and the power supply voltage. The method of claim 9, wherein the first amplifier A second resistor coupled between the first resistor and the power supply voltage; And And a PMOS transistor connected across said second resistor and controlled by an output signal of said second inverter. The method of claim 6, wherein the second amplifier A PMOS transistor having a source connected to the power supply voltage, a drain connected to the third node, and a gate connected to the second node; And And an NMOS transistor having a drain connected to the third node, a source connected to a ground voltage, and a gate connected to the second node. The method of claim 11, wherein the second amplifier A resistor coupled between the source of the first NMOS transistor and the ground voltage; And And a transistor connected across the resistor and controlled by the output signal of the first inverter. The method of claim 4, wherein the second power-on reset unit A voltage divider for dividing the power voltage and outputting the divided voltage to a first node; A first amplifier amplifying the voltage signal of the first node and outputting the voltage signal to the second node; And And a second amplifier for amplifying the voltage signal of the second node and generating and outputting the second power-on reset signal to a third node. The method of claim 13, wherein the second power-on reset unit A first inverter for inverting the voltage signal of the third node; And And a second inverter for inverting the output signal of the first inverter and outputting the second power-on reset signal. 15. The apparatus of claim 14, wherein the voltage divider is A first resistor coupled between the power supply voltage and a first node; And And a second resistor coupled between the first node and a ground voltage. 16. The voltage divider of claim 15, wherein the voltage divider is A third resistor coupled between the second resistor and the ground voltage; And And a transistor connected across said third resistor and controlled by an output signal of said first inverter. 15. The method of claim 14, wherein the first amplifier An NMOS transistor having a gate connected to the first node, a source connected to a ground voltage, and a drain connected to a second node; And And a first resistor coupled between the second node and the power supply voltage. 18. The method of claim 17, wherein the first amplifier A second resistor coupled between the first resistor and the power supply voltage; And And a PMOS transistor connected across said second resistor and controlled by an output signal of said second inverter. The method of claim 14, wherein the second amplifier A PMOS transistor having a source connected to the power supply voltage, a drain connected to the third node, and a gate connected to the second node; And And an NMOS transistor having a drain connected to the third node, a source connected to a ground voltage, and a gate connected to the second node. 20. The apparatus of claim 19, wherein the second amplifier is A resistor coupled between the source of the first NMOS transistor and the ground voltage; And And a transistor connected across the resistor and controlled by the output signal of the first inverter. A first power-on reset that transitions at a first level of a power supply voltage at a first temperature and transitions at a second level of the power supply voltage that is higher than the first level of the power supply voltage at a second temperature lower than the first temperature A first power-on reset unit for generating a signal; A second power-on that generates a second power-on reset signal that transitions near the second level of the power supply voltage at the first temperature and transitions near the first level of the power supply voltage at the second temperature A reset unit; And And an AND gate for performing an AND operation on the first power-on reset signal and the second power-on reset signal and generating a third power-on reset signal. 22. The system of claim 21, wherein the power-on reset circuit is The power-on reset is designed such that a time point at which the first power-on reset signal transitions at the second temperature is substantially the same as a time point at which the second power-on reset signal transitions at the first temperature. Circuit. 23. The system of claim 22, wherein the third power-on reset signal is Power-on reset circuit which is activated at about the same time, either at said first temperature or at said second temperature. 24. The circuit of claim 23, wherein the power-on reset circuit is The third power-on reset signal transitions when the first power-on reset signal transitions at the second temperature, and the third power when the second power-on reset signal transitions at the first temperature. The on-on reset signal transitions. The method of claim 24, wherein the first power-on reset unit A voltage divider for dividing the power voltage and outputting the divided voltage to a first node; A first amplifier amplifying the voltage signal of the first node and outputting the voltage signal to the second node; And And a second amplifier for amplifying the voltage signal of the second node and generating and outputting the first power-on reset signal to a third node. The method of claim 25, wherein the first power-on reset unit A first inverter for inverting the voltage signal of the third node; And And a second inverter for inverting an output signal of the first inverter and outputting the first power-on reset signal. The method of claim 24, wherein the second power-on reset unit A voltage divider for dividing the power voltage and outputting the divided voltage to a first node; A first amplifier amplifying the voltage signal of the first node and outputting the voltage signal to the second node; And And a second amplifier for amplifying the voltage signal of the second node and generating and outputting the second power-on reset signal to a third node. 28. The method of claim 27, wherein the second power-on reset unit A first inverter for inverting the voltage signal of the third node; And And a second inverter for inverting the output signal of the first inverter and outputting the second power-on reset signal. A first power-on reset that transitions at a first level of a power supply voltage at a first temperature and transitions at a second level of the power supply voltage that is higher than the first level of the power supply voltage at a second temperature lower than the first temperature Generating a signal; Generating a second power-on reset signal that transitions near the second level of the power supply voltage at the first temperature and transitions near the first level of the power supply voltage at the second temperature; And Performing an OR operation on the first power-on reset signal and the second power-on reset signal and generating a third power-on reset signal. 30. The method of claim 29, wherein the power-on reset method is And the time point at which the first power-on reset signal transitions at the first temperature is substantially the same as the time point at which the second power-on reset signal transitions at the second temperature. 31. The system of claim 30, wherein the third power-on reset signal is And at said first temperature or at said second temperature at about the same time. 32. The method of claim 31, wherein said power-on reset method is The third power-on reset signal transitions when the first power-on reset signal transitions at the first temperature, and the third power when the second power-on reset signal transitions at the second temperature. -The on-reset signal transitions. A first power-on reset that transitions at a first level of a power supply voltage at a first temperature and transitions at a second level of the power supply voltage that is higher than the first level of the power supply voltage at a second temperature lower than the first temperature Generating a signal; Generating a second power-on reset signal that transitions near the second level of the power supply voltage at the first temperature and transitions near the first level of the power supply voltage at the second temperature; And Performing an AND operation on the first power-on reset signal and the second power-on reset signal and generating a third power-on reset signal. 34. The method of claim 33, wherein the power-on reset method is And the time point at which the first power-on reset signal transitions at the second temperature is substantially the same as the time point at which the second power-on reset signal transitions at the first temperature. 35. The system of claim 34, wherein said third power-on reset signal is And at said first temperature or at said second temperature at about the same time. 36. The method of claim 35, wherein the power-on reset method is The third power-on reset signal transitions when the first power-on reset signal transitions at the second temperature, and the third power when the second power-on reset signal transitions at the first temperature. Power-on reset method characterized in that the on-on reset signal transitions.

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