CN107342757B - Power-on reset circuit based on improved band-gap reference structure - Google Patents
Power-on reset circuit based on improved band-gap reference structure Download PDFInfo
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- CN107342757B CN107342757B CN201710567419.9A CN201710567419A CN107342757B CN 107342757 B CN107342757 B CN 107342757B CN 201710567419 A CN201710567419 A CN 201710567419A CN 107342757 B CN107342757 B CN 107342757B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
- H03K17/223—Modifications for ensuring a predetermined initial state when the supply voltage has been applied in field-effect transistor switches
Abstract
The invention discloses a power-on reset circuit based on an improved band-gap reference structure, which comprises: the power-on detection circuit is used for generating a first divided voltage RX and a second divided voltage LX of differentiated output voltages during power-on; the comparison circuit is used for shaping the output of the power-on detection circuit to obtain a RESET signal RESET required by the digital circuit; the variable resistance circuit is used for connecting a resistance into a circuit or short-circuiting the resistance under the control of a RESET signal RESET output by the comparison circuit.
Description
Technical Field
The present invention relates to a power-on reset circuit, and more particularly, to a power-on reset circuit based on an improved bandgap reference structure.
Background
Fig. 1 shows a power-on reset circuit with a simple structure and most common in the prior art, as shown in fig. 1, the power-on reset circuit includes a resistor R, a capacitor C, a discharge diode D, a comparator CMP and an inverter INV, the circuit utilizes the principle that the voltage on the capacitor cannot change suddenly, when a power supply VDD is turned on, the RC charges to generate an analog signal that gradually rises, when the analog signal voltage is lower, the comparator CMP outputs a stable high level or low level, when the analog signal voltage exceeds the reference voltage of the comparator CMP, the comparator outputs a jump signal, and the reset signal POR is shaped by the inverter INV, wherein the diode functions to quickly discharge the charges accumulated on the capacitor at the moment of power failure so as to generate an effective reset signal at the next power-on.
However, with the conventional reset circuit, the threshold voltage is greatly affected by temperature and process, and the accuracy is poor because the conventional reset circuit does not have a low-voltage protection function.
Disclosure of Invention
In order to overcome the defects in the prior art, the present invention provides a power-on reset circuit based on an improved bandgap reference structure, so as to implement a low-power-consumption power-on reset circuit with a relatively stable threshold voltage under different temperatures and process deviations.
To achieve the above and other objects, the present invention provides a power-on reset circuit based on an improved bandgap reference structure, including:
the power-on detection circuit is used for generating a first divided voltage RX and a second divided voltage LX of differentiated output voltages during power-on;
the comparison circuit is used for shaping the output of the power-on detection circuit to obtain a RESET signal RESET required by the digital circuit;
and the resistance changing circuit is used for connecting the resistance into the circuit or short-circuiting the resistance under the control of a RESET signal RESET output by the comparison circuit.
Furthermore, the power-on detection circuit comprises a first resistor, a second resistor, a third resistor, a capacitor, a first NMOS transistor and a second NMOS transistor, wherein one end of the first resistor and one end of the second resistor are connected with the power supply voltage, the other end of the first resistor is connected with one input end of the comparison circuit, the grid electrode and the drain electrode of the first NMOS transistor to form a first voltage division node RX, the other end of the second resistor is connected with the other input end of the comparison circuit, the third resistor and the capacitor to form a second voltage division node LX, the other end of the third resistor is connected with the grid electrode and the drain electrode of the second NMOS transistor, and the source electrode of the first NMOS transistor, the source electrode of the second NMOS transistor and the other end of the capacitor are grounded.
Further, the comparison circuit employs a comparator, the first voltage division RX is connected to a non-inverting input terminal of the comparator, and the second voltage division LX is connected to an inverting input terminal of the comparator.
Further, the output of the comparator is connected with a plurality of inverters to shape the output to obtain the RESET signal RESET required by the digital circuit.
Furthermore, the variable resistance circuit comprises a fourth resistor, a fifth resistor and a third NMOS transistor, wherein one end of the fourth resistor is connected to the second voltage-dividing node LX, the other end of the fourth resistor is connected to one end of the fifth resistor and the drain of the third NMOS transistor, the gate of the third NMOS transistor is connected to the output end of the comparison circuit, and the source of the third NMOS transistor is grounded.
Furthermore, the second NMOS pipe is formed by connecting m NMOS pipes with the size of the first NMOS pipe in parallel.
Further, m is a positive integer of 2 or more.
Furthermore, the first NMOS pipe and the second NMOS pipe are replaced by bipolar transistors, and the proportional relation of the first NMOS pipe and the second NMOS pipe is unchanged.
Further, in the power-on reset process, when the power supply voltage VDD starts to rise from 0V, before the power supply voltage VDD does not reach the threshold voltages of the first NMOS transistor and the second NMOS transistor, the first NMOS transistor and the second NMOS transistor are turned off, before the output voltage of the comparator is lower than the threshold voltage of the third NMOS transistor, the voltage at the first voltage division RX node is greater than the voltage at the second voltage division LX node, and the voltage difference gradually increases, at this time, the output of the comparator is at a high level, when the output is higher than the threshold voltage of the third NMOS transistor, the third NMOS transistor is turned on, and the fifth resistor is short-circuited; when the power supply voltage exceeds the threshold voltage of the first NMOS transistor, the voltage difference between the two points of the first voltage division RX node and the second voltage division LX node is gradually reduced to 0 along with the reduction of the voltage increase speed at the first voltage division RX node, and the voltage value of the corresponding power supply VDD is the upper threshold voltage VthrWhen the power supply voltage VDD exceeds the upper threshold voltage VthrThen, at this time, the comparator output jumps from a high level to a low level, and the third NMOS transistor NM3 is turned off.
Further, the low-voltage protection reset and the power-on reset are opposite processes, and the difference is that the output of the comparator is at a low level in the initial stage of the low-voltage protection reset, the fifth resistor is connected into the circuit, and the corresponding lower threshold voltage is VthfTherefore, a window is ensured for the power-on reset threshold and the power-off reset threshold.
Compared with the prior art, the power-on reset circuit based on the improved band-gap reference structure realizes the power-on reset circuit by utilizing the improved band-gap reference source structure aiming at the problem that the traditional simple power-on reset circuit is not high in accuracy. Two different threshold voltages are obtained by changing the size of one resistance value, so that the power-off reset function is realized, and the low-power-consumption reset circuit with relatively stable threshold voltages at different temperatures and process deviations is realized.
Drawings
Fig. 1 is a simple and most common power-on reset circuit in the prior art;
fig. 2 is a circuit structure diagram of a power-on reset circuit based on an improved bandgap reference structure according to the present invention;
FIG. 3 is a diagram of the simulation effect of the slow power-on process of the present invention;
FIG. 4 is a diagram illustrating the simulation effect of the fast power-on process of the present invention.
Detailed Description
Other advantages and capabilities of the present invention will be readily apparent to those skilled in the art from the present disclosure by describing the embodiments of the present invention with specific embodiments thereof in conjunction with the accompanying drawings. The invention is capable of other and different embodiments and its several details are capable of modification in various other respects, all without departing from the spirit and scope of the present invention.
Fig. 2 is a circuit structure diagram of a power-on reset circuit based on an improved bandgap reference structure. As shown in fig. 2, the power-on reset circuit based on the improved bandgap reference structure of the present invention includes a power-on detection circuit 10, a comparison circuit 20 and a resistance-changing circuit 30.
The power-on detection circuit 10 consists of resistors R1-R3 and capacitors C, NMOS of NM1-NM2 and is used for generating differentiated output voltages of a first voltage division RX and a second voltage division LX during power-on; a comparator circuit 20, which uses a comparator CMP and is generally accompanied with a plurality of inverters to shape the output to obtain a RESET signal RESET required by the digital circuit; the resistance changing circuit 30 is composed of resistors R4 to R5 and an NMOS transistor NM3, and is used to switch the resistor R5 into a circuit or short-circuit under the control of a RESET signal RESET output from the comparison circuit 20.
One end of each of the resistors R1 and R2 is connected with a power supply VDD, the other end of the resistor R1 is connected with a non-inverting input end of the comparator CMP and a grid and a drain of the NMOS tube NM1 to form a first voltage division node RX, the other end of the resistor R2 is connected with an inverting input end of the comparator CMP, one end of the resistor R3, one end of the resistor R4 and one end of the capacitor C to form a second voltage division node LX, the other end of the resistor R3 is connected with a grid and a drain of the NMOS tube NM2, the other end of the resistor R4 is connected with one end of the resistor R5 and a drain of the NMOS tube NM3, sources of the NMOS tubes NM1, NM2 and NM3, the other end of the capacitor C and the other end of the resistor R5 are grounded, and an output RES.
The power-up process is divided into two stages, the first stage, where the power supply voltage VDD rises from 0V, and NM1 and NM2 are in an off state before reaching the threshold voltages of NM1 and NM2 in a diode connection manner. The voltage value of the first voltage division RX node is VRXThe voltage value at the second voltage division LX is V before the comparator CMP output voltage is lower than the threshold voltage of the NMOS transistor NM3LXVDD — (R4+ R5)/(R2+ R4+ R5), during which the voltage V at the first partial voltage RX nodeRXThe voltage difference is gradually increased and is greater than the voltage value at the second voltage-dividing LX node, the output of the comparator CMP is at a high level, when the output is greater than the threshold voltage of the NMOS transistor NM3, the NMOS transistor NM3 is turned on, R5 is short-circuited, the voltage value at the second voltage-dividing LX node drops to VDD × R4/(R2+ R4), and the output of the comparator CMP is still at a high level. In the second stage, the power supply voltage exceeds the threshold voltage of the diode-connected NMOS transistor NM1, and the voltage value at the first voltage division RX node is
When the NMOS transistor NM2 is turned on, the voltage at the second voltage-dividing LX node is equal to
Following the voltage V at the first partial voltage RX nodeRXThe increase speed is reduced, the voltage difference between the two points of the first voltage division RX node and the second voltage division LX node is gradually reduced to 0, and the voltage value of the corresponding power supply VDD is the upper threshold voltage VthrThe expression is as follows:
wherein Δ VGS＝VGS1-VGS2。
When the power supply voltage VDD exceeds VthrThen, VRX＜VLXAt this time, the comparison is madeThe output of the device CMP jumps from high to low and the NMOS transistor NM3 is turned off.
The low-voltage protection reset process is opposite to the power-on reset process, except that the output of the comparator is low level in the initial stage of low-voltage protection, R5 is connected into the circuit, and the corresponding lower threshold voltage
Thereby ensuring that the power-on reset threshold and the power-off reset threshold have a window.
It should be noted that, in the embodiment of the present invention, the NMOS transistor NM2 is a parallel connection of m NMOS transistors NM1, where m is a positive integer greater than or equal to 2, and of course, NM1 and NM2 may be replaced by BJTs, and their proportional relationship is not changed.
The invention realizes better power-on reset and low-level protection functions under lower current consumption, and the double-threshold voltage process and temperature influence are less. However, the accuracy is ensured, and meanwhile, a comparator is needed to be used for comparison, so that the framework is suitable for power-on reset detection and power-off reset of VDD above 1V in order to ensure the normal operation of the comparator.
Fig. 3 is a diagram of simulation effect of the slow power-on process of the present invention. When the power supply VDD gradually rises, the voltage of the first node RX changes to slowly rise after rising for a period of time along with the power supply, the voltage of the second node LX basically changes linearly along with the rising of the power supply voltage, the RESET signal RESET is at a high level before the two voltages are equal, and then changes to a low level, the process is opposite after the power supply falls, but the power supply voltage corresponding to the inversion of the RESET during power-off is slightly lower than the power supply voltage corresponding to the inversion of the RESET during power-on.
FIG. 4 is a diagram illustrating the simulation effect of the fast power-on process of the present invention. When the power supply is powered on quickly, the voltage of the capacitor C can not change suddenly and is slowly charged and raised, namely the LX voltage can not rise quickly, so that the RESET signal RESET shows hysteresis to the power supply voltage, namely the RESET signal RESET is turned over after the power supply VDD reaches the maximum for a period of time, which is also required by the RESET signal RESET.
In summary, the power-on reset circuit based on the improved bandgap reference structure of the present invention utilizes the improved bandgap reference source structure to implement the power-on reset circuit, which aims at the problem that the conventional simple power-on reset circuit is not high in accuracy. Two different threshold voltages are obtained by changing the size of one resistance value, so that the power-off reset function is realized, and the low-power-consumption reset circuit with relatively stable threshold voltages at different temperatures and process deviations is realized.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Modifications and variations can be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the present invention. Therefore, the scope of the invention should be determined from the following claims.
Claims (8)
1. A power-on reset circuit based on an improved bandgap reference structure, comprising:
the power-on detection circuit comprises a first resistor, a second resistor, a third resistor, a capacitor, a first NMOS tube and a second NMOS tube, wherein one end of the first resistor and one end of the second resistor are connected with a power voltage, the other end of the first resistor is connected with one input end of a comparison circuit, a grid electrode and a drain electrode of the first NMOS tube to form a first voltage division node RX, the other end of the second resistor is connected with the other input end of the comparison circuit, the third resistor and the capacitor to form a second voltage division node LX, the other end of the third resistor is connected with the grid electrode and the drain electrode of the second NMOS tube, and a source electrode of the first NMOS tube, a source electrode of the second NMOS tube and the other end of the capacitor are grounded and used for generating differential output voltages of the first voltage division RX and the second voltage division node LX during power-on;
the comparison circuit is used for shaping the output of the power-on detection circuit to obtain a RESET signal RESET required by the digital circuit;
the variable resistance circuit comprises a fourth resistor, a fifth resistor and a third NMOS tube, wherein one end of the fourth resistor is connected with a second voltage division node LX, the other end of the fourth resistor is connected with one end of the fifth resistor and a drain electrode of the third NMOS tube, a grid electrode of the third NMOS tube is connected with an output end of the comparison circuit, a source electrode of the third NMOS tube is grounded, and the variable resistance circuit is used for connecting the resistors into the circuit or short-circuiting the resistors under the control of a RESET signal RESET output by the comparison circuit to obtain two threshold voltages.
2. A power-on reset circuit based on an improved bandgap reference structure as claimed in claim 1, wherein: the comparison circuit adopts a comparator, the first voltage division RX is connected with a non-inverting input end of the comparator, and the second voltage division LX is connected with an inverting input end of the comparator.
3. A power-on reset circuit based on an improved bandgap reference structure as claimed in claim 2, wherein: the output of the comparator is connected with a plurality of inverters to shape the output to obtain a RESET signal RESET required by the digital circuit.
4. A power-on reset circuit based on an improved bandgap reference structure as claimed in claim 3 wherein: the second NMOS tube adopts m NMOS tubes with the size of the first NMOS tube to be connected in parallel.
5. The power-on reset circuit based on the improved bandgap reference structure of claim 4, wherein: m is a positive integer of 2 or more.
6. A power-on reset circuit based on an improved bandgap reference structure as claimed in claim 5 wherein: the first NMOS tube and the second NMOS tube are replaced by bipolar transistors, and the proportional relation of the first NMOS tube and the second NMOS tube is unchanged.
7. The power-on reset circuit based on the improved bandgap reference structure of claim 6, wherein: in the power-on reset process, when the power supply voltage VDD starts to rise from 0V, before the power supply voltage VDD does not reach the threshold voltages of the first NMOS tube and the second NMOS tube, the first NMOS tube and the second NMOS tube are in a cut-off state, before the output voltage of the comparator is lower than the threshold voltage of the third NMOS tube, the voltage at the first voltage division RX node is larger than the voltage at the second voltage division LX node, the voltage difference is gradually increased, the output of the comparator is at a high level, and when the output is higher than the threshold voltage of the third NMOS tube, the output is higher than the high levelWhen the threshold voltage of the third NMOS tube is higher than the threshold voltage of the third NMOS tube, the third NMOS tube is conducted, and the fifth resistor is short-circuited; when the power supply voltage exceeds the threshold voltage of the first NMOS transistor, the voltage difference between the two points of the first voltage division RX node and the second voltage division LX node is gradually reduced to 0 along with the reduction of the voltage increase speed at the first voltage division RX node, and the voltage value of the corresponding power supply VDD is the upper threshold voltage VthrWhen the power supply voltage VDD exceeds the upper threshold voltage VthrThen, at this time, the comparator output jumps from a high level to a low level, and the third NMOS transistor NM3 is turned off.
8. A power-on reset circuit based on an improved bandgap reference structure as claimed in claim 7 wherein: the difference between the processes of low-voltage protection reset and power-on reset is that the output of the comparator is low level in the initial stage of the low-voltage protection reset, the fifth resistor is connected into the circuit, and the corresponding lower threshold voltage is VthfTherefore, a window is ensured for the power-on reset threshold and the power-off reset threshold.
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| CN107342757B true CN107342757B (en) | 2020-12-04 |
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| CN111900964B (en) * | 2020-08-13 | 2024-03-12 | 南京物间科技有限公司 | Power-on reset and power-off reset circuit with accurate threshold point |
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| US5151614A (en) * | 1990-07-13 | 1992-09-29 | Mitsubishi Denki Kabushiki Kaisha | Circuit having charge compensation and an operation method of the same |
| JPH07202662A (en) * | 1993-12-28 | 1995-08-04 | Nec Corp | Power-on reset circuit |
| US5523709A (en) * | 1994-11-30 | 1996-06-04 | Sgs-Thomson Microelectronics, Inc. | Power-on reset circuit and method |
| CN103178820A (en) * | 2013-03-18 | 2013-06-26 | 珠海市杰理科技有限公司 | Power-on reset circuit |
| JP2014207615A (en) * | 2013-04-15 | 2014-10-30 | ラピスセミコンダクタ株式会社 | Semiconductor device |
| CN104811171A (en) * | 2014-01-26 | 2015-07-29 | 京微雅格（北京）科技有限公司 | Power on reset circuit of zero current |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100607180B1 (en) * | 2004-06-18 | 2006-08-01 | 삼성전자주식회사 | Power-Up reset circuit of semiconductor memory device |
| KR100583611B1 (en) * | 2005-01-25 | 2006-05-26 | 삼성전자주식회사 | Circuit and method for power-on reset |
| JP6046522B2 (en) * | 2013-03-05 | 2016-12-14 | ルネサスエレクトロニクス株式会社 | Semiconductor device and wireless communication device |
| US20150042386A1 (en) * | 2013-08-06 | 2015-02-12 | Cirel Systems Private Limited | Highly accurate power-on reset circuit with least delay |
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Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5151614A (en) * | 1990-07-13 | 1992-09-29 | Mitsubishi Denki Kabushiki Kaisha | Circuit having charge compensation and an operation method of the same |
| JPH07202662A (en) * | 1993-12-28 | 1995-08-04 | Nec Corp | Power-on reset circuit |
| US5523709A (en) * | 1994-11-30 | 1996-06-04 | Sgs-Thomson Microelectronics, Inc. | Power-on reset circuit and method |
| CN103178820A (en) * | 2013-03-18 | 2013-06-26 | 珠海市杰理科技有限公司 | Power-on reset circuit |
| JP2014207615A (en) * | 2013-04-15 | 2014-10-30 | ラピスセミコンダクタ株式会社 | Semiconductor device |
| CN104811171A (en) * | 2014-01-26 | 2015-07-29 | 京微雅格（北京）科技有限公司 | Power on reset circuit of zero current |
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