JP6326021B2 - Semiconductor chip and semiconductor device packaged with the same - Google Patents

Semiconductor chip and semiconductor device packaged with the same Download PDF

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JP6326021B2
JP6326021B2 JP2015183182A JP2015183182A JP6326021B2 JP 6326021 B2 JP6326021 B2 JP 6326021B2 JP 2015183182 A JP2015183182 A JP 2015183182A JP 2015183182 A JP2015183182 A JP 2015183182A JP 6326021 B2 JP6326021 B2 JP 6326021B2
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semiconductor chip
control circuit
circuit
logic
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JP2016034028A (en
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啓明 木村
啓明 木村
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ローム株式会社
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Description

  The present invention relates to a semiconductor chip and a semiconductor device packaged with the semiconductor chip.

  Conventionally, many semiconductor devices have an electrostatic breakdown protection element in an I / O [Input / Output] portion of an internal circuit.

  As an example of the related art related to the above, Patent Document 1 can be cited.

JP 2010-287644 A

  The electrostatic breakdown protection element described above can prevent electrostatic breakdown of the internal circuit when a surge is applied. However, when a current flows into the power supply line through the electrostatic protection element when a surge is applied, a low voltage of about 0.5 V may be generated in the power supply line. Therefore, in a semiconductor device that can be driven at a low voltage by miniaturization of a semiconductor manufacturing process, an internal circuit malfunctions when a surge is applied.

  In particular, when the internal circuit includes a “nonvolatile memory element that can be driven at a low voltage”, an unintended access operation to the nonvolatile memory element is performed when a surge is applied, and the data of the nonvolatile memory element is garbled. There was a risk of it occurring.

  In view of the above-described problems found by the inventors of the present application, the present invention provides a semiconductor chip capable of preventing malfunction of an internal circuit at the time of applying a surge (for example, data corruption of a nonvolatile memory element), and An object of the present invention is to provide a semiconductor device in which this is packaged.

  In order to achieve the above object, a semiconductor chip according to the present invention includes a plurality of pads, a plurality of electrostatic breakdown protection elements connected between the plurality of pads and a power supply line, and the plurality of pads. A configuration having a surge detection unit that monitors whether or not applied voltages appearing at least two pads are at the same logic level, and an internal circuit whose operation is permitted / prohibited according to the detection result of the surge detection unit ( First configuration).

  In the semiconductor chip having the first configuration, the pads that are monitored by the surge detection unit may be arranged adjacent to each other (second configuration).

  In the semiconductor chip having the first or second configuration, the internal circuit may have a configuration (third configuration) including a nonvolatile logic for storing data in a nonvolatile manner.

  In order to achieve the above object, a semiconductor chip according to the present invention includes a first control circuit, a second control circuit, a controlled circuit, a first pad connected to the first control circuit, A second pad connected to a second control circuit, wherein the first control circuit and the second control circuit are configured such that a signal externally output from the first control circuit via the first pad Only when externally input to the second control circuit via the second pad, a single control circuit is formed to control the operation of the controlled circuit (fourth configuration).

  In the semiconductor chip having the fourth configuration, the first pad and the second pad may be configured to be spaced apart from each other (fifth configuration).

  In the semiconductor chip having the fourth or fifth configuration, the controlled circuit may have a configuration (sixth configuration) including a nonvolatile logic for storing data in a nonvolatile manner.

  In order to achieve the above object, a semiconductor chip according to the present invention includes a first pad, a second pad, and a signal externally output via the first pad via the second pad. A configuration (seventh configuration) is provided that includes a mounting detection unit that monitors whether or not the operation has been performed and an internal circuit that is permitted / prohibited in accordance with the detection result of the mounting detection unit.

  In the semiconductor chip having the seventh configuration, the mounting detection unit includes a transmission unit that transmits a signal through the first pad, a reception unit that receives a signal through the second pad, and the transmission unit. And a synchronization control unit that performs synchronization control of the receiving unit (eighth configuration).

  In the semiconductor chip having the eighth configuration, a signal transmitted and received between the transmission unit and the reception unit may have a configuration (a ninth configuration) that is a multi-bit serial signal.

  In the semiconductor chip having the ninth configuration, when the mounting detection unit detects that transmission / reception of a signal is established between the transmission unit and the reception unit, the mounting detection unit holds the detection result and transmits / receives the signal. It may be configured to stop (10th configuration).

  In the semiconductor chip having the tenth configuration, the mounting detection unit may be configured to periodically transmit / receive a signal and update a detection result (an eleventh configuration) after stopping the transmission / reception of the signal.

  In the semiconductor chip having any one of the seventh to eleventh configurations, the first pad and the second pad may be configured to be spaced apart from each other (a twelfth configuration).

  In the semiconductor chip having any one of the seventh to twelfth configurations, the internal circuit may have a configuration (a thirteenth configuration) including a nonvolatile logic for storing data in a nonvolatile manner.

  In the semiconductor chip having any one of the second, sixth, and thirteenth configurations, the nonvolatile logic is a volatile storage unit that holds data in a volatile manner using a plurality of logic gates connected in a loop. A nonvolatile storage unit that nonvolatilely stores data volatilely stored in the volatile storage unit using the hysteresis characteristics of the ferroelectric element, and the volatile storage unit and the nonvolatile storage unit. And a circuit separation unit that electrically isolates the circuit (a fourteenth configuration).

  A semiconductor device according to the present invention includes a semiconductor chip having any one of the first to fourteenth configurations, a sealing body that seals the semiconductor chip, a plurality of pads provided on the semiconductor chip, and And a plurality of electrically connected lead frames (fifteenth configuration).

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor chip which can prevent the malfunctioning of an internal circuit at the time of a surge application (for example, data corruption of a non-volatile memory element), and the semiconductor device which packaged this can be provided.

The top view which shows the whole structure of a semiconductor device Circuit diagram showing a first configuration example of the semiconductor chip 10 Block diagram showing a second configuration example of the semiconductor chip 10 Block diagram showing a third configuration example of the semiconductor chip 10 The circuit diagram which shows the example of 1 structure of the data holding device which forms the non-volatile logic 142 Timing chart for explaining an operation example of the data holding device Circuit diagram showing signal path during normal operation Circuit diagram showing signal path during data write operation Circuit diagram showing signal path during data read operation

<Semiconductor device>
FIG. 1 is a plan view showing the overall configuration of the semiconductor device (the inside of the semiconductor device is a perspective view with broken lines). The semiconductor device 1 of this configuration example includes a semiconductor chip 10, a sealing body 20, and a plurality of lead frames 30.

  The semiconductor chip 10 is a chip that can be driven at a low voltage by miniaturization of a semiconductor manufacturing process. The sealing body 20 is a resin member that seals the semiconductor chip 10. The lead frame 30 is a metal member that is electrically connected to a plurality of pads P provided on the semiconductor chip 10. One end of each lead frame 30 is drawn out of the sealing body 20 and is electrically connected to a printed wiring on a substrate on which the semiconductor device 1 is mounted.

<Semiconductor chip>
[First configuration example]
FIG. 2 is a circuit diagram showing a first configuration example of the semiconductor chip 10. The semiconductor chip 10 of the first configuration example has a function of detecting whether surge is applied and determining whether the internal circuit 14 is operable. Specifically, the semiconductor chip 10 of the first configuration example includes pads P11 and P12, diodes 11H and 11L, diodes 12H and 12L, an AND gate 13, an internal circuit 14, a first power supply line 15, and the like. And a second power supply line 16.

  The pads P11 and P12 are used as a surge detection pad (a monitoring target pad by the AND gate 13) among the plurality of pads P provided on the semiconductor chip 10. The pads P11 and P12 are also used as input pads for the external enable signals S11 and S12.

  The diodes 11H and 11L are electrostatic breakdown protection elements connected between the pad P11 and the first power supply line 15 and the second power supply line 16. The anode of the diode 11H is connected to the pad P11. The cathode of the diode 11 </ b> H is connected to the first power supply line 15. The cathode of the diode 11L is connected to the pad P11. The anode of the diode 11 </ b> L is connected to the second power supply line 15. Accordingly, when a positive surge is applied to the pad P11, a current flowing from the pad P11 to the first power supply line 15 through the diode 11H is absorbed to absorb the positive surge and prevent the internal circuit 14 from being destroyed. can do. On the other hand, when a negative surge is applied to the pad P11, current flowing from the second power supply line 15 to the pad P11 through the diode 11L is absorbed to absorb the negative surge and prevent the internal circuit 14 from being destroyed. can do.

  The diodes 12H and 12L are electrostatic breakdown protection elements connected between the pad P12 and the first power supply line 15 and the second power supply line 16. The anode of the diode 12H is connected to the pad P12. The cathode of the diode 12 </ b> H is connected to the first power supply line 15. The cathode of the diode 12L is connected to the pad P12. The anode of the diode 12 </ b> L is connected to the second power supply line 15. Therefore, when a positive surge is applied to the pad P12, a current flowing from the pad P12 to the first power supply line 15 through the diode 12H is absorbed to absorb the positive surge and prevent the internal circuit 14 from being destroyed. can do. On the other hand, when a negative surge is applied to the pad P12, current flowing from the second power supply line 15 to the pad P12 via the diode 12L is absorbed to absorb the negative surge and prevent the internal circuit 14 from being destroyed. can do.

  The AND gate 13 is connected between the first power supply line 15 and the second power supply line 16, and determines whether or not the applied voltages (external enable signals S11 and S12) appearing on the pads P11 and P12 are at the same logic level. The internal enable signal S13 is generated by monitoring. More specifically, the AND gate 13 has a logic between an external enable signal S11 applied to the first input terminal (non-inverted format) and an external enable signal S12 applied to the second input terminal (inverted format). The product signal is output as the internal enable signal S13. Therefore, the internal enable signal S13 becomes high level (logic level for permitting the operation of the internal circuit 14) only when the external enable signal S11 is at high level and the external enable signal S12 is at low level. In both cases, the level is low (a logic level for inhibiting the operation of the internal circuit 14).

  The internal circuit 14 is connected between the first power supply line 15 and the second power supply line 16, and is a circuit block whose operation is permitted / prohibited according to the internal enable signal S13. The internal circuit 14 includes a control circuit 141 and nonvolatile logic 142.

  The control circuit 141 generates a control signal SX for performing non-volatile save / restore of register data or the like in the non-volatile logic 142. For example, when the power supply voltage VDD is cut off, a control signal SX for saving register data or the like from the volatile storage unit in the nonvolatile logic 142 to the nonvolatile storage unit is generated. On the other hand, when the power supply voltage VDD is turned on, a control signal SX for restoring register data or the like from the nonvolatile storage unit in the nonvolatile logic 142 to the volatile storage unit is generated.

  The non-volatile logic 142 is a controlled circuit to which the control signal SX from the control circuit 141 is input, and is a logic having a function of performing non-volatile save / restore of register data and the like handled internally based on the control signal SX. Circuit. Note that the configuration and operation of a data holding device (such as a latch circuit combining a volatile storage unit and a nonvolatile storage unit) forming the nonvolatile logic 142 will be described in detail later.

  The first power supply line 15 is a line to which the power supply voltage VDD is applied in a state where the semiconductor device 1 is mounted on the substrate. The second power supply line 16 is a line to which the ground voltage GND is applied in a state where the semiconductor device 1 is mounted on the substrate.

  The surge detection operation of the semiconductor chip 10 having the above configuration will be described in detail. First, in a state where the semiconductor device 1 is not mounted on the substrate, a positive surge is applied to any one of the lead frames 30 provided in the semiconductor device 1, and the voltage of the first power supply line 15 is applied to the AND gate 13 and the internal Consider a case where the voltage rises transiently to the operable voltage of the circuit 14.

  In this case, a voltage rise occurs in the pads P11 and P12 connected to the first power supply line 15 via the diodes 11H and 12H in the same manner as the first power supply line 15. Such a state corresponds to a state in which the external enable signals S11 and S12 input to the AND gate 13 are both at a high level. Accordingly, since the internal enable signal S13 output from the AND gate 13 is at a low level, the operation of the internal circuit 14 (at least the operation of generating the control signal SX by the control circuit 141) is prohibited. As a result, unintended access to the non-volatile storage unit included in the non-volatile logic 142 can be prohibited, so that it is possible to prevent data corruption in the non-volatile storage unit when a surge is applied.

  The pads P11 and P12 are desirably arranged adjacent to each other on the semiconductor chip 10 so that the voltage fluctuation occurs in the same manner as the voltage of the first power supply line 15 changes.

  Next, consider the case where the external enable signal S11 is set to the high level and the external enable signal S12 is set to the low level while the semiconductor device 1 is mounted on the substrate. In this case, since the internal enable signal S13 output from the AND gate 13 is at a high level, the operation of the internal circuit 14 is permitted. As a result, the control circuit 141 can perform non-volatile save / restore of register data and the like in the non-volatile logic 142 as necessary.

  On the other hand, if the nonvolatile saving / restoring of register data or the like in the nonvolatile logic 142 is intentionally prohibited, the external enable signals S11 and S12 are set to logic levels (H / H, L) other than the above combinations (H / L). / H, L / L).

  As described above, the AND gate 13 functions as a surge detection unit when the semiconductor device 1 is not mounted on the substrate, and functions as an internal enable signal generation unit when the semiconductor device 1 is mounted on the substrate. .

  An EXOR gate can be used instead of the AND gate 13. Further, the number of pads to be monitored by the AND gate 13 is not limited to two, and may be three or more. In that case, it is possible to use a majority circuit instead of the AND gate 13.

[Second configuration example]
FIG. 3 is a block diagram illustrating a second configuration example of the semiconductor chip 10. The semiconductor chip 10 of the second configuration example has a function of detecting whether or not the semiconductor device 1 is mounted on a substrate by the chip itself and determining whether or not the internal circuit 14 can operate. More specifically, the semiconductor chip 10 of the second configuration example includes a pad P21, a pad P22, and an internal circuit 14. The internal circuit 14 includes a control circuit 141 and nonvolatile logic 142. The basic functions of the control circuit 141 and the nonvolatile logic 142 are the same as those in the first configuration example described above.

  In the semiconductor chip 10 of the second configuration example, the control circuit 141 is separated into a first control circuit CTRL1 and a second control circuit CTRL2. The signal output terminal of the first control circuit CTRL1 is connected to the lead frame 31 via the pad P21. The signal input terminal of the second control circuit CTRL2 is connected to the lead frame 32 via the pad P22.

  The first control circuit CTRL1 and the second control circuit CTRL2 are configured such that the signal S21 output from the first control circuit CTRL1 via the pad P21 and the lead frame 31 is output to the second control circuit via the lead frame 32 and the pad P22. Only when externally input to CTRL 2, one control circuit 141 is formed, and it becomes possible to control nonvolatile saving / restoring of register data and the like in the nonvolatile logic 142.

  That is, the first control circuit CTRL1 and the second control circuit CTRL2 are only provided when the semiconductor device 1 is mounted on the substrate and the lead frame 31 and the lead frame 32 are connected via the printed wiring 40. One control circuit 141 is formed, and it becomes possible to control nonvolatile saving / restoring of register data and the like in the nonvolatile logic 142.

  Therefore, when the semiconductor device 1 is not mounted on the substrate, the control circuit 141 does not function at all. Therefore, even if the power supply voltage rises unintentionally when a surge is applied, the nonvolatile logic 142 includes Unintentional access to the storage unit does not occur, and as a result, data corruption of the nonvolatile storage unit when a surge is applied can be prevented.

  It should be noted that the pads P21 and P22 are preferably arranged apart from each other so that the pad P21 and the pad P22 are not unintentionally short-circuited and the control circuit 141 becomes operable. . For the same reason as described above, it is desirable that the lead frames 31 and 32 are also arranged apart from each other.

[Third configuration example]
FIG. 4 is a block diagram illustrating a third configuration example of the semiconductor chip 10. The semiconductor chip 10 of the third configuration example also has a function of detecting whether or not the semiconductor device 1 is mounted on the substrate by itself and determining whether or not the internal circuit 14 can operate. This has common points with the second configuration example. However, unlike the second configuration example, the semiconductor chip 10 of the third configuration example is not configured to separate the control circuit 141 into two as mounting detection means, but is configured to have a separate mounting detection unit 17. Specifically, the semiconductor chip 10 of the third configuration example includes a pad P31, a pad P32, an internal circuit 14, and a mounting detection unit 17.

  The mounting detector 17 monitors whether or not the signal S31 externally output via the pad P31 is externally input via the pad P32 and generates the internal enable signal S32. Specifically, the mounting detection unit 17 includes a transmission unit 171, a reception unit 172, and a synchronization control unit 173. Transmitter 171 transmits signal S31 via pad P31. The receiving unit 172 receives the signal S31 via the pad P32. The synchronization control unit 173 performs synchronization control of the transmission unit 171 and the reception unit 172.

  The reception unit 172 sets the internal enable signal S32 to a high level only when the signal S31 externally output from the transmission unit 171 via the pad P31 and the lead frame 31 is externally input via the lead frame 32 and the pad P32. The operation of the internal circuit 14 is permitted. That is, the internal enable signal S32 is set to the high level only when the semiconductor device 1 is mounted on the substrate and the lead frame 31 and the lead frame 32 are connected via the printed wiring 40. The operation of the internal circuit 14 is permitted.

  On the other hand, when the semiconductor device 1 is not mounted on the substrate and the lead frame 31 and the lead frame 32 are not connected, the internal enable signal S32 is set to the low level and the operation of the internal circuit 14 is performed. Is prohibited. Therefore, in a state where the semiconductor device 1 is not mounted on the substrate, unintended access to the nonvolatile memory unit included in the nonvolatile logic 142 occurs even when the power supply voltage unintentionally rises when a surge is applied. In other words, it is possible to prevent garbled data in the non-volatile storage unit when a surge is applied.

  In order to increase the detection accuracy of the mounting detection unit 17, the signal S31 transmitted and received between the transmission unit 171 and the reception unit 172 is not a simple high / low signal (1-bit binary signal), It is desirable to use a multi-bit serial signal.

  Further, when the mounting detection unit 17 detects that the transmission / reception of the signal S31 is established between the transmission unit 171 and the reception unit 172 (that is, the semiconductor device 1 is mounted on the substrate), the mounting enable unit 17 It is desirable that the transmission / reception of the signal S31 is stopped while holding S32 at a high level. With this configuration, power is not wasted in the mounting detection unit 17 during normal operation of the semiconductor device 1.

  However, when it is necessary to detect the unmounting of the semiconductor device 1, the mounting detection unit 17 periodically transmits / receives the signal S31 after stopping the transmission / reception of the signal S31 to update the logic level of the internal enable signal S32. It does not matter as a structure to do.

  The pads P31 and P32, and the lead frames 31 and 32 are desirably spaced apart from each other so that an unintended short circuit is unlikely to occur.

<Non-volatile logic>
FIG. 5 is a circuit diagram showing a configuration example of the data holding device forming the nonvolatile logic 142. The data holding device of this configuration example includes inverters INV1 to INV7, path switches SW1 to SW4, multiplexers MUX1 and MUX2, N-channel field effect transistors Q1a, Q1b, Q2a, and Q2b, and ferroelectric elements (ferroelectric elements). Body capacitor) CL1a, CL1b, CL2a, CL2b.

  The input end of the inverter INV1 is connected to the application end of the data signal (D). The output terminal of the inverter INV1 is connected to the input terminal of the inverter INV2. The output terminal of the inverter INV2 is connected to the first input terminal (1) of the multiplexer MUX1 via the pass switch SW1. The output terminal of the multiplexer MUX1 is connected to the input terminal of the inverter INV3. The output terminal of the inverter INV3 is connected to the input terminal of the inverter INV5. The output end of the inverter INV5 is connected to the output end of the output signal (Q). The first input terminal (1) of the multiplexer MUX2 is connected to the output terminal of the inverter INV3. The output terminal of the multiplexer MUX2 is connected to the input terminal of the inverter INV4. The output terminal of the inverter INV4 is connected to the first input terminal (1) of the multiplexer MUX1 via the pass switch SW2.

  As described above, the data holding device of this configuration example uses the two logic gates connected in a loop (inverters INV3 and INV4 in FIG. 5) to volatilize the input data signal D. It has a sex memory unit VM (loop structure unit).

  The input terminal of the inverter INV6 is connected to the first input terminal (1) of the multiplexer MUX1. The output terminal of the inverter INV6 is connected to the second input terminal (0) of the multiplexer MUX2 via the pass switch SW3. The input terminal of the inverter INV7 is connected to the first input terminal (1) of the multiplexer MUX2. The output terminal of the inverter INV7 is connected to the second input terminal (0) of the multiplexer MUX1 via the pass switch SW4.

  The positive electrode end of the ferroelectric element CL1a is connected to the first plate line PL1. The negative end of the ferroelectric element CL1a is connected to the second input end (0) of the multiplexer MUX2. A transistor Q1a is connected between both ends of the ferroelectric element CL1a. The gate of the transistor Q1a is connected to the application terminal of the F reset signal FRST.

  The positive terminal of the ferroelectric element CL1b is connected to the second input terminal (0) of the multiplexer MUX2. The negative electrode end of the ferroelectric element CL1b is connected to the second plate line PL2. A transistor Q1b is connected between both ends of the ferroelectric element CL1b. The gate of the transistor Q1b is connected to the application terminal of the F reset signal FRST.

  The positive electrode end of the ferroelectric element CL2a is connected to the first plate line PL1. The negative end of the ferroelectric element CL2a is connected to the second input end (0) of the multiplexer MUX1. A transistor Q2a is connected between both ends of the ferroelectric element CL2a. The gate of the transistor Q2a is connected to the application terminal of the F reset signal FRST.

  The positive terminal of the ferroelectric element CL2b is connected to the second input terminal (0) of the multiplexer MUX1. The negative electrode end of the ferroelectric element CL2b is connected to the second plate line PL2. A transistor Q2b is connected between both ends of the ferroelectric element CL2b. The gate of the transistor Q2b is connected to the application terminal of the F reset signal FRST.

  Thus, the data holding device of this configuration example stores the data D held in the volatile storage unit VM in a nonvolatile manner using the hysteresis characteristics of the ferroelectric elements (CL1a, CL1b, CL2a, CL2b). A non-volatile storage unit NVM is included.

  Among the above-described components, the path switch SW1 is turned on / off in response to the clock signal CLK, and the path switch SW2 is turned on / off in response to the inverted clock signal CLKB (logic inverted signal of the clock signal CLK). The That is, the path switch SW1 and the path switch SW2 are turned on / off exclusively (complementarily) to each other.

  On the other hand, the path switches SW3 and SW4 are both turned on / off according to the control signal E1. Further, the signal paths of the multiplexers MUX1 and MUX2 are switched according to the control signal E2. That is, in the data holding device of this configuration example, the multiplexers MUX1 and MUX2, the inverters INV6 and INV7, and the path switches SW3 and SW4 are circuit separations that electrically separate the volatile memory unit VM and the nonvolatile memory unit NVM. It functions as a part SEP.

  Next, the operation of the data holding device configured as described above will be described in detail. In the following description, the voltage appearing at the connection node of the ferroelectric elements CL1a and CL1b is V1, the voltage appearing at the connection node of the ferroelectric elements CL2a and CL2b is V2, the voltage appearing at the input terminal of the inverter INV4 is V3, The voltage appearing at the output terminal of the inverter INV4 is denoted by V4, the voltage appearing at the input terminal of the inverter INV3 is denoted by V5, and the voltage appearing at the output terminal of the inverter INV3 is denoted by V6.

  FIG. 6 is a timing chart for explaining an operation example of the data holding device. In order from the top, the power supply voltage VDD, the clock signal CLK, the data signal D, the control signal E1, the control signal E2, and the F reset signal FRST. 2 shows voltage waveforms of the applied voltage of the first plate line PL1, the applied voltage of the second plate line PL2, the node voltage V1, the node voltage V2, and the output signal Q.

  Of the various signals described above, the clock signal CLK, the control signal E1, the control signal E2, the F reset signal FRST, the applied voltage of the first plate line PL1, and the applied voltage of the second plate line PL2 are the control circuit 141. Corresponds to the control signal SX (see FIGS. 2 to 4).

  First, the normal operation of the data holding device will be described.

  Until the time point W1, the F reset signal FRST is “1 (high level: VDD)”, the transistors Q1a, Q1b, Q2a, Q2b are turned on, and both ends of the ferroelectric elements CL1a, CL1b, CL2a, CL2b. Since all of them are short-circuited, no voltage is applied to these ferroelectric elements CL1a, CL1b, CL2a, CL2b. The first plate line PL1 and the second plate line PL2 are both “0 (low level: GND)”.

  Further, until the time point W1, the control signal E1 is set to “0 (GND)”, and the path switch SW3 and the path switch SW4 are turned off. Therefore, the data write drivers (inverters INV6 and INV7 in the example of FIG. 5) are used. ) Are all invalid.

  Further, until the time point W1, the control signal E2 is set to “1 (VDD)” and the multiplexer MUX1 and the first input terminal (1) of the multiplexer MUX2 are selected. A loop is formed.

  Therefore, during the high level period of the clock signal CLK, the pass switch SW1 is turned on and the pass switch SW2 is turned off, so that the data signal D is directly passed as the output signal Q. On the other hand, since the pass switch SW1 is turned off and the pass switch SW2 is turned on during the low level period of the clock signal CLK, the data signal D is latched at the falling edge of the clock signal CLK.

  FIG. 7 is a circuit diagram showing a signal path (depicted as a thick line in the drawing) during the normal operation described above.

  Next, a data write operation to the ferroelectric element will be described.

  At time points W1 to W3, the clock signal CLK is set to “0 (GND)”, and the inverted clock signal CLKB is set to “1 (VDD)”. Accordingly, the first path switch SW1 is turned off and the second path switch is turned on. As described above, by fixing the logic of the clock signal CLK and the inverted clock signal CLKB in advance, it is possible to improve the stability of the data write operation with respect to the ferroelectric element.

  At time points W1 to W3, the F reset signal FRST is set to “0 (GND)”, the transistors Q1a, Q1b, Q2a, and Q2b are turned off, and voltage application to the ferroelectric elements CL1a, CL1b, CL2a, and CL2b is performed. Possible state.

  Further, at time points W1 to W3, the control signal E1 is set to “1 (VDD)”, and the path switch SW3 and the path switch SW4 are turned on. Accordingly, the data write drivers (inverters INV6 and INV7 in the example of FIG. 5) are all valid.

  Note that at the time points W1 to W3, the control signal E2 is set to “1 (VDD)”, and the multiplexer MUX1 and the first input terminal (1) of the multiplexer MUX2 are selected. A normal loop is formed in the storage unit VM.

  Further, at the time points W1 to W2, the first plate line PL1 and the second plate line PL2 are set to “0 (GND)”, and at the time points W2 to W3, the first plate line PL1 and the second plate line PL2 are set to “1 ( VDD) ". That is, the same pulse voltage is applied to the first plate line PL1 and the second plate line PL2. By applying such a pulse voltage, the remanent polarization state inside the ferroelectric element is set to either the inversion state or the non-inversion state.

  More specifically, referring to FIG. 6, since the output signal Q is “1 (VDD)” at the time point W1, the node voltage V1 becomes “0 (GND)” and the node voltage V2 becomes “1 (VDD). ) ”. Therefore, at time points W1 to W2, while the first plate line PL1 and the second plate line PL2 are set to “0 (GND)”, no voltage is applied across the ferroelectric elements CL1a and CL1b. Thus, a negative voltage is applied between both ends of the ferroelectric element CL2a, and a positive voltage is applied between both ends of the ferroelectric element CL2b. On the other hand, at time points W2 to W3, no voltage is applied across the ferroelectric elements CL2a and CL2b while the first plate line PL1 and the second plate line PL2 are set to “1 (VDD)”. Thus, a positive voltage is applied across the ferroelectric element CL1a, and a negative voltage is applied across the ferroelectric element CL1b.

  As described above, by applying the pulse voltage to the first plate line PL1 and the second plate line PL2, the remanent polarization state inside the ferroelectric element is set to either the inversion state or the non-inversion state. . Note that the remanent polarization state is reversed between the ferroelectric elements CL1a and CL1b and between the ferroelectric elements CL2a and CL2b. Further, the remanent polarization state is also reversed between the ferroelectric elements CL1a and CL2a and between the ferroelectric elements CL1b and CL2b.

  At the time point W3, the F reset signal FRST is set to “1 (VDD)” again, so that the transistors Q1a, Q1b, Q2a, and Q2b are turned on, and between both ends of the ferroelectric elements CL1a, CL1b, CL2a, and CL2b. Since both are short-circuited, no voltage is applied to these ferroelectric elements CL1a, CL1b, CL2a, CL2b. At this time, both the first plate line PL1 and the second plate line PL2 are set to “0 (GND)”.

  At the time point W3, the control signal E1 is again set to “0 (GND)”, and the pass switch SW3 and the pass switch SW4 are turned off, so that the data write drivers (inverters INV6 and INV7 in the example of FIG. 5) Is also invalidated. Note that the control signal E2 is not questioned, but is “0 (GND)” in the example of FIG.

  At time W4, the supply of the power supply voltage VDD is interrupted. At this time, the F reset signal FRST is maintained at “1 (VDD)” from the time point W3, and the transistors Q1a, Q1b, Q2a, Q2b are turned on, and both ends of the ferroelectric elements CL1a, CL1b, CL2a, CL2b. Both are short-circuited. Therefore, since no voltage is applied to the ferroelectric elements CL1a, CL1b, CL2a, and CL2b, even if a voltage fluctuation occurs when the power is shut off, the ferroelectric elements CL1a, CL1b, CL2a, An unintended voltage is not applied to CL2b, and garbled data can be avoided.

  FIG. 8 is a circuit diagram showing a signal path (depicted as a thick line in the drawing) during the above-described data write operation (particularly, time points W1 to W3).

  Next, a data read operation from the ferroelectric element will be described.

  At time points R1 to R5, the clock signal CLK is set to “0 (GND)”, and the inverted clock signal CLKB is set to “1 (VDD)”. Accordingly, the first path switch SW1 is turned off and the second path switch is turned on. As described above, by fixing the logic of the clock signal CLK and the inverted clock signal CLKB in advance, it is possible to improve the stability of the data reading operation from the ferroelectric element.

  At the time point R1, the F reset signal FRST is first set to “1 (VDD)”, the transistors Q1a, Q1b, Q2a, Q2b are turned on, and both ends of the ferroelectric elements CL1a, CL1b, CL2a, CL2b. Both are short-circuited. Accordingly, since no voltage is applied to the ferroelectric elements CL1a, CL1b, CL2a, and CL2b, even if voltage fluctuation occurs when the power is turned on, the ferroelectric elements CL1a, CL1b, CL2a, and CL2b An unintended voltage is not applied, and garbled data can be avoided.

  At time R1, both the first plate line PL1 and the second plate line PL2 are set to “0 (GND)”.

  At the time point R2, the control signals E1 and E2 are both set to “0 (GND)” (that is, the data write driver is invalidated, and the normal loop is invalidated in the volatile memory unit VM). Power supply voltage VDD is turned on. At this time, the signal line depicted by the thick line in FIG. 9 is floating.

  At the subsequent time point R3, the F reset signal FRST is set to “0 (GND)”, the transistors Q1a, Q1b, Q2a, and Q2b are turned off, and a voltage can be applied to the ferroelectric elements CL1a, CL1b, CL2a, and CL2b. On the other hand, the first plate line PL1 is set to “1 (VDD)” while the second plate line PL2 is maintained at “0 (GND)”. By applying such a pulse voltage, voltage signals corresponding to the remanent polarization state in the ferroelectric element appear as the node voltage V1 and the node voltage V2.

  More specifically, referring to the example of FIG. 6, a relatively low voltage signal (hereinafter, the logic is referred to as WL [Weak Low]) appears as the node voltage V1, and the node voltage V2 is relatively A high voltage signal (hereinafter, its logic is called WH [Weak Hi]) appears. That is, a voltage difference is generated between the node voltage V1 and the node voltage V2 according to the difference in the remanent polarization state in the ferroelectric element.

  At this time, at time points R3 to R4, the control signal E2 is set to “0 (GND)”, and the multiplexer MUX1 and the second input terminal (0) of the multiplexer MUX2 are selected, so that the logic of the node voltage V3 becomes WL. The logic of the node voltage V4 is WH. The logic of the node voltage V5 is WH, and the logic of the node voltage V6 is WL. As described above, at the time points R3 to R4, the node voltages V1 to V6 of each part of the device are still in an unstable state (the logic inversion in the inverter INV3 and the inverter INV4 is not completely performed, and the output logic is surely “0 (GND ) ”/“ 1 (VDD) ”.

  At the time point R4, the control signal E2 is set to “1 (VDD)”, and the multiplexer MUX1 and the first input terminal (1) of the multiplexer MUX2 are selected. Therefore, a normal loop is formed in the volatile memory unit VM. Yes. With such switching of the signal path, the output terminal (logic: WH) of the inverter INV4 and the input terminal (logic: WH) of the inverter INV3 are connected, and the output terminal (logic: WL) of the inverter INV3 and the input of the inverter INV4 The end (logic: WL) is connected. Accordingly, no mismatch occurs in the signal logic (WH / WL) of each node, and thereafter, while the normal loop is formed in the volatile memory unit VM, the inverter INV3 receives the input of the logic WL, The inverter INV4 tries to raise the output logic to “1 (VDD)”, and the inverter INV4 tries to lower the output logic to “0 (GND)” in response to the input of the logic WH. As a result, the output logic of the inverter INV3 is determined from the unstable logic WL to “0 (GND)”, and the output logic of the inverter INV4 is determined from the unstable logic WH to “1 (VDD)”.

  As described above, at the time point R4, the signal (potential difference between the node voltage V1 and the node voltage V2) read from the ferroelectric element in accordance with the volatile memory unit VM being in the normal loop is the volatile memory unit. The data is amplified by the VM, and the retained data (“1 (VDD)” in the example of FIG. 6) before the power interruption is restored as the output signal Q.

  Thereafter, at the time point R5, the F reset signal FRST is again set to “1 (VDD)”, the transistors Q1a, Q1b, Q2a, and Q2b are turned on, and both ends of the ferroelectric elements CL1a, CL1b, CL2a, and CL2b are connected. Since both are short-circuited, no voltage is applied to these ferroelectric elements CL1a, CL1b, CL2a, CL2b. At this time, both the first plate line PL1 and the second plate line PL2 are set to “0 (GND)”. Therefore, the data holding device is returned to the same state as before the time point W1, that is, the normal operation state.

  FIG. 9 is a circuit diagram showing a signal path (depicted as a thick line in the drawing) during the above-described data read operation (particularly, time points R3 to R4).

  As described above, the data holding device of this configuration example includes a volatile storage unit VM that holds data in a volatile manner using logic gates (inverters INV3 and INV4 in FIG. 5) connected in a loop, A nonvolatile storage unit NVM (CL1a, CL1b, CL2a, CL2b, Q1a, Q1b, Q2a, Q2b) for storing data held in the volatile storage unit VM in a nonvolatile manner using the hysteresis characteristics of the ferroelectric element; A circuit separation unit SEP (MUX1, MUX2, INV6, INV7, SW3, SW4) that electrically separates the volatile storage unit VM and the non-volatile storage unit NVM. During the normal operation of the holding device, the volatile memory unit VM is electrically operated while the voltage applied to the ferroelectric element is kept constant.

  As described above, the ferroelectric elements CL1a, CL1b, CL2a, and CL2b are not directly driven from the signal line of the volatile memory unit VM, but the signal lines and the ferroelectric elements CL1a, CL1b, and CL2a of the volatile memory unit VM. , CL2b are provided with data write drivers (inverters INV6, INV7 in FIG. 5) that also function as buffers, so that the ferroelectric elements CL1a, CL1b, CL2a, CL2b are loaded in the volatile memory unit VM. It becomes possible not to become capacity.

  Further, if the path switches SW3 and SW4 are connected to the output terminals of the data write drivers (inverters INV6 and INV7), and the path switches SW3 and SW4 are turned on only when data is written according to the control signal E1, During normal operation, the ferroelectric elements CL1a, CL1b, CL2a, and CL2b can be prevented from being driven.

  When data is read, the input / output paths of the multiplexers MUX1 and MUX2 are switched according to the control signal E2, so that the logic gates (inverters INV3 and INV4 in FIG. 5) and the ferroelectrics in the volatile memory unit VM are switched. It is possible to control conduction / cutoff with the body elements CL1a, CL1b, CL2a, CL2b. Therefore, it is not necessary to add a large load clock line in order to place the specific node in a floating state, so that it is possible to avoid an increase in power consumption.

  Thus, in the data holding device of this configuration example, since the ferroelectric element is not driven wastefully during normal operation, the same level of speedup as the volatile data holding device, and Low power consumption can be achieved.

  That is, since it can be handled in the same manner as a volatile data holding device, the memory element portion of the existing circuit is replaced with the data holding device of this configuration example without performing redesign such as timing design and power consumption design. It becomes possible. Therefore, since the existing circuit can be easily made non-volatile, for example, it is possible to realize a CPU or the like that can shut down the power without erasing data during standby or can immediately resume the operation after the power is turned on. Become.

<Other variations>
In the above embodiment, the configuration for preventing data corruption of the nonvolatile memory element at the time of surge application has been described as an example, but the configuration of the present invention is not limited to this, The present invention can be widely applied as a technique for preventing malfunction of an internal circuit when a surge is applied.

  Various technical features disclosed in the present specification can be variously modified within the scope of the technical creation in addition to the above-described embodiment. For example, the logic level inversion of various signals is arbitrary. That is, the above-described embodiment is an example in all respects and should not be considered as limiting, and the technical scope of the present invention is not the description of the above-described embodiment, but the claims. It should be understood that all modifications that come within the meaning and range of equivalents of the claims are included.

  The present invention can be used as a technique for improving the reliability of a semiconductor device.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 10 Semiconductor chip 11H, 11L Diode (electrostatic destruction protection element)
12H, 12L diode (electrostatic breakdown protection element)
13 AND gate (surge detector)
14 Internal circuit 141 Control circuit 142 Non-volatile logic 15 First power supply line (VDD line)
16 Second power line (GND line)
17 mounting detection unit 171 transmission unit 172 reception unit 173 synchronization control unit 20 sealing body 30, 31, 32 lead frame 40 printed wiring P11, P12, P21, P22, P31, P32 pad INV1 to INV7 inverter SW1 to SW4 path switch MUX1 , MUX2 Multiplexer Q1a, Q1b, Q2a, Q2b N-channel field effect transistor CL1a, CL1b, CL2a, CL2b Ferroelectric element VM Volatile memory unit NVM Non-volatile memory unit SEP Circuit separation unit P1-P3 P-channel MOS field effect Transistor N1-N3 N-channel MOS field effect transistor

Claims (5)

  1. A first pad and a second pad;
    A plurality of electrostatic breakdown protection elements connected between the first pad and the second pad and a power line;
    A surge detector comprising an AND gate to which signals are input from the first pad and the second pad;
    An internal circuit whose operation is permitted / prohibited according to the detection result of the surge detector;
    A semiconductor chip having
    The internal circuit is
    A first control circuit;
    A second control circuit;
    A controlled circuit;
    Including
    The semiconductor chip is
    A third pad connected to the first control circuit;
    A fourth pad connected to the second control circuit;
    Further comprising
    In the first control circuit and the second control circuit, a signal externally output from the first control circuit via the third pad is externally input to the second control circuit via the fourth pad. Only in such a case, a semiconductor chip is characterized in that one control circuit is formed to control the operation of the controlled circuit.
  2. The semiconductor chip according to claim 1, wherein the third pad and the fourth pad are spaced apart from each other.
  3.   The semiconductor chip according to claim 1, wherein the controlled circuit includes a nonvolatile logic that stores data in a nonvolatile manner.
  4. The non-volatile logic is
    A volatile storage unit that volatilely stores data using a plurality of logic gates connected in a loop; and
    A nonvolatile memory unit that nonvolatilely stores data volatilely stored in the volatile memory unit using the hysteresis characteristics of the ferroelectric element;
    A circuit separation unit for electrically separating the volatile storage unit and the nonvolatile storage unit;
    The semiconductor chip according to claim 3 , comprising:
  5. The semiconductor chip according to any one of claims 1 to 4 ,
    A sealing body for sealing the semiconductor chip;
    A plurality of lead frames each electrically connected to a plurality of pads provided on the semiconductor chip;
    A semiconductor device comprising:
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Publication number Priority date Publication date Assignee Title
JPS61251985A (en) * 1985-04-30 1986-11-08 Toshiba Corp Memory protecting mechanism
JPH0863566A (en) * 1994-08-19 1996-03-08 Sharp Corp Device for preventing memory card malfunction
JP4000096B2 (en) * 2003-08-04 2007-10-31 株式会社東芝 ESD protection circuit
JP4728779B2 (en) * 2005-11-11 2011-07-20 シャープ株式会社 Detection circuit
JP2007201431A (en) * 2005-12-27 2007-08-09 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit device
JP2007187489A (en) * 2006-01-12 2007-07-26 Renesas Technology Corp Semiconductor integrated circuit
JP5069872B2 (en) * 2006-05-31 2012-11-07 新日本無線株式会社 Semiconductor integrated circuit
JP5209445B2 (en) * 2008-11-20 2013-06-12 ローム株式会社 Data holding device
JP5206571B2 (en) * 2009-04-22 2013-06-12 富士通セミコンダクター株式会社 Integrated circuit device having ground open detection circuit

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