JPH0416016A - Flip-flop - Google Patents

Abstract

PURPOSE:To attain high processing speed for the operation of a master slave flip-flop by using only one P-channel MOS treansistor(TR) in existence in a current path determining leading and trailing time of an output signal so as to decrease the leading and trailing time of the output signal. CONSTITUTION:When a clock signal phi1 is at a VDD potential an input signal D is at a VDD potential and an input signal the inverse of D is at a GND potential, then a clock signal phi2 is at a GND potential, N-channel MOS TRs MN3, 6, 7 are turned off and MN1, 2 are turned on. Since a P-channel MOS TR MP1 is turned on and MP2 is turned off, a node 1 goes to a VDD potential and a node 2 goes to a GND potential. When the clock signals phi1, phi2 go to a GND potential and a VDD potential respectively, the processing is implemented reverse, then the potential state of the nodes 1, 2 is stored. That is, the input data signals D, the inverse of D at the trailing are stored in a master slave flip-flop FF1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a flip-flop using a CMOS structure semiconductor integrated circuit, and more particularly to a master-slave type flip-flop that maintains a logic value in a logic circuit.

[Conventional technology]

In the conventional CMO6 structure master-slave type flip-flop, as shown in FIG. 3, the data input terminal and the first CMOS inverter V1 are connected by the first transfer gate TGI, and the first inverter IV1 is 8 is connected to its own input via the second inverter IV2 and the second transfer gate TG2, and is also connected to the third inverter I via the third transfer gate TG3.
V3, and the output of the third inverter IV3 is connected to its own input via the fourth inverter IV4 and fourth transfer gate TG4, and is also connected to the data output terminal Q. The first to fourth transfer gates are MN31 and MP31. MN34 and MP
34. MN35 and MP35. It consists of a pair of N-channel and P-channel transistors, MN38 and MP38, and the first to fourth four inverters are MN32 and MP38.
32. MN33 and MP3B, MN36 and MP36. MN
37 and MP37, a pair of N-channel and P-channel transistors, respectively. Here, MNXX
indicates an N-channel MOS transistor, and MPXX indicates a P
A channel M○S transistor is shown.

In the semiconductor integrated circuit of the CMO3 ellipse, transfer gate TGI~4 and inverter IV1~ are used for boat fishing.
4, a circuit configuration in which a P-channel MOS transistor and an N-channel MOS transistor are connected in a complementary manner is used. In this circuit configuration, when the input signal of the inverter is at GND potential or VDD potential, the output signal potential is at VDD potential or GND potential;
The current flowing to ND is 0, and the steady current is 0 even if multiple stages of inverters are connected in cascade. In low power consumption semiconductor integrated circuits, P-channel MO
It is common to use a CMO8 logic circuit in which an S transistor and an N-channel MOS transistor are connected in a complementary manner, and the circuit shown in FIG. 3 is commonly used as a master-slave type flip-flop.

In FIG. 3, signals φr, cbx, φz, and T2 to the gates of transfer gates TO1 to TO4 are clock signals, and the clock signals of φl and φ2 are complementary clock signals that do not overlap with each other as shown in FIG. It is. φ1 is a negative signal of φ, and φ2 is a negative signal of φ2. The data input signal is applied to the inverter IVI when φ1 is at high level as shown in the second section, and is taken into the master flip-flop (consisting of inverters IVI and IV2) by the falling edge of φ1, and is separated from the input terminal. Retained. This held data signal is output from the data output terminal Q via the third inverter IV3 at the rising edge of φ2 immediately thereafter, and is taken into the slave flip-flop (consisting of inverters IV3 and IV4).

[Problem to be solved by the invention]

In the conventional CMO8 structure master-slave flip-flop described above, the potential of the data output terminal Q is VDD.
In the case of transition from the potential to the GND potential, when φ2 becomes VDD[, the P-channel transistor M of the first inverter IVI is transferred from the VDD terminal of the first inverter IVI.
Current flows to the input of the third inverter through two P-channel MOS transistors, P32 and P-channel transistor MP35 of the third transfer gate, charging the gate terminals of both transistors MP36 and MN36 of the third inverter. It will be done.

MP36. When the gate terminal of MN36, that is, the input of the third inverter IV3, is charged and its potential changes from the GND potential to the VDD potential, the voltage flows from the output terminal Q through the N-channel MOS transistor of the MN36 to the GND terminal of the third inverter IV3. A current flows, and the potential of the pressure terminal Q changes from the VDDti level to the GNDt level. Further, when the potential of the data output terminal Q changes from about GNDt to about VDDtJ, the transistor M of the third inverter IV3
P36. When φ2 becomes VDD, the charge stored in the gate terminal of MN36 becomes MN35. A current flows through the two N-channel MOS transistors of MN32 to the GND terminal of the first inverter IV1, and the input terminal of the third inverter IV3 (MP36, the gate terminal of MN36) transitions from the VDD potential to the GND potential. As a result, V.D.
Current flows from the D terminal through the MP36 to the output terminal Q,
The potential of the output terminal Q transitions from the GND potential to the VDD potential.

Opening at the time of transition when the potential of the output terminal Q changes from the GND potential to the DD potential or from the VDD potential to the GND potential is governed by the ease with which each of the above-mentioned currents flows. The carriers of N-channel MOS transistors are electrons, and the carriers of P-channel MOS transistors are holes, so P-channel MOS transistors are generally used in the same semiconductor technology.
Compared to N-channel MOS transistors, transistors have a longer current flow and rise time, especially at VD.
If there are multiple P-channel MOS transistors in the current path from the D terminal, the rise time will be very long.

In the flip-flop shown in FIG. 3, the VDD terminal is connected to the transistor MP36 MN36 of the third inverter IV3.
2 of MP32 and MP35 in the current path to the gate terminal of
Since there are two P-channel MOS transistors, MP3
6. There is a drawback that the rise time of the gate terminal of MN36 becomes very long, and as a result, the fall time of the 8-power terminal Q becomes very long.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a CMo5 elliptical master-slave type flip-flop having a short operating time.

Another object of the present invention is to provide a CMOS master-slave flip-flop without a P-channel transistor between the nodes of the master flip-flop and slave flip-flop.

[Means to solve the problem]

According to the present invention, the pair of input/output nodes of the first flip-flop circuit of the CMo5 ellipse, the second flip-flop 71 circuit of the CMo6 ellipse, and the first flip-flop circuit are connected to the second flip-flop circuit. A first pair of transfer gates formed by N-channel MOS transistors respectively connected to a pair of input/output nodes of a flip-flop circuit, and a pair of input/output nodes of the first flip-flop circuit connected to true complementary data input terminals, respectively. a second transfer gate pair formed by connected N-channel MOS transistors;
means for respectively connecting a pair of input/output nodes of the flip-flop circuit to true complementary data output terminals; means for activating the first flip-flop circuit in response to a first clock signal; means for activating the second flip-flop circuit in response to a clock signal; means for turning on the first pair of transfer gates in response to a first clock signal; Second
and means for turning on a pair of transfer gates.

In a more specific aspect of the present invention, a first N-channel MOS transistor is connected between one of the pair of true complementary data input terminals and the first node, and a first N-channel MOS transistor is connected between the other of the pair of data input terminals and the second node. A second N-channel MOS transistor is connected between the first and second N-channel MOS transistors.
The gate terminal of the OS transistor is connected to the first clock input terminal, the third N-channel MOS transistor is connected between the GND terminal and the third node, and the third N-channel MOS transistor is connected between the GND terminal and the third node.
The gate terminal of the channel MOS transistor is connected to the second clock input terminal, a fourth N-channel MOS transistor is connected between the first node and the third node, and the gate terminal of the fourth N-channel MOS transistor is connected to the second clock input terminal. The terminal is connected to the second node, a fifth N-channel MOS transistor is connected between the second node and the third node, and the gate terminal of the fifth N-channel MOS transistor is connected to the first node. connected to the VDD terminal and the first. Second
between the first and second nodes. Second P-channel MOS transistors are connected to the first . Second P channel M
OS) The gate terminal of the Lancistor is the second. Sixth and seventh terminals are connected to the first node, respectively, and are connected to one and the other of the data output terminals of the true complement of the first and second nodes.
N-channel MOS? - transistors are respectively connected, and the sixth. The gate terminals of the seventh N-channel MOS transistor are both connected to the second clock input terminal, and the eighth N-channel MOS transistor is connected between the fourth node and the GND terminal.
- the gate terminal of the eighth N-channel MOS transistor is connected to the first clock input terminal, and the ninth and tenth N-channel MOS transistors are connected between the node 4 and one and the other of the data output terminals; The transistors are connected respectively to the ninth and tenth N-channel M
The gate terminals of the OS transistors are connected to the other and one of the data output terminals, respectively, and the third and fourth P-channel MoS transistors are connected between the VDD terminal and one and the other of the data output terminals, respectively. The gate terminal of the fourth P-channel MOS transistor is connected to the other and one of the data output terminals, respectively, and the first clock signal and the second clock signal are clock signals that do not overlap with each other. A master-slave type flip-flop is obtained.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention. The data input terminals and D are input terminals for data signals, and D is the negative value of D. Output terminals Q and Q are data signal output terminals, and Q
is the negative value of Q.

φ1. φ2 is a clock signal, and as shown in FIG. 2, it is a complementary lock signal that does not overlap with each other. N-channel MOS transistor NM forming the transfer gate
The gate terminals of I and MN2 are connected to the clock signal φ1, and the source terminals are connected to the data input terminal D, respectively. Input/output node 1 of master flip-flop FF1
, 2 and the input/output nodes Q, Q of the slave flip-flop FF2) - the gate terminals of the transistors MN6 and MN7 are connected to the clock signal φ2, and the source terminals are
It is connected to the train terminals of I and MN2, and its drain terminals are connected to the output terminals Q and Q, respectively. The gate terminals of N-channel MOS transistors MN3 and MN8 for respectively activating both flip-flops FFI and FF2 are connected to clock signals φ2. φ1, its source terminal is connected to the GND terminal, and its drain terminals are connected to nodes 3 and 4, respectively.

P channel M forming master flip-flop FFI
OS transistor MP1. MP2 source terminal is VDD
terminal, and the gate terminal is connected to node 2. At node l,
The drain terminals are connected to node 1 and node 2, respectively,
N-channel MOS transistor MN4. MN5 is connected between nodes 1 and 2 and 3, respectively, and their gate terminals are connected to nodes 2 and 1, respectively. On the other hand, Slave Flip 70 Tsubu FF2
The P-channel MO3 transistor MP3. MP
4 is an N-channel transistor MN9. between the VDD terminal and the output terminal Q. MNlo is connected between output terminals Q and Q and node 4, respectively. The gate terminals of MN9 and MP3 are connected to Q, and the gate terminals of MNIO and MP4 are connected to output terminal Q, respectively. The operation of the master-slave type flip-flop having such a configuration will be explained below.

The clock signal φ1 is at VDD potential, and the input signal is at VDD potential.
At position t, when D is at GND potential, clock signal φ2 is at GN
D potential, and MN3. MN6MN7 is OFF state MN
I and MN2 are in the ON state. Therefore, flip-flop FFI becomes inactive, and nodes 1 and 2 are disconnected from output terminals Q and Q and connected to input terminal D. At this time, the node 1 attempts to transition to the VDD potential, and the node 2 attempts to transition to the GNDt potential. Then, MPI goes to ON state and MP2 goes to OFF state, so finally node 1 goes to VDDi level and node 2 goes to G
6 Next, when the clock signal φ1 goes to the GND potential and goes to φ2 or VDDiii, the MN11MN2 goes into the OFF state and the MN3 goes into the ON state. MN3 is ON
When this happens, flip-flop FF1 is activated and node 1 is at VDD potential and node 2 is at GNDt.
MPI, MN5 are in ON state, MP2, MN4 are OFF
state, and the potential state of node 1.2 is maintained. That is, the input data signal D at the falling edge of φ1 is held in the master flip-flop FFI.

In the above explanation, the input signal is at VDD potential and D is at GND potential.
However, it is exactly the same when D is the GND potential and D is the VDD potential.

MNI and MN2 in the above explanation. MN3. MN4, MN5
．． The part consisting of MP1 and MP2 is the master part of the master-slave type flip-flop of the present invention, and the remaining MN6. MN7, MN8. MN9. MNIO,
MP3. The part composed of MP4 is the slave part.

As for the slave section, φ1 and φ2 of the master section are exchanged, and the operation is exactly the same as that of the master section. Therefore, when φ2 transitions to the VDD potential, the potential of node 1.2 is transmitted to the output terminals Q, Q. Also, φ
When l is at the VDD potential, the potential state of the slave section is maintained.

As explained above, with the circuit configuration of FIG. 1, the input data signal D is φ as shown in the timing diagram of FIG.
It is taken in at the falling edge of φ2, held in the master-slave type flip-flop of the present invention, and outputs data signals Q and Q at the rising edge of φ2. Here, the rise time and fall time of the output signals Q and F will be explained. The current path when the output signal Q transitions from the VDD potential to the GND potential is the N-channel MOS transistor M.
N6. MN4. This is a route that passes through MN3 and reaches the GND terminal. At this time, Q transitions from GND potential to VDD potential, but this is because the output terminal Q transitions to GND potential and P
Channel MOS transistor MP4 turns on,
This is because Q transitions to the VDD potential. Output signal Q is G
When changing from ND potential to VDD potential, output terminal Q
The VDD potential of N-channel MOS transistor MN7.
MN5. Discharged to GND terminal through MN3 and connected to GND
Q becomes the VDD potential through the P-channel MOS transistor MP3, which is turned on. As described above, there is at most one P-channel MOS transistor in the current path that governs the rise time and fall time of the output terminals Q and Q. Therefore, the rise time and fall time of the master-slave type flip-flop of the present invention can be made shorter than the conventional master-slave type flip-flop.

〔Effect of the invention〕

As explained above, in the master-slave type flip-flop according to the present invention, only one P-channel MOS transistor exists in the current path that governs the rise and fall times of the output signal. can be made shorter. Therefore, the master-slave type flip-flop of the present invention has the advantage of being able to operate at high speed.

data input signal, Q, Q...data specific power signal, φ.

φ2...Clock signal.

Claims (1)

[Claims] A first flip-flop circuit with a CMOS structure and a CMOS
A second flip-flop circuit with an S structure, and a second flip-flop circuit formed by an N-channel MOS transistor that connects a pair of input/output nodes of the first flip-flop circuit to a pair of input/output nodes of the second flip-flop circuit, respectively. 1 transfer gate pair, a second transfer gate pair formed of N-channel MOS transistors connecting the pair of input/output nodes of the first flip-flop circuit to true complementary data input terminals, and the second flip-flop circuit. means for respectively connecting a pair of input/output nodes of the flip-flop circuit to the data output terminals of the true complement; means for activating the first flip-flop circuit in response to a first clock signal;
means for activating the second flip-flop circuit in response to a clock signal; means for turning on the first transfer gate pair in response to a first clock signal; and means for turning on the second pair of transfer gates.