JPH08213884A - Mos static flip-flop - Google Patents

Abstract

PURPOSE: To reduce the number of transistors(TRs) in the MOS static flip-flop. CONSTITUTION: In the case of D-flip-flop, CMOS inverters IV1 to IV6 and control switches S1 to S4 are connected as shown in the figure, P-channel MOS TRs are adopted for the switches S1 , S4 and N-channel MOS TRs are adopted for the switches S2 , S3 . The TRs of the switches S1 to S4 are controlled by a clock signal ϕ. The TRs for the switches S2 , S3 with a higher threshold voltage are adopted for the N-channel MOSFET NH of the inverter IV2 and the P-channel MOSFET PH of the inverter IV4 . A circuit section including the S2 , IV3 and a circuit section including the S4 and IV5 may be CMOS inverters with a lower drive capability than those of the IV1 , IV2 . This invention is applicable to a T-flip-flop.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS type static flip-flop, and in particular, in a D (delay) -flip-flop [hereinafter abbreviated as D-FF], data transfer between inverters is controlled by one-phase clock signal. By doing so, the number of transistors is reduced.

[0002]

2. Description of the Related Art Conventionally, a D-FF of this type is shown in FIG.
The following are known. The circuit of FIG. 5 corresponds to one D-FF cell in the MOS integrated circuit integrated on one semiconductor chip.

First inverter I for receiving input data D
A control switch S ₁ having a configuration in which a P-channel MOS type transistor P ₁ and an N-channel MOS type transistor N ₁ are connected in parallel is connected to the output side of V ₁ , and the second inverter IV ₂ includes a switch S ₁ It is adapted to receive the output of the inverter IV ₁ when it is turned on.

The third inverter IV ₃ is an inverter I
It intended to receive the output D 'of V _2, the output side, the control switch S ₂ of the same configuration as the switch S ₁ is connected. The output of the inverter IV ₃ is input to the inverter IV ₂ when the switch S ₂ is on.

A control switch S ₃ having the same structure as the switch S ₁ is connected to the output side of the inverter IV ₂ , and the fourth inverter IV ₄ outputs the output D of the inverter IV ₂ when the switch S ₃ is turned on. 'Is received.

The fifth inverter IV ₅ is an inverter I
It receives the output of V ₄ , and a control switch S ₄ having the same configuration as the switch S ₁ is connected to the output side thereof. The output of the inverter IV ₅ is input to the inverter IV ₄ when the switch S ₄ is on.

The sixth inverter IV ₆ is an inverter I
The output of V ₄ is inverted and the inverted output is sent as output data Q. When the output data NQ corresponding to the inverted data of the output data Q is required, the output of the inverter IV ₄ may be derived.

The seventh inverter IV ₇ inverts the clock signal φ and outputs a clock signal Nφ having a reverse phase. The clock signal φ is supplied to the gates of the P-channel MOS type transistors of the switches S ₁ and S ₄ and the gates of the N-channel MOS type transistors of the switches S ₂ and S ₃ . In addition, the clock signal Nφ
Is supplied to the gates of the N-channel MOS type transistors of the switches S ₁ and S ₄ , and the switches S ₂ and S 4.
It is supplied to the gate of the ₃ P-channel MOS type transistor.

Each of the inverters IV _{1 to} IV ₇ is composed of a CMOS (complementary MOS) type inverter IV as shown in FIG. This inverter I
For V, N-channel MOS transistor N ₁₁
And the gate of the P-channel MOS transistor P ₁₁ are both connected to the input wiring L _i , and the drain of the transistor N ₁₁ and the source of the transistor P ₁₁ are both connected to the output wiring L _o . Also, the transistor N
The ₁₁ source, with given reference potential, such as ground potential, the drain of the transistor P ₁₁ is operating potential V _DD
Is given.

When the input signal I supplied to the input wiring L _i becomes "1", the transistors N ₁₁ and P ₁₁ are turned on and off, respectively, and the output signal N obtained from the output wiring L _o.
I becomes "0". When the input signal I becomes “0”, the transistors N ₁₁ and P ₁₁ are turned off and on, respectively, and the output signal NI becomes “1”.

FIG. 7 shows various signal waveforms of the circuit of FIG. 5, and the operation of the circuit of FIG. 5 will be described with reference to FIG.

First, at time t _1, clock signals φ and N
When φ becomes “0” and “1” respectively, the switch S ₁
Is turned on, the input data D = "1" is transferred from the inverter IV ₁ to the inverter IV ₂ , and the inverter I
The output D'of V ₂ becomes "1". At this time, the output D '=
"1" is input to the inverter IV ₃ , but switch S
_{Since 2} is off, the output "0" of the inverter IV ₃ is not input to the inverter IV ₂ . Further, the switch S _{3 is} also off, and the output D ′ = “1” is not input to the inverter IV ₄ .

Next, at time t ₂ , clock signals φ and Nφ
When each of them becomes "1" and "0", the switch S ₁ is turned off and the switches S ₂ and S ₃ are both turned on. Therefore, the output D'of the inverter IV ₂ =
"1" is transferred to the inverter IV _4, the output Q of the inverter IV ₆ becomes "1" accordingly. Further, the output “0” of the inverter IV ₃ which receives the output D ′ = “1”
Is input to the inverter IV ₂ via the switch S _2, the inverter IV ₂ maintains the state of the output D '= "1". At this time, the output of the inverter IV ₄ "0" is input to the inverter IV _5, since the switch S ₄ is in the OFF state, the output of the inverter IV ₅ "1" is not input to the inverter IV _4.

After the time t ₂ , when the switches S ₂ and S ₃ are in the ON state, even if the input data D changes from "1" to "0", the switch S ₁ is in the OFF state, so that the inverter The output D ′ of IV ₂ does not change and remains “1”. Therefore, the output Q also remains "1".

Next, at time t ₃ , clock signals φ and Nφ
Switches to "0" and "1" respectively, switches S ₁ ,
S ₄ is the switch S _2, S ₃ with the ON state is turned off. Therefore, the output “1” of the inverter IV ₅
Is input to the inverter IV ₄ via the switch S ₄ ,
The inverter IV ₄ maintains the state of the output = “0”, and therefore the output Q also maintains the state of “1”. At this time, since the input data D is “0”, the output of the inverter IV ₁ =
“1” is transferred to the inverter IV ₂ via the switch S ₁ , and the output D ′ becomes “0” accordingly.

When the input data D changes from "0" to "1" or from "1" to "0" while the switches S ₂ and S ₃ are off after the time t _3. Although the output states of the inverters IV ₂ and IV ₃ change in response to such a change, the output state of the inverter IV ₄ does not change, and thus the state of the output Q does not change.

After this, at time t ₄ , clock signals φ and N
When φ becomes “1” and “0” respectively, the switch S
_The switches S ₂ and S ₃ are turned on while the switches ₁ and S ₄ are turned off. Therefore, the output of the inverter IV ₃ "1" is input to the inverter IV ₂ via the switch S _2, the inverter IV ₂ maintains the state of the output D '= "0". Further, since the output D ′ = “0” is transferred to the inverter IV ₄ via the switch S ₃ , the inverter IV
The output Q of ₆ becomes "0".

The operation after time t ₅ is performed in the same manner as described above. According to the circuit of FIG. 5, the input data D can be taken in at the rising edge of the clock signal φ and the taken-in data can be held until the next rising edge of the clock signal φ.

[0019]

According to the above-mentioned conventional technique, since 22 transistors are required for each D-FF cell, the cell size is increased and the chip size is increased.

Further, since each control switch is composed of two MOS type transistors, the number of clock inputs is as many as two, that is, eight in total for each control switch. Therefore,
It is not suitable for high speed operation because the input capacity becomes large.

On the other hand, a data transfer circuit as shown in FIG. 8 is known, and by applying this data transfer circuit as shown in FIG.
It is conceivable to construct F.

The circuit of FIG. 8 has an N-channel MOS type transistor N ₂₁ and a P-channel MOS type transistor P.
A first inverter IV ₂₁ containing _21, N-channel MO
S-type transistor N ₂₂ , N-channel MOS type transistor N ₂₃ and P-channel MOS type transistor P _H
And a second inverter IV ₂₂ including a control signal SC
Accordingly, when the transistor N ₂₂ is turned on, the output of the inverter IV ₂₁ is transferred to the inverter IV ₂₂ .

In such a circuit, when the transistor N ₂₂ turns on when the transistor N ₂₁ is off, the potential at the point X, which is the gate connection point of the transistors N ₂₃ and P _H , is only up to V _DD -V _TN. I can't go up. Where V _DD is
The source potentials of the transistors P ₂₁ and P _H , V _TN, are the threshold voltage of the transistor N ₂₂ . Therefore, when the threshold voltage of the transistor P _H has a value close to V _TN , the transistor P _H cannot be turned off sufficiently and a leak current flows. Therefore, the threshold voltage value of the transistor P _H is set larger than V _TN (for example, 1.4).
(About V) so that the transistor P _H is sufficiently turned off.

The D-FF of FIG. 9 is intended to reduce the number of transistors by applying such an idea to the D-FF of FIG. That is, the control switch S ₁ ~
Each of S ₄ is composed of only N-channel MOS type transistors, and the P-channel MOS type transistors P _H forming the inverters IV ₂ and IV ₄ have higher threshold voltages than those of S ₁ and S ₃ . 2 transistors per cell
The number is reduced from 2 to 18. This makes it possible to reduce the cell size or the chip size and the number of clock inputs, but it is desirable to further reduce the number of transistors.

As a measure for reducing the number of transistors, it is possible to prepare the clock signal Nφ outside the cell and supply it to each cell. This would give an additional 2 per cell.
The number of transistors (inverter IV ₇ ) can be reduced.
However, it is necessary to provide a wiring for routing the clock signal Nφ to each cell, which causes a problem that a chip area increases and a delay time difference occurs between the clock signals φ and Nφ.

An object of the present invention is to provide a novel MOS type static flip-flop in which the number of transistors is reduced without causing such a problem.

[0027]

A MOS type static flip-flop according to the present invention is a MOS type first inverter and a MOS having a first conductivity type channel.
A first control switch comprising a transistor
A second CMOS type inverter controlled by a one-phase control signal and a second CMOS type inverter which receives the output of the first inverter when the first control switch is turned on. A transistor having a channel of a second conductivity type opposite to the first conductivity type has a higher threshold voltage than a transistor forming the first control switch, and receives an output of the second inverter. A CMOS type third inverter and an MO having the second conductivity type channel.
A second control switch formed of an S-type transistor, the second control switch being controlled by the control signal and being turned on by the third control switch.
Which inputs the output of the inverter to the second inverter, and a third control switch composed of a MOS transistor having a channel of the second conductivity type, which is controlled by the control signal. A fourth CMOS type inverter that receives the output of the second inverter when the third control switch is turned on, and has the first conductivity type channel among the two MOS type transistors forming the inverter. Has a threshold voltage higher than that of the transistor forming the third control switch, a fifth CMOS type inverter for receiving the output of the fourth inverter, and a MOS type transistor having the first conductivity type channel. A fourth control switch consisting of: The output of the serial fifth inverter is obtained a one to be input to the fourth inverter.

[0028]

According to the structure of the present invention, each of the first to fourth control switches is composed of one MOS type transistor and is controlled by a one-phase control signal. Therefore, the number of transistors is 18 per cell. It is possible to reduce the number to less than or equal to one and to eliminate the problems associated with the use of the two-phase clock.

[0029]

1 is a block diagram of a D-FF according to an embodiment of the present invention.
The same parts as those in FIGS. 5 and 9 are designated by the same reference numerals, and detailed description thereof will be omitted.

The D-FF of FIG. 1 is characterized in that the data transfer circuit as shown in FIGS. 8 and 10 is used to control the data transfer between the inverters by a one-phase clock signal. is there.

The circuit of FIG. 10 is based on the concept of the circuit of FIG.
It is applied to data transfer by the channel MOS transistor P ₂₂ . The inverter IV ₂₁ is the same as that described in FIG. 8, and the inverter IV ₂₃ includes the N-channel MOS type transistor N _H and the P-channel M.
It includes an OS type transistor P ₂₃ . Control signal S
When the transistor P ₂₂ is turned on by C ′, the output of the inverter IV ₂₁ is transferred to the inverter IV ₂₃ .

In such a circuit, when the transistor P ₂₂ turns on while the transistor N ₂₁ is on, the potential at the point Y, which is the gate connection point of the transistors P ₂₃ and N _H , rises to V _SS + V _TP. Will end up. Where V _SS is
The source potentials of the transistors N ₂₁ and N _H , V _TP, is the threshold voltage of the transistor P ₂₂ . Thus, the threshold voltage of the transistor N _H is the is close to V _TP, the transistor N _H can not be sufficiently off. Therefore, so that the transistor N _H is turned off sufficiently by setting larger than the threshold voltage of the transistor N _H to V _TP.

In the circuit of FIG. 1, the control switch S ₁ is composed of only P-channel MOS type transistors and
Controlled by the phase clock signal φ, the N-channel MOS type transistor N _H of the inverter IV ₂ has a higher threshold voltage than the transistor as S ₁ . Therefore, normal operation is ensured by the principle described in FIG. Also, the control switch S ₃ and the control of the 1-phase clock signal φ with consist only of N-channel MOS transistor, the threshold voltage is higher than the transistor as S ₃ as P-channel MOS transistor P _H of the inverter IV ₄ I am using one. Therefore, normal operation is ensured by the principle described in FIG.

Since the control switch S ₂ operates in synchronization with the switch S ₃ , it is composed of only N-channel MOS type transistors and is controlled by the one-phase clock signal φ, like S ₃ . Further, the control switch S ₄ is
Since it operates in synchronization with the switch S ₁ , S ₁
In the same manner as the above, it is composed of only P-channel MOS type transistors and is controlled by a one-phase clock signal φ.

The D-FF of FIG. 1 operates similarly to the D-FF of FIG. According to the D-FF of FIG. 1, the number of transistors is 16, and the cell size or chip size can be reduced. Further, since the number of clock inputs is as small as four and the input capacity is reduced, high speed operation is possible. Further, since the clock signal has one phase, 2
There are no problems with using a phase clock. When only the output data NQ corresponding to the inverted output of the output data Q is used, the inverter IV ₆ can be omitted and the number of transistors is further reduced by 2.

In the circuit of FIG. 1, an output NQ is supplied as an input of the inverter IV ₁ instead of the input data D as shown by a broken line BL ₁ , and a one-phase clock is used as a control signal for each switch of S _{1 to} S _4. When a one-phase trigger signal is supplied instead of the signal φ, a T (trigger or toggle) -flip-flop [hereinafter abbreviated as T-FF] can be realized.

FIG. 2 shows a modification of the circuit shown in FIG. 1. The same parts as those in FIG. 1 are designated by the same reference numerals and detailed description thereof will be omitted.

The characteristic feature of the D-FF in FIG. 2 is that
Inverter IV₂ And control switch S₃CMOS type between
Inverter IV₈  Equipped with an inverter IV_Four On the output side of
Inverter IV₆ Is the loss. In this case,
Inverter IV_Four When the output data Q is obtained from the output side of
Both inverters IV_Four Output data NQ is obtained from the input side of
Can be

Also in the circuit of FIG. 2, T-FF can be realized by supplying the output NQ as the input of the inverter IV ₁ and supplying the trigger signal instead of the clock signal φ as shown by the broken line BL _2. .

FIG. 3 shows a D- according to another embodiment of the present invention.
The FF is shown, and the same portions as those in FIG. 1 are denoted by the same reference numerals and detailed description thereof will be omitted.

The D-FF of FIG. 3 differs from the D-FF of FIG. 1 in that the control switch S ₂ and the inverter IV _{3 of} FIG.
₁ is provided with a CMOS type inverter IV ₃₁ whose drive capability is lower than that of the inverter IV _{1 in place of the} circuit section including
In place of the circuit section including the control switch S ₄ and the inverter IV ₅ , the CMOS whose drive capability is lower than that of the inverter IV ₂
A type inverter IV ₅₁ is provided. Inverter I
As V ₃₁ and IV _51, it is possible to use those in which the driving capability is reduced by increasing the channel length L and decreasing the channel width W.

In the configuration of FIG. 3, when the control switch S ₁ is turned on, the potential of the input point Z ₁ of the inverter IV ₂ is determined according to the output of the inverter IV ₁ , and when the control switch S ₃ is turned on. Input point Z _{2 of} IV ₄
Is determined according to the output of the inverter IV ₂ .

According to the D-FF of FIG. 3, the D-FF of FIG.
Compared with, the number of transistors is reduced by 2 and the number of transistors is 14. Therefore, it is possible to further reduce the cell size or the chip size and further increase the speed.

Also in the circuit of FIG. 3, when the output NQ is supplied as the input of the inverter IV ₁ and the trigger signal is supplied instead of the clock signal φ as shown by the broken line BL ₃ , T-FF can be realized. .

FIG. 4 shows a modification of the circuit shown in FIG. 3, and the same parts as those in FIG. 3 are designated by the same reference numerals and detailed description thereof will be omitted.

[0046] It is a feature of the D-FF in FIG. 4, a CMOS inverter IV ₈ provided between the inverter IV ₂ and the control switch S _3, it lost inverter IV ₆ of the output side of the inverter IV ₄ Is. In this case, as the inverter IV ₅₁ , one having a lower drive capacity than the inverter IV ₈ is used. According to D-FF in FIG. 4, the output data NQ from the input side of the inverter IV ₄ together with the output data Q from the output side of the inverter IV ₄ is obtained can be obtained.

Also in the circuit of FIG. 4, T-FF can be realized by supplying the output NQ as the input of the inverter IV ₁ and supplying the trigger signal instead of the clock signal φ as shown by the broken line BL _4. .

The present invention is not limited to the above embodiments, but can be implemented in various modified forms. For example, Nφ is used instead of φ as a clock signal, and the channel conductivity type of the transistors forming the control switches S _{1 to} S ₄ is opposite to that shown in the figure, and the inverter IV ₂ is a P-channel transistor and the inverter IV ₄ is a transistor. Each N-channel transistor may have a high threshold voltage.

[0049]

As described above, according to the present invention, the MO
Since the number of transistors forming the S-type static flip-flop is significantly reduced, the cell size or the chip size can be reduced.

Further, since each control switch is composed of one transistor and is controlled by a one-phase control signal, it is possible to operate at high speed and avoid disadvantages associated with the use of a two-phase control signal. There is also.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a circuit configuration of a D-FF according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a modified example of the circuit of FIG.

FIG. 3 is a circuit diagram showing a circuit configuration of a D-FF according to another embodiment of the present invention.

FIG. 4 is a circuit diagram showing a modified example of the circuit of FIG.

FIG. 5 is a circuit diagram showing a circuit configuration of a conventional D-FF.

FIG. 6 is a circuit diagram showing a circuit configuration of a CMOS inverter.

FIG. 7 is a signal waveform diagram for explaining the operation of the circuit of FIG.

FIG. 8 is a circuit diagram showing a data transfer circuit using N-channel MOS type transistors.

9 is a circuit diagram showing a circuit configuration of a D-FF configured by using the circuit of FIG.

FIG. 10 is a circuit diagram showing a data transfer circuit using P-channel MOS type transistors.

[Explanation of symbols]

_{IV 1 ~IV 8, IV 31,} IV 51: CMOS inverter, S ₁ ~S _4: control switch.

Claims (4)

[Claims] 1. A first control switch comprising a CMOS first inverter and a MOS transistor having a first conductivity type channel, which is controlled by a one-phase control signal. A second CMOS-type inverter that receives the output of the first inverter when the first control switch is conductive, and is a second inverter of the two MOS-type transistors that constitutes the inverter and is opposite to the first conductivity type. A transistor having a conductivity type channel has a higher threshold voltage than a transistor constituting the first control switch, and a CMOS type third transistor which receives an output of the second inverter.
And a second control switch comprising a MOS transistor having a channel of the second conductivity type, the output of the third inverter being controlled by the control signal and being turned on to the second inverter. An input, a third control switch including a MOS transistor having the second conductivity type channel, which is controlled by the control signal, and the second control switch when the third control switch is conductive. A fourth CMOS-type inverter that receives the output of the inverter, and one of the two MOS-type transistors forming the inverter, which has the channel of the first conductivity type, forms the third control switch. One having a higher threshold voltage and a CMO receiving the output of this fourth inverter S-type fifth
And a fourth control switch including a MOS transistor having the first conductivity type channel, which is controlled by the control signal and outputs the output of the fifth inverter to the fourth inverter when conducting. MOS type static flip-flop with input. 2. A first control switch comprising a CMOS first inverter and a MOS transistor having a first conductivity type channel, which is controlled by a one-phase control signal. A second CMOS-type inverter that receives the output of the first inverter when the first control switch is conductive, and is a second inverter of the two MOS-type transistors that constitutes the inverter and is opposite to the first conductivity type. A transistor having a conductivity type channel has a higher threshold voltage than a transistor constituting the first control switch, and a CMOS type third transistor which receives an output of the second inverter.
And a second control switch composed of a MOS transistor having a channel of the second conductivity type, the output of the third inverter being controlled by the control signal and being turned on to the second inverter. What is input, and a fourth CMOS type that receives the output of the second inverter
And a third control switch comprising a MOS transistor having a channel of the second conductivity type, the third control switch being controlled by the control signal, and the fourth control switch when the third control switch is conductive. A fifth CMOS-type inverter for receiving the output of the inverter, wherein one of the two MOS-type transistors forming the inverter, which has the channel of the first conductivity type, is better than the transistor forming the third control switch. One having a high threshold voltage and one CMOS type sixth receiving the output of this fifth inverter
And a fourth control switch composed of a MOS transistor having the first conductivity type channel, which is controlled by the control signal and outputs the output of the sixth inverter to the fifth inverter when conducting. MOS type static flip-flop with input. 3. A first control switch composed of a first CMOS-type inverter and a MOS-type transistor having a first conductivity type channel, which is controlled by a one-phase control signal. A second CMOS-type inverter that receives the output of the first inverter when the first control switch is conductive, and is a second inverter of the two MOS-type transistors that constitutes the inverter and is opposite to the first conductivity type. A transistor having a conductivity type channel has a threshold voltage higher than that of the transistor forming the first control switch, and an output of the second inverter is inverted, and the inverted output is input to the second inverter. A third CMOS-type inverter having a lower drive capacity than the first inverter; and a second conductivity type channel. A second control switch consisting of a MOS transistor having a switch, which is controlled by the control signal, and a CMOS type fourth switch which receives the output of the second inverter when the second control switch is conductive. Of the two MOS type transistors forming the inverter, the one having the channel of the first conductivity type has a higher threshold voltage than the transistor forming the second control switch, A fifth CMOS-type inverter for inverting the output of the fourth inverter and inputting the inverted output to the fourth inverter, the fifth-type CMOS inverter having lower drive capability than the second inverter. flip flop. 4. A first control switch composed of a first CMOS-type inverter and a MOS-type transistor having a channel of the first conductivity type, which is controlled by a one-phase control signal. A second CMOS-type inverter that receives the output of the first inverter when the first control switch is conductive, and is a second inverter of the two MOS-type transistors that constitutes the inverter and is opposite to the first conductivity type. A transistor having a conductivity type channel has a threshold voltage higher than that of the transistor forming the first control switch, and an output of the second inverter is inverted, and the inverted output is input to the second inverter. A third CMOS-type inverter having a lower drive capacity than the first inverter, and a second inverter Fourth CMOS type that receives power
And a second control switch composed of a MOS transistor having a channel of the second conductivity type, the second control switch being controlled by the control signal, and the fourth control switch when the second control switch is conductive. A fifth CMOS-type inverter that receives the output of the inverter, of the two MOS-type transistors that form the inverter, the one that has the channel of the first conductivity type is better than the transistor that forms the second control switch. A sixth CMOS type inverter having a high threshold voltage, inverting the output of the fifth inverter and inputting the inverted output to the fifth inverter, the driving capability of which is higher than that of the fourth inverter. MOS-type static flip-flop with low and low.