JP2728719B2 - Variable frequency divider - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a variable frequency dividing circuit in a semiconductor integrated circuit or the like.

(Prior art) Conventionally, as a technique in such a field, there is a proposal of the IEICE General Conference, S7-4 (Showa 56), written by Yamashita, Kaji, Tota, Sekine, "1GH _Z direct feedback type 2-modulus". Prescaler
MSI "P.3-264 to 3-365. Hereinafter, the configuration will be described with reference to the drawings.

FIG. 2 is a configuration diagram showing one configuration example of a conventional variable frequency dividing circuit.

The variable frequency dividing circuit includes three stages of cascade-connected delay flip-flops (hereinafter, referred to as D-FFs) 1, 2, and 3,
The feedback signal S3 and the operation mode signal MC output from the positive-phase output terminal Q3 of the final stage D-FF3 are connected to a two-input AND gate 4. D-FF1,2,3 are clock signals CK
From a high level (hereinafter “H”) to a low level (hereinafter “H”).
It has a function of taking in input data in synchronization with the fall to “L” and outputting data in accordance with the input data. The output signal S4 of the AND gate 4 and the feedback signal S2 output from the in-phase output terminal Q2 of D-FF2 are connected to a two-input NOR gate 5, and the output signal S5 of the NOR gate 5 is used as the first stage D signal. Connected to input terminal D1 of -FF1. Each D-FF1 ~
The three clock terminals C1, C2, C3 are connected to the clock signal CK.

In FIG. 2, Q1,1 are the positive-phase output terminal and negative-phase output terminal of the first stage D-FF1, D2, D3 are the input terminals of D-FF2,3,
Reference numerals 2 and 3 denote negative phase output terminals of the D-FFs 2 and 3, and OUT denotes an output signal of the variable frequency dividing circuit. The truth table of each D-FF1,2,3 is as follows.

When the clock signal CK is “H”, each of the D-FFs 1, 2, and 3 is independent of the logic level of the input terminal D (“H” or “L”).
The logic level of the output terminal Q, holds the previous state. First
When the clock signal CK falls from “H” to “L” and the input terminal D is “H”, the output terminal Q rises from “L” to “H” (at this time, the output terminal becomes “H”). Falling from "H" to "L"). When the next second clock signal CK falls from “H” to “L”, if the input terminal D is “H”, the output terminal Q is in the previous state (that is, Q is “H”). “L”). Thereafter, when the third clock signal CK falls from “H” to “L”, if the input terminal D is “L”, the output terminal Q falls from “H” to “L” (at this time, The output terminal rises from "L" to "H".

In this variable frequency dividing circuit, a ring counter is composed of D-FFs 1 and 2 and an OR gate 5, and a shift register is composed of D-FF3, and performs the following operation.

 FIG. 3 is a timing chart of FIG.

When the operation mode signal MC is “L”, the AND gate 4 having the function of a switch for switching the mode is turned off,
The output signal S4 becomes "L". Then, the OR gate 5 becomes D
− Feedback signal S2 output from FF2 is output signal S5
Is fed back to the D-FF1 in the form of (1), so that the output signal OUT obtained by dividing the clock signal CK by 1/4 is output by the shift operation of the D-FF1 and 2.

When the operation mode signal MC changes to “H”, the AND gate 4
Is turned on, and the feedback signal S through the AND gate 4
3 is applied to the OR gate 5 in the form of an output signal S4. The output signal S4 is supplied to the D-FF1 through the OR gate 5 in the form of the output signal S5.
Is supplied to the input terminal D1. As a result, the feedback signal S2 output from D-FF2 via D-FF1 is shifted by D-FF3, and the output signal OUT obtained by dividing the clock signal CK by 1/5 is output.

(Problems to be Solved by the Invention) However, in the variable frequency dividing circuit having the above configuration, the maximum operating frequency of the circuit is D-FF1, 2, 3, the AND gate 4, and the OR gate 4.
The delay is limited by the sum of the delay times of the gate 5, and especially the feedback signal S3
The delay time of the AND gate 4 and the OR gate 5 to which the input signal is input accounts for a large proportion of the entire circuit, which is a factor that hinders high speed operation.

Therefore, conventionally, in order to solve this problem, a technique of removing the AND gate 4 and adding an AND gate function to the D-FF 3 and clearing the same to perform mode switching (switching of the dividing ratio) is also available. Proposed. However, the feedback signal
Since the OR gate 5 that takes the logical sum of S2 and S3 is required, the operation speed cannot be sufficiently improved due to the delay time due to the OR gate 5, and the circuit formation area and power consumption increase. Has not yet been solved, and a technically satisfactory one has not yet been obtained.

An object of the present invention is to provide a variable frequency dividing circuit which solves the problems of the prior art in terms of lowering operation speed, increasing circuit formation area, and increasing power consumption.

(Means for Solving the Problems) In order to solve the problems, claim 1 of the present invention.
According to the invention, in the variable frequency dividing circuit, D-stages of m stages (where m is a positive integer) for taking in the input signal at either the falling edge or the rising edge of the clock signal, respectively.
FFs are cascaded, and the second output signal of the complementary first and second output signals output from the m-th stage D-FF is fed back to the first stage D-FF. And a ring counter which receives the input signal at one of the falling edge and the rising edge of the clock signal.
D-FFs of stages (where n is a positive integer) are cascaded to the output side of the ring counter, and the first output signal is input to the D-FF of the first stage, From the output side of the D-FF of the complementary first and second logic levels (for example,
A shift register that outputs a feedback signal having “H” and “L”).

Then, the first stage D-FF of the ring counter is flip-flop operated by the second logic level of the feedback signal, and the first stage D-FF of the ring counter is operated by the first logic level of the feedback signal. And the flip-flop operation of the n-stage D-FFs of the shift register according to the second logic level of the operation mode signal having the complementary first and second logic levels, Set or reset the n-stage D-FF of the shift register according to the first logical level of the shift register, and switch the frequency division ratio of the clock signal by switching between the first logical level and the second logical level of the operation mode signal. It is configured to switch between 1 / (2m) and 1 / (2m + n) respectively.

According to the invention of claim 2, the D-FF of claim 1 is constituted by a master-slave type D-FF circuit including a master-side flip-flop (hereinafter referred to as FF) and a slave-side FF.

(Operation) According to the present invention, since the variable frequency dividing circuit is configured as described above, for example, when the number of stages of the D-FF is m = n = 1, the ring counter and the shift register each have one stage. It is composed of D-FF with set or reset. When the operation mode signal is at the first logic level, the D-FF of the shift register is set or reset, the feedback signal output from the D-FF is fixed at the second logic level, and the D-FF of the ring counter is set. Perform a normal D-FF operation. Thereby, the clock signal is divided by 1 / (2m) = 1/2. On the other hand, when the operation mode signal is at the second logic level, the D-FF of the shift register performs a normal D-FF operation,
Is supplied to D-FF of the ring counter. The D-FF of this ring counter is set or reset by the first logic level of the feedback signal,
A normal D-FF operation is performed by the second logic level of the feedback signal. Thereby, the clock signal is 1 / (2m + n) =
It is divided by 1/3.

For example, when the number of stages of the D-FF is m = 2 and n = 1, the ring counter has two stages of the D-FF, and the first stage is the D-FF with the set or reset, and the second stage is the D-FF with the reset. Normal D
-FF. The shift register is composed of a one-stage D-FF with set or reset. In the variable frequency dividing circuit having such a configuration, the operation mode signal is set to the first mode.
When the logic level is, the division ratio of the clock signal is 1 / (2m)
= 1/4, and when the operation mode signal is at the second logic level, the frequency division ratio of the clock signal is 1 / (2m + n) = 1/5.

Embodiment FIG. 1 is a configuration diagram of a variable frequency dividing circuit showing a first embodiment of the present invention.

This variable frequency divider circuit sets the frequency division ratio of the clock signal CK to 1 /
(2m) and 1 / (2m + n) (where m and n indicate the number of bits, that is, the number of stages, and in this embodiment, m = n = 1). It comprises a shift register 20 connected to the output side. The ring counter 10 has an input terminal D11, a clock terminal C
11, a set terminal S11, a positive-phase output terminal Q11 for the first output signal S11a, and a negative-phase output terminal 1 for the second output signal S11b
A 1-stage (= m) set D-FF11 having 1 and its input terminal D11 is connected back to the output terminal 11;
Further, the clock terminal C11 is connected to the clock signal CK, and the output terminal Q
11 is connected to the output signal ▲ ▼ of the opposite phase, respectively.

The shift register 20 has an input terminal D21 and a clock terminal C2.
1, set terminal S21, positive phase output terminal Q21, and feedback signal FB
(= N) D-FF21 with a set having an inverted-phase output terminal 21 for input, and its input terminal D21 is connected to an output terminal Q11.
Clock terminal C21 to clock signal CK, set terminal S
21 is connected to an operation mode signal MC for frequency division ratio switching, and the output terminal 21 is connected to a set terminal S11.
The truth table of each set-added D-FF11, 21 is as follows.

When the set terminal S is "L", each of the set-added D-FFs 11 and 21 performs the same operation as a normal D-FF. When the set terminal S is set to “H”, the output terminal Q is fixed to “H” regardless of the logic levels of the clock terminal C and the input terminal D (at this time, the output terminal is fixed to “L”). ).

FIG. 4 is a timing chart of FIG. 1. The operation of FIG. 1 will be described with reference to FIG.

If the operation mode signal MC before the time T0 is “H”, the D-FF21
Is set, and the feedback signal FB on its output terminal 21 is “L”
Becomes Then, the D-FF 11 performs the normal D-FF operation, and at the time t1 when the clock signal CK falls, the input terminal
The “L” of the signal S11b on D11 is captured, and the “L” of the signal S11a is output from the output terminal Q11. At the time of falling of the clock signal CK at the time t2, the signal S11b is taken in “H”.
The FF11 outputs “H” of the signal S11a from the output terminal Q11. Therefore, the D-FF 11 outputs an output signal 信号 obtained by dividing the clock signal CK by か ら from the output terminal Q 11.

At time T0 after elapse of time t3, the operation mode signal MC becomes “L”
Then, the D-FF 21 starts a normal D-FF operation, that is, a shift register operation. Since the output signal S11a is “L” and the output signal S11b is “H” between times t3 and t4, the output signal S11a is “H”, the output signal S11b is “L”, and the output terminal Q21 between times t4 and t5.
Becomes "L", the feedback signal FB becomes "H", D-FF11 is set, the output signal S11a becomes "H", and the output signal S11b becomes "L".
From time t5 to t6, the feedback signal FB becomes “L”, and the setting of D-FF11 is released. Since the output signal S11b is at "L" from time t5 to t6, the output signal S11a is at "L" from time t6 to t7, and the output signal S1
1b becomes “H”, and the output signal ▲ ▼ obtained by dividing the clock signal CK by 3 is output from the output terminal Q11. Thus, when the operation mode signal MC is “H”, the clock signal CK is
1 / (2m) = 1 / (2 x 1) = 1/2 frequency division, when "L", 1 / (2m
+ N) = 1 / (2 × 1 + 1) = 1/3 frequency division is performed.

 This embodiment has the following advantages.

(A) The ring counter 10 and the shift register 20 are configured by the set D-FFs 11 and 12, and the feedback signal FB is directly input to the set terminal S11 of the D-FF 11 having the frequency dividing function without passing through another logic gate. As a result, the delay of signal feedback can be reduced, and the speed of the variable frequency dividing circuit can be increased.

(B) Since it is composed only of D-FF11 and 12 with set,
Since the circuit configuration is simplified, and there is no other logic gate on the feedback signal FB path, the circuit area and power consumption can be reduced when integrated.

FIG. 5 is a configuration diagram of a variable frequency dividing circuit showing a second embodiment of the present invention.

In the first embodiment, m = 1 stage ring counter 10 and n
Although the variable frequency dividing circuit is constituted by the single-stage shift register 20, in the second embodiment, an m-stage ring counter 10 m
And the n-stage shift register 20n constitute a variable frequency dividing circuit, and the frequency dividing ratio of the clock signal CK is 1 / (2m) and 1 / (2m + n)
Can be switched over.

The ring counter 10m has m stages of D-FFs 11-1 to 11-m
Is a cascade-connected configuration, of which only the first stage is a set D-FF 11-1 and the others are ordinary D-FFs 11-2 to 11-m similar to the conventional FIG. D-FF11-1 to 11
Of -m, the D-FF 11-1 with a set at the first stage has a set terminal S, and the input terminal D of the D-FF 11-1 is connected to the negative-phase output terminal of the D-FF 11-m at the last stage. I have. The clock terminals C of the D-FFs 11-1 to 11-m are connected to the clock signal CK, and the positive-phase output terminal Q of the final stage D-FF 11-m is connected to the output signal ▼.

The shift register 20n includes an n-stage set D-FF21-
1 to 21-n are connected in cascade. Each of the set D-FFs 21-1 to 21-n has a clock terminal C for a clock signal CK and a set terminal S for applying an operation mode signal MC, and outputs a reverse-phase output of the final stage D-FF 21-n. Terminal is D
-Connected to the set terminal S of FF11-1.

6 and 7 are for simply explaining the operation of FIG. 5. FIG. 6 is a block diagram of the variable frequency dividing circuit when m = 2 and n = 1, and FIG. 7 is a timing chart of FIG.

In the variable frequency dividing circuit shown in FIG.
The shift register 20n is composed of two stages of a D-FF 11-1 with a set and a normal D-FF 11-2, and the shift register 20n is composed of a D-FF 21-1 with a single stage.

In FIG. 7, when the operation mode signal MC is "H", the D-FF 21-1 in FIG. 6 is set to fix the output terminal Q to "H" and the output terminal to "L". D-FF21-
When the output terminal of 1 is fixed to "L", the shift register
20n is separated from the ring counter 10m.
The FF 11-1 performs a normal D-FF operation, and the D-FF 11-1
And the D-FF 11-2 perform a two-stage counting operation. The clock signal CK is output from the output terminal Q of the D-FF 11-2.
Is output by dividing the frequency by 1 / (2m) = 1/4.

In FIG. 7, when the operation mode signal MC is "L", D
The set of FF21-1 is released, the D-FF21-1 performs a normal D-FF operation, and the D-FF21-1 performs a one-stage shift operation, and the output of the D-FF21-1 is output. The logic level on the terminal repeats "H" and "L". When the output terminal of D-FF 21-1 is "H", D-FF 11-1 is set and its output terminal Q is fixed at "H". When the output terminal of the D-FF 21-1 is "L", the setting of the D-FF 11-1 is released, and the logical level on the output terminal Q changes to "H" and "L".
A two-stage counting operation is performed by the FFs 11-1 and 11-2. As a result, an output signal ▼ obtained by dividing the frequency of the clock signal CK by 1 / (2m + n) = 1 / (2 × 2 + 1) = 1/5 is output from the output terminal Q of the D-FF 11-2.

As described above, in the configuration of FIG. 5, the frequency division ratio of the clock signal CK is changed by switching the operation mode signal MC between “H” and “L”.
It can be switched between 1 / (2m) and 1 / (2m + n). Therefore, a desired frequency division ratio can be easily and accurately obtained by selecting the number of stages m and n.

FIG. 8 is a configuration diagram of a variable frequency dividing circuit showing a third embodiment of the present invention.

This variable frequency dividing circuit includes a ring counter 30 and a shift register 40 connected to its output node N2,2.

The ring counter 30 is composed of a one-stage (= m) set master / slave type D-FF circuit that takes in input data in synchronization with the falling of the clock signal CK. , The master FF 30a and the slave FF 30b connected to the output node N1,1. Similarly, the shift register 40 is also composed of a one-stage (= n) set master / slave type D-FF circuit that takes in input data in synchronization with the fall of the clock signal CK. The FF circuit includes a master FF 40a and a slave FF 40b connected to the output nodes N3 and N3. The truth table of the set master / slave type D-FF circuit is the same as that of the set D-FFs 11 and 21 in FIG.

In the ring counter 30, the master-side FF 30a and the slave-side FF 30b include transfer gates 31-1 to 31-8 formed of field-effect transistors (hereinafter, referred to as FETs), latch circuits 32 formed by cross-connecting inverters 32a and 32b,
Latch circuit 3 in which inverters 33a and 33b are cross-connected
3 and inverters 34-1 to 34-4 for an output buffer. Among the transfer gates 31-1 to 31-8, the transfer gates 31-1 to 31-4 have a function of performing on / off operations by the clock signal CK and the negative-phase clock signal ▼ to transfer signals. . The transfer gates 31-5 to 31-8 are turned on and off by a signal (that is, a feedback signal) of the negative-phase output side node 4 of the slave FF 40b in the shift register 40, and set a predetermined node to a constant potential Vh of "H" and a predetermined potential. It has the function of setting the FFs 30a and 30b by setting it to the "L" constant potential Vl.

The transfer gate 31-1 connected to the negative-phase output node 2 is connected to the latch circuit 32 and the inverter 34-1.
The transfer gate 31-2 connected to the transfer gate 31-5 and the output node N2 includes a latch circuit 32, an inverter 34-2, and a transfer gate.
31-6. The output node N1 of the inverter 34-1 is connected to the latch circuit 33, the inverter 34-3, and the transfer gate 31-7 via the transfer gate 31-3.
It is connected to the. The output node 1 of the inverter 34-2 is connected to the latch circuit 33, the inverter 34-4 and the transfer gate 31 via the transfer gate 31-4.
-8.

In the shift register 40, the master FF 40a and the slave FF 40b include transfer gates 41-1 to 41-4 for signal transfer, transfer gates 41-5 to 41-8 for setting, and an inverter, similarly to the ring counter 30 side. 42a, 42
b, a latch circuit 43 composed of inverters 43a and 43b, and inverters 44-1 to 44- for output buffers.
4.

FIG. 9 is a time chart of FIG. 8, and the operation of FIG. 8 will be described with reference to FIG.

From time t1 to t5 (T1), the operation mode signal MC becomes “H”.
And the node 4 is “L”. At this time, the transfer gates 31-5 to 31-8 are turned off, and the variable frequency dividing circuit uses the ring counter 30 to calculate 1 / (2) of the clock signal CK.
m) = 1 / (2 × 1) = 1/2.

When the operation mode signal MC becomes “L” at time t5 (T1), the signal of the output node N2,2 of the ring counter 30 is transmitted to the shift register 40. At the timing of time t7, the output node 4 becomes “H”, and the transfer gates 31-5 to 31-
When 8 is turned on, the ring counter 30 is set. Therefore, from time t7 to t9, the node N1 becomes “L”, the node 1 becomes “H”, the node N2 becomes “H”, and the node 2 becomes “L”. Times of Day
When the node 4 becomes "L" at the timing of t9, the transfer gates 31-5 to 31-8 are turned off, and the set is released. However, since the clock signal CK is “L” from time t9 to t10, the logic level of the node N1,1 remains “L” for the node N1 and “H” for the node 1. Therefore, during two periods of the clock signal CK from time t6 to time t10, the node N1 becomes "L" and the node 1 becomes "H", and the time t7 to t11
Until then, the node N2 is at "H" and the node 2 is at "L", and the clock signal CK is divided by 1 / (2m + n) = 1 / (2 × 1 + 1) = 1/3.

In the third embodiment, when the operation mode signal MC is "H", 1 /
The operation of dividing by 1/3 is performed by dividing the frequency by 2 and MC at "L". Further, in this variable frequency dividing circuit, since the ring counter 30 and the shift register 40 are composed of a master / slave type D-FF circuit, oscillation due to feedback from the output to the input can be prevented, and the operation is accurate and stable. Not only DCFL (Direct Coupled FET L
ogic) The operation speed can be improved by adopting a structure or the like.

Note that the present invention is not limited to the illustrated embodiment, and various modifications are possible. For example, there are the following modifications.

(1) D-FFs 11, 11-1 to 11-m, 2 in FIGS. 1 and 5
1, 21-1 to 21-n can be composed of master-slave type or other types of D-FF circuits.

(2) In FIG. 1, FIG. 5 and FIG.
A set D-FF that captures input data in synchronization with the falling edge of CK is used, but a set D-FF that captures input data in synchronization with the rising edge of the clock signal CK, or a D-FF with reset is used. By changing the connection state using Functions and effects substantially similar to those of the above embodiment can be obtained. For example, in a D-FF with reset that takes in input data in synchronization with the falling of the clock signal CK, the reset is performed when the reset terminal R is "H" and the output terminal Q is fixed at "L".

(3) In FIG. 6, the variable frequency dividing circuit is constituted by the one-stage ring counter 30 and the one-stage shift register 40. However, if the variable frequency dividing circuit is constituted by the m-stage ring counter and the n-stage shift register, 1 A variable frequency divider circuit capable of switching between / (2m) and 1 / (2m + n) frequency divisions.

(Effects of the Invention) As described above in detail, according to the first aspect of the present invention, the feedback signal output from the D-FF of the n-th stage of the shift register is directly transmitted to the ring without passing through another logic gate. Since the set signal or the reset signal is input to the D-FF of the first stage of the counter, the delay in returning the signal can be reduced, and the operation speed can be increased. In addition, since the other logic gate is not required, the circuit formation area in the integrated circuit can be reduced, and the power consumption can be reduced.

Further, the ring counter and the shift register are D-FF
Therefore, the number of clock signals is small and the circuit configuration is simple. In addition, desired division ratios 1 / (2m) and 1 / (2m + n) can be easily and accurately obtained by selecting the number of stages m and n of the D-FF.

According to the third aspect of the invention, since the D-FF is constituted by the master-slave type D-FF circuit, the operation is accurate and stable, and the operation speed can be further improved.

[Brief description of the drawings]

FIG. 1 is a block diagram of a variable frequency dividing circuit showing a first embodiment of the present invention, FIG. 2 is a block diagram of a conventional variable frequency dividing circuit, FIG. 3 is a timing chart of FIG. 2, and FIG. 1 is a timing chart of FIG. 1, FIG. 5 is a block diagram of a variable frequency dividing circuit showing a second embodiment of the present invention, and FIG. 6 is the number of stages m = 2, n in FIG.
FIG. 7 is a timing chart of FIG. 6, FIG. 8 is a block diagram of a variable frequency dividing circuit showing a third embodiment of the present invention, and FIG. 9 is a timing chart of FIG. 10,10m, 30 …… Ring counter, 11,11-1 to 11-m, 21,2
1-1 to 21-n D-FF, 20, 20n, 40 Shift register, 30a, 40a Master FF, 30b, 40b Slave F
F, CK: Clock signal, ▲ ▼: Negative phase clock signal, FB: Feedback signal, MC: Operation mode signal.

Claims (2)

(57) [Claims] An m-stage (where m is a positive integer) delay type flip-flop for taking in an input signal at one of a falling edge and a rising edge of a clock signal is cascade-connected. A second counter of the complementary first and second output signals output from the flip-flop, the second counter being fed back and input to the first-stage delay flip-flop; N stages (where the input signal is taken at either the falling edge or the rising edge of the signal, respectively,
(n is a positive integer) cascade-connected to the output side of the ring counter, the first output signal is input to the first-stage delay flip-flop, and the n-th delay A shift register that outputs a feedback signal having complementary first and second logic levels from an output side of the flip-flop, and a first stage of the ring counter according to a second logic level of the feedback signal. The delay flip-flop operates as a flip-flop, sets or resets the first-stage delay flip-flop of the ring counter according to the first logic level of the feedback signal, and sets the complementary first and second logic levels. Causing the n-stage delay flip-flop of the shift register to perform a flip-flop operation in accordance with the second logic level of the operation mode signal having: An n-stage delay flip-flop of the shift register is set or reset by the first logic level of the operation mode signal, and the first logic level of the operation mode signal and the second flip-flop are reset.
A frequency dividing ratio of the clock signal is switched between 1 / (2m) and 1 / (2m + n) by switching the logic level of the variable frequency dividing circuit. 2. The variable frequency dividing circuit according to claim 1, wherein the delay flip-flop comprises a master-slave delay flip-flop circuit comprising a master flip-flop and a slave flip-flop.