JPH0146929B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a reference signal generator for a magnetic recording/reproducing device (VTR), which generates a reference signal whose phase is synchronized with a vertical synchronizing signal during recording, and a reference signal having approximately the same frequency as the vertical synchronizing signal during playback. It is configured to generate a reference signal.

FIG. 1 is a block diagram showing the configuration of a conventional reference signal generator used in a VTR. During recording (REC), the vertical synchronization signal (V .sync.), the output is synchronized with crystal oscillator 2 during playback (PB).
The output obtained by dividing the oscillation frequency by the frequency dividing circuit 3 is switched by the changeover switch 5 and guided to the output terminal 6, where it is used as a reference signal.

The reference signal during playback is obtained from the crystal oscillator 2, so it is stable, but V.sync during recording may drop out in a weak electric field.

V.sync is disturbed by external noise.

It is not necessarily stable for the following reasons.

Therefore, if V.sync is simply frequency-divided and used as a reference signal for the servo circuit during recording, the operation of the servo circuit will become unstable, making it impossible to perform stable recording on the VTR. The astable multi 1 is used as a countermeasure against this problem, and a specific circuit example thereof is shown in FIG.

In Figure 2, Q1 is an astable multi V.
Trigger transistor for locking by sync, R1 is the base resistance of transistor Q1, Q
2 and Q3 are the first and second transistors constituting the astable multi, and R2 and R3 are the transistors Q, respectively.
2. The collector resistances of Q3, C1, R4, and VR are a capacitor, resistor, and volume that respectively determine the OFF period of transistor Q3 (ON) of transistor Q3, and these C2 and R5 respectively determine the OFF period of transistor Q2 (ON) of transistor Q3. These are capacitors and resistors that determine the period. That is, the transistor Q3
In the OFF state, capacitor C1 is connected to the power supply → VR → R4
→C1→Q2→GND, and when the base potential of transistor Q3 becomes V _{BE3 (ON)} , Q3 becomes
Turn on. Capacitor C2 is already connected to the power supply → R3 →
It is charged through the path C2→Q2→GND, and when transistor Q3 is turned on, the base of transistor Q2 is negatively biased and Q2 is turned off. When the transistor Q3 is in the ON state, the capacitor C2 is charged through the path of power supply → R5 → C2 → Q3 → GND, and when the base potential of the transistor Q2 becomes V _{BE2 (ON)} , Q2 is turned ON. On the other hand, capacitor C1 is power → R
2→C1→Q3→GND, and when transistor Q2 is turned on, the base of Q3 is negatively biased and transistor Q3 is turned off.
Make it. Thereafter, capacitors C1 and C2 are similarly charged and discharged, and transistors Q2 and Q3 are turned ON and OFF to continue oscillation. The oscillation frequency at this time is the period τ ₁ when transistor Q3 is OFF and the period when transistor Q2 is OFF.
It becomes 1/(τ ₁ +τ ₂ )Hz from the OFF period τ ₂ . Therefore, it is possible to adjust the oscillation frequency by adjusting τ ₁ using VR.

Here, the astable multi can be locked by V.sync only when transistor Q2 is OFF, so the frequency of the astable multi is set lower than the frequency of V.sync to reduce the influence of external noise. , τ ₁ > τ ₂
It is necessary to set τ ₁ , which is approximately 80% of the reference signal period of the servo circuit.

In the case of the NTSC system, the V.sync frequency is 60 Hz, and since servo circuits generally use 1/2, 30 Hz, as the reference frequency, it is set as 30>1/(τ ₁ +τ ₂ ). Here, V.sync may be either 60Hz or 30Hz.

By using the astable multiplier as described above, a buffer function can be provided and the above-mentioned problems can be solved, but this conventional reference signal generating device has the following drawbacks.

It is necessary to adjust the oscillation frequency of the astable multi.

Since capacitors, resistors, volumes, and transistors have temperature characteristics, the oscillation frequency changes.

It requires a capacitor, resistor, and volume, and is not suitable for integrated circuits.

The present invention provides a reference signal generating device that can solve the drawbacks of the conventional example.

FIG. 3 shows an embodiment of the reference signal generator according to the present invention, where 8 is an n-bit binary counter, 9 is an n-bit binary counter, and 9 is an n-bit binary counter.
Bit preset value generation and preset circuit,
10 is a count value detection circuit, 11 is an RS flip-flop, and 12 is a preset pulse generation circuit.

FIG. 4 is an analog representation of the counting operation of the n-bit binary counter 8, and the counted values _NOR and _NOP are the preset value generation and preset values of the preset circuit 9 during recording and playback. , which is switched by different signals applied to the terminal 15 during recording and during reproduction. Count value N ₁
and N ₂ are the count values detected by the count value detection circuit 10, and the relationship among N _OR , N _OP , N ₁ and N ₂ is given by the following equation.

N ₂ −N _OP / _CK 1 / _V ……(1) N _OR =N _OP −ΔN ……(2) N ₁ −N _OR ／N ₂ −N _OR ×10080(%) ……(3) Here , _V is the frame frequency of the vertical synchronization signal,
_CK is the clock frequency, and ΔN is the value that determines the buffer frequency.

FIG. 5 is an operational waveform diagram during recording, and b is an analog representation of the counting operation of the n-bit binary counter 8. A is a vertical synchronizing signal input to the terminal 13, and the sync is missing in some places. The operation of FIG. 3 will be explained with reference to FIG. When the vertical synchronizing signal a is input to the preset pulse generating circuit 12, the pulse generator 1 synchronized with the vertical synchronizing signal a
A preset pulse e with a clock width is output,
The RS flip-flop 11 is set, and the n-bit binary counter 8 is set via the preset circuit 9.
Set to preset value _NOR . Immediately thereafter, counting is started by the clock pulse g input to the terminal 14, and when the count value is _N1 , the count value detection circuit 10 generates a pulse C to reset the RS flip-flop 11 and generate the preset pulse. The circuit 12 is placed in a state in which it accepts a vertical synchronization signal. That is, when the count value of the n-bit binary counter 8 is between _NOR and _N1 , input of the vertical synchronizing signal is prohibited to take measures against noise. Then, the count value of n-bit binary counter 8 is from _N1 to
If the vertical synchronizing signal a is input during _N2 , the preset pulse e is output, the n-bit binary counter 8 is set to the preset value _NOR again, and
The RS flip-flop 11 is set and repeats the same operation thereafter. Furthermore, if the vertical synchronization signal a is dropped for some reason, the n-bit binary counter 8 counts up to the count value _N2 , and outputs the output pulse d of the count value detection circuit 10 generated at the count value _N2 . n-bit binary counter 8 as set pulse e
Set to preset value _NOR . And also
RS flip-flop 4 is also set and the above operation is repeated.

In this way, when the vertical synchronizing signal a is lost, it can be backed up with the output pulse d of the count value detection circuit 10 to provide a buffer function, and the vertical synchronizing signal a returns to the n-bit binary counter 8.
If the count value falls within the period from _N1 to _N2 , the preset operation using the vertical synchronizing signal a becomes possible again.

As described above, the signals e and f are synchronized with V.sync and can be used as reference signals for the servo circuit.

FIG. 6 is an operational waveform diagram during reproduction, and b is an analog representation of the counting operation of the n-bit binary counter 10. During reproduction, input of the vertical synchronizing signal a is prohibited in the preset pulse generation circuit 12 by a signal applied to the terminal 15 indicating the reproduction time, and the output pulse d of the count value detection circuit 10 is converted into a bit binary value as the preset pulse e. Set counter 8 to preset value _NOP . Immediately after that, counting starts and counts up to N ₂ . Thereafter, by repeating the same operation, a reference signal for the servo circuit during reproduction is obtained.

In the above embodiment, an up counter is used as an example of the binary counter 8, but a down counter can also be used.

As described above, the reference signal generating device of the present invention counts clock pulses and generates a reference signal when a predetermined count value is reached, and uses the counting means (n
(consisting of a bit binary counter 8, a preset circuit 9, a count value detection circuit 10, and a preset pulse generation circuit 12), the cycle is longer than the cycle of the vertical synchronization signal input from the outside during recording, and the cycle is longer than the cycle of the vertical synchronization signal input from the outside during playback. The initial value is set so that the reference signal is obtained at approximately equal intervals (consisting of an n-bit binary counter 8, a preset circuit 9, and a preset pulse generation circuit 12), and the initial value is set during recording. It is also performed using the vertical synchronization signal (n-bit binary counter 8, preset circuit 9).
and a preset pulse generation circuit 12),
Further, at least during recording, the output obtained by detecting the count value of the counting means prohibits the setting of the initial value by the vertical synchronization signal during a predetermined period of the cycle of the vertical synchronization signal (count value detection circuit 10, The RS flip-flop circuit 11 and the preset pulse generation circuit 12).

As explained above, in the present invention, all the components are digitalized, so there is no need to adjust the buffer frequency as in the conventional method, and the drawback that the buffer frequency changes due to temperature changes can also be eliminated. It has the advantage that it is unnecessary and is suitable for integration into integrated circuits.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing a conventional reference signal generating device, Fig. 2 is a specific circuit diagram of an astable multiplier used in the conventional reference signal generating device, and Fig. 3 is a diagram of a reference signal generating device according to the present invention. A block diagram showing one embodiment, FIG. 4 is an analog representation of the counting operation of the n-bit binary counter shown in FIG. 3, and FIG. 5 is an operational waveform diagram of the reference signal generator of the present invention during recording. , FIG. 6 is an operational waveform diagram during reproduction. 8...n-bit binary counter, 9...preset circuit, 10...count value detection circuit, 11...RS
Flip-flop circuit, 12... Preset pulse generation circuit, 13... Vertical synchronization signal input terminal, 1
4... Clock signal input terminal, 15... Record/playback signal input terminal.

Claims (1)

[Claims] 1 Counting means that forms a closed loop that counts clock pulses and generates a reference signal when a predetermined count value is reached, and sets the initial count value using this reference signal, and a vertical synchronization signal that is input from the outside during recording. The initial value is set so that the reference signal is obtained with a period longer than the period of , and with a substantially equal period during reproduction, and the initial value is also set using the vertical synchronization signal during recording, and A reference signal generating device configured to prohibit setting of the initial value by the vertical synchronizing signal during a predetermined period of the cycle of the vertical synchronizing signal, using an output obtained by detecting a count value of the counting means at least during recording.