JPH10191096A - Pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a displayed video image from being distorted by suppressing fluctuation in a control voltage of a voltage controlled oscillator(VCO) of a phase locked loop(PLL) even when a period of an input horizontal synchronizing signal is in disturbance so as to prevent the oscillated frequency from being fluctuated. SOLUTION: A synchronizing separator section 2 separates a horizontal synchronizing signal (HD) and a vertical synchronizing signal (VD) from an input signal and the synchronizing signals are given to a synchronization recovery section consisting of a phase comparator 3, an LPF 4, a VCO 5, and a frequency divider 7, a clock 6 is outputted and the HD 8 is outputted. The HD is used to reset a clock counter 9, which counts number of the clock signal 6 at each horizontal period (H) and the VD is used to reset an H counter 10, which counts number of HDs, and each of 1H registers 12-1-12-n latches counts of the corresponding H from the CK counter 9 for each vertical synchronizing period (1V) based on a signal decoded by a decoder 11 and the latched count is shifted by shift registers 13-1-13-n. The counts of the 1H registers and the shift registers for each H are read by a selector 14, the result is divided by number of fields added by an adder 15 and a subtractor 16 and the quotient is stored in a mean value register 17, is read and used to control a frequency division ratio of the frequency divider 7 so as to control a phase of a HD reference signal (Ref) to be the same as the phase of the HD.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit,
The present invention relates to a method for suppressing disturbance of the oscillation frequency of a voltage-controlled oscillator included in a PLL circuit when a signal whose period of an input horizontal synchronizing signal changes is input, and preventing vertical lines from being bent in a displayed image.

[0002]

2. Description of the Related Art In a PLL (Phase Locked Loop) circuit of a video signal processing device or the like, as shown in FIG. The signal is input to the comparator 23, the phase of the reference signal (HD Ref) from the frequency divider 27 is compared with the phase of HD, and the signal of the phase difference from the phase comparator 23 is filtered by an LPF (low-pass filter) 24. , DC component is extracted and VCO (Voltage Controlled Oscillator)
25, oscillates at a frequency corresponding to this signal (voltage), divides the frequency into the HD frequency by a frequency divider 27, and feeds it back to the phase comparator 23. Generates a clock 26 and HD 28 that match
For example, in the case of reproducing a VTR (Video Tape Recorder) and switching the head, the cycle of HD is disturbed and skew occurs, as shown in FIG. 4, the first field (a) and the second field (a '). ), A difference occurs in the period between the playback HD from the PLL circuit and the start point of the video, so that there is a time difference a'-a in the display position of the video as shown in FIG. 5, and the displayed video has a vertical line curve. Occurs. In other words, as shown in FIG. 2, the length of the input HD (HD from the sync separation unit 22) interval = 1H (one horizontal scanning period) varies.
If the period (1H) of the frequency divider 27 is long, the output of the phase comparator 23 falls to the L level, the oscillation frequency of the VCO 25 is reduced, and the frequency divider 27
The HD Ref operates so that the phase of the HD Ref matches the HD phase, the width of the L level gradually decreases, the output of the phase comparator 23 converges to Z (zero), and the skew stops.

[0003]

As described above, the VTR
When the cycle of the input HD is disturbed at the time of reproduction of the display, the control voltage applied to the VCO is disturbed and the display image is bent.
Disturbance of the HD cycle caused by special reproduction (still, double speed, high speed reproduction, etc.) of the image recording apparatus including the VTR, ie, 1
The change in the length of H is regular when viewed in field units (or frame units), and occurrence can be predicted. The present invention focuses on this point, and sets the number of PLL clocks to one.
By counting every H and generating a PLL reference signal (HD Ref) based on the count value, it is possible to suppress disturbance of a signal (control voltage) applied to the VCO and prevent bending of a display image. is there.

[0004]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention comprises a sync separator for separating HD and VD from a composite video signal, a phase comparator, a VCO, a frequency divider, and the like. The oscillated clock is frequency-divided by a frequency divider to the frequency of HD from the synchronous separation unit, input to the phase comparator together with HD, and a signal output from the phase comparator according to the phase difference is applied to the VCO, A synchronous reproduction unit that outputs a clock having a phase that matches the phase of the HD and the reproduced HD, a clock counter that counts the clock from the synchronous reproduction unit for each horizontal scanning period, and a clock for the required number of fields for each horizontal scanning period An average calculation unit for calculating an average of the numbers, and an HD reproduced by the synchronous reproduction unit based on a signal from the average calculation unit.
And a PLL circuit that controls the frequency of the PLL circuit.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In a PLL circuit according to the present invention, HD and VD are separated from a composite video signal by a sync separation unit. In a synchronous reproduction unit including a phase comparator, a VCO, a frequency divider, etc., the clock oscillated by the VCO is frequency-divided by the frequency divider to the same frequency as the HD, and input to the phase comparator together with the HD. A signal (control voltage) output in accordance with the phase difference is applied to the VCO, a clock having the same phase as the HD and a reproduced HD are output, and the clock from the synchronous reproduction section is horizontally scanned by a clock counter. It counts for each period, records the required number of fields for each horizontal scanning period in the memory unit, reads out the data of the memory unit for each horizontal scanning period via the selector, inputs the data to the average value calculation unit, and inputs the data for each horizontal scanning period. The average value of the number of clocks is calculated, and the signal from the average value calculation unit controls the frequency division ratio of the frequency divider to be reproduced.
Control the HD frequency.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a PLL circuit according to the present invention will be described below in detail with reference to the drawings. FIG. 1 shows a PL according to the present invention.
FIG. 3 is a block diagram of a main part of an embodiment of an L circuit. In the figure, 1 is a terminal for inputting a composite video signal, 2 is a sync separation unit, and a sync separation unit 2 converts the composite video signal from
(Horizontal synchronization signal) and VD (vertical synchronization signal). Reference numeral 3 denotes a phase comparator which compares the phase of the HD Ref (reference signal) from the frequency divider 7 with the phase of the HD from the sync separator 2 and outputs a signal corresponding to the phase difference. Reference numeral 4 denotes an LPF (low-pass filter) for extracting a DC component of the signal from the phase comparator 3. A VCO 5 oscillates a clock 6 having a frequency corresponding to the signal level from the LPF 4. The divider 7 has V
The clock 6 from the CO 5 is frequency-divided to the HD frequency from the sync separation unit 2 to generate HD Ref, and is fed back to the phase comparator 3. The HD Ref from the frequency divider 7 is output as a playback HD 8. The phase comparator 3, LPF 4, VCO 5 and frequency divider 7 constitute a synchronous reproduction unit.

Reference numeral 9 denotes a clock counter, which is reset by the HD from the sync separation unit 2 and counts the clock from the VCO 5. Reference numeral 10 denotes a horizontal synchronization counter, which is reset by VD from the synchronization separation unit 2 and counts HD from the synchronization separation unit 2. A decoder 11 decodes a signal from the horizontal synchronization counter 10. 12-1 to 12-n are 1H registers provided with the number of horizontal scanning periods of one frame: n (525 in the NTSC system), and the count value of the clock counter 9 based on the first HD to n-th HD signals from the decoder 11. (Data) are respectively latched. 13-1
13-n are shift registers, each of which is a 1H register 12
The data from -1 to 12-n are sequentially shifted and recorded by the VD from the sync separation unit 2. Reference numeral 14 denotes a selector for sequentially selecting data in the shift registers 13-1 to 13-n. An adder 15 adds the data of N to Nm from the selector 14. 16
Is a divider, which divides the data from the adder 15 by the number of added fields, that is, m + 1. An average value register 17 stores the data calculated by the divider 16.

Next, the operation of the PLL circuit according to the present invention will be described. The composite video signal from the terminal 1 is input to the sync separation unit 2 to separate HD and VD, and the separated HD is input to the phase comparator 3. The phase comparator 3 receives the HD Ref from the frequency divider 7
Is compared with the HD phase. If the HD phase is advanced, an H-level signal is output, and if the HD phase is delayed, an L-level signal is output. The signal from the phase comparator 3 is LP
The DC component is input to F4, and is applied to VCO5. The oscillation frequency of the VCO 5 increases with an H level signal, and decreases with an L level signal. When the HD Ref and the HD have the same phase, the output of the phase comparator 3 becomes zero, the output becomes high impedance, and the VCO 5
And the oscillation frequency is held. VCO5
The input signal (clock 6) is input to a frequency divider 7, which divides the frequency based on a signal from an average value register 17, which will be described later, is output as a reproduced HD 8, and is also fed back to the phase comparator 3 as an HD Ref. You.

The clock counter 9 receives a signal from the synchronization separation unit 2.
HD, the number of clocks 6 output from the VCO 5 during 1H (one horizontal scanning period) is counted, and the horizontal synchronization counter 10 is reset by VD from the synchronization separation unit 2, and
Is counted. The signal from the horizontal synchronization counter 10 is decoded by the decoder 11, the first HD signal is sent to the 1H register 12-1, the second HD signal is sent to the 1H register 12-2,
The nth signal is applied to the 1H register 12-n (n is the number of horizontal scanning periods, 525 in NTSC). The data from the clock counter 9 is applied to the 1H registers 12-1 to 12-n, and latched in the 1H registers to which the signal from the decoder 11 is applied. Then, the data of the 1H register 12-1 is transferred to the shift register 13 according to the VD from the synchronization separator 2.
-1 group is sequentially shifted, the data of the previous field is stored in the N-1 shift register, the data of the previous field is stored in the N-2 shift register, and the data of the previous field is stored in the Nm shift register. Similarly, the data of the 1H register 12-2 is stored in the shift register 13-2 group, and the data of the 1H register 12-n is stored in the shift register 13-n group. The data is sequentially shifted and recorded accordingly.

The signal from the horizontal synchronization counter 10 is used by the selector 14 together with the data of the 1H registers (12-1 to 12-n) 1H ahead, together with the same H shift register group (13-1, 13-n).
2, 13-n) is read out by group, and adder 1
5, add, input to the divider 16, divide by m + 1, calculate the average value of the number of clocks of each H in the field number m + 1, record in the average value register 17,
The frequency division ratio of the frequency divider 7 is controlled on the basis of the data from 17.

As a result, as shown in FIG.
If the interval (the length of 1H) of the (HD from the synchronization separation unit 2) is longer or shorter, the count average value (average number of clocks of each H) recorded in the average value register 17 depends on the length of 1H. Since these data control the frequency division ratio of the frequency divider 7 with these data, the phase of the HD Ref from the frequency divider 7 is always close to the phase of the input HD, and the output of the phase comparator 3 is Since it becomes almost zero, the oscillation frequency of the VCO 5 hardly fluctuates, and the fluctuation of the cycle of the reproduction HD is suppressed, so that the displayed image is hardly bent.

The number of recorded data (the number of fields) of each 1H register and each shift register group is set to an appropriate number of fields, for example, 30 fields so that the frequency of the reproduced HD does not repeatedly change rapidly. And so on.

[0013]

As described above, according to the present invention, P
According to the LL circuit, the number of clocks generated by the VCO is 1
Counting for each H, calculating the average value of the required number of fields for each H, controlling the dividing ratio of the frequency divider with each H based on this average value, suppressing the fluctuation of the output of the phase comparator, Since the oscillation frequency is prevented from unnecessarily fluctuating, for example, even if the cycle of the input HD is disturbed due to special reproduction of an image recording apparatus such as a VTR or the like, the display image is hardly bent.

[Brief description of the drawings]

FIG. 1 is a main part block diagram of an embodiment of a PLL circuit according to the present invention.

FIG. 2 is a time chart for explaining the operation of the PLL circuit according to the present invention.

FIG. 3 is an example of a conventional PLL circuit.

FIG. 4 is a time chart for explaining an operation of a conventional PLL circuit.

FIG. 5 is an explanatory diagram of an operation when a skew occurs.

[Explanation of symbols]

 Reference Signs List 2 sync separation unit 3 phase comparator 5 VCO (voltage controlled oscillator) 6 clock 7 frequency divider 8 playback HD (playback horizontal synchronization signal) 9 clock counter 10 horizontal synchronization counter 11 decoder 12-1 to 12-n 1H register 13- 1 to 13-n shift register 14 selector 15 adder 16 divider 17 average value register

Claims (10)

[Claims] 1. A synchronizing separator for separating a horizontal synchronizing signal and a vertical synchronizing signal from a composite video signal, a phase comparator, a voltage controlled oscillator, a frequency divider, etc., and a clock oscillated by the voltage controlled oscillator is divided by a frequency divider. The frequency divider divides the frequency into the frequency of the horizontal synchronizing signal from the sync separator, inputs the signal to the phase comparator together with the horizontal synchronizing signal, applies a signal output according to the phase difference from the phase comparator to the voltage controlled oscillator, A synchronous reproducing unit for outputting a clock having a phase coincident with the phase of the synchronous signal and a reproduced horizontal synchronizing signal, a clock counter for counting clocks from the synchronous reproducing unit for each horizontal scanning period, and a required number of clocks for each horizontal scanning period An average value calculation unit for calculating an average value of the number of clocks in the field, and a frequency of a horizontal synchronization signal reproduced by the synchronous reproduction unit is controlled based on a signal from the average value calculation unit. PLL circuit. 2. The PLL circuit according to claim 1, wherein a frequency division ratio of said frequency divider is controlled based on a signal from said average value calculation section to control a frequency of a reproduced horizontal synchronizing signal. 3. The number of fields for calculating the average value is:
2. The PLL circuit according to claim 1, wherein the required number of fields is set so that the frequency of the reproduced horizontal synchronizing signal does not repeatedly change rapidly. 4. The PLL circuit according to claim 1, wherein the clock counter is reset by a horizontal synchronization signal from the synchronization separation unit and counts a clock from a synchronization reproduction unit. 5. A memory unit for recording a count value from the clock counter for a plurality of fields for each horizontal scanning period, reading data from the memory unit for each horizontal scanning period, and inputting the data to the average value calculating unit. The PLL circuit according to claim 1 or 4. 6. The PLL circuit according to claim 5, wherein said memory unit comprises a shift register for recording a count value of a plurality of fields for each horizontal scanning period. 7. The PLL circuit according to claim 5, wherein a selector for reading data from the memory unit for each horizontal scanning period is provided, and data from the selector is input to the average value calculation unit. 8. A horizontal synchronizing counter for measuring an order of a horizontal synchronizing signal during a vertical synchronizing period based on the horizontal synchronizing signal and the vertical synchronizing signal from the synchronizing separator, and counting the count value from the clock counter to the memory. 8. The PLL circuit according to claim 5, wherein data is recorded in an area corresponding to a horizontal scanning period. 9. The average value calculation unit includes an adder that calculates a sum of count values of a plurality of fields for each horizontal scanning period, and a divider that divides data from the adder by the number of fields. 2. The PLL circuit according to 1. 10. An average value calculation section, wherein an average value memory section for recording data from a divider is provided, and a frequency division ratio of the frequency divider is controlled based on data read from the average value memory section. The PLL circuit according to claim 9.