JP3095853B2 - Time axis correction device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time axis correcting apparatus for correcting a time axis of a reproduced signal in an apparatus having an information reproducing function such as a VTR, and more particularly, to a method for removing an instantaneous speed error. And a time axis correction device.

[0002]

2. Description of the Related Art For example, in a VTR, a time axis error called jitter occurs in a reproduced signal due to a change in relative speed between a magnetic tape and a reproducing head. It will be disturbed. For this reason, a conventional VTR is provided with a time axis correction device for removing a time axis error as described below.

In this time axis correction device, for example, as shown in FIG. 7, an A / D converter (A / D converter in FIG. 7) converts an input signal (reproduction signal) with a write clock WCK synchronized with the input signal.
D) digitizing by 31 and writing to the memory 32 to remove jitter, read out the input signal with a reference clock, and convert it to analog by a D / A converter (D / A in the figure) 33. ing.

The write address of the memory 32 is determined based on the write clock WCK described above.
4 and the write address generator 3
4 is cleared every 1H by a reproduction horizontal synchronization signal (hereinafter, appropriately referred to as a tape H). A read address for reading an input signal from the memory 32 is generated by a read address generator 35 based on a reference clock, and the read address generator 35 generates a stable reference horizontal synchronizing signal (hereinafter referred to as a reference H).

In such a time axis correction apparatus, it is necessary to accurately synchronize the write clock WCK with the input signal in order to remove jitter. Therefore, the above-described time axis correction device includes a multi-phase clock generation unit 36, a reference signal detection unit 37, and a clock selection unit 38.
It is configured to generate the write clock WCK as follows.

The multi-phase clock generator 36 generates a plurality of multi-phase clocks having a minute phase difference based on a stable reference clock that is asynchronous in phase with the input signal. On the other hand, the tape H is detected from the input signal by the reference signal detection unit 37 and is extracted. Then, the clock selection unit 38
, A clock closest in phase to the reference signal is selected from the multi-phase clock, and is output as a write clock WCK synchronized with the input signal.

[0007]

However, since the write clock WCK obtained as described above has the same frequency as the reference clock, an instantaneous speed error which occurs between 1H called a velocity error occurs. In this case, the length of 1H of the input signal fluctuates, and the write clock WCK is not accurately synchronized with the input signal. Therefore, the memory 32
In this case, the number of write addresses for writing the input signal fluctuates, and it becomes impossible to accurately remove the velocity error.

When the velocity error is accumulated, the reproduced signal has a large jitter in the latter half of 1H and the length of 1H changes. Then, when the reproduced signal is displayed on a monitor, a disturbance peculiar to a velocity error in which the right end of the reproduced image is irregular occurs, and the image quality is reduced.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to accurately remove a jitter including a velocity error over the entire 1H and to perform time axis correction with high accuracy.

[0010]

In order to solve the above-mentioned problems, a time axis correcting apparatus according to the present invention has a first memory for holding an input signal and a first memory for holding an input signal read from the first memory. A second memory for reading out the data with a reference clock, multi-phase clock generation means for generating a plurality of clocks having different phases based on the reference clock, and a clock added by the multi-phase clock generation means to the input signal. A clock selecting means for selecting a clock substantially synchronized with a reference signal such as a horizontal synchronizing signal as a clock for writing an input signal to the first memory; and a clock selected by the clock selecting means separated by the reference signal. Of the number of clocks per period (eg, 1H)
Clock of reference clock per period separated by signal
By switching the clocks generated by the multi-phase clock generating means at intervals corresponding to the increase / decrease in the number, a clock is generated in which the number of clocks per predetermined period (for example, regular 1H) is constant, and this clock is generated. An input signal is read from the first memory and the second signal is read.
A multi-phase clock switching means for outputting as a clock for writing an input signal to the memory.

[0011]

When the above configuration is applied to a VTR, a reference signal of a reproduced signal to be an input signal, for example, a horizontal synchronization signal, is input from a plurality of clocks (multi-phase clocks) generated by the multi-phase clock generation means by a clock selection means. The one synchronized with the signal is selected as the write clock. The input signal is written to the first memory by this write clock, and at this time, jitter of one clock or less of the write clock is removed, but the length of the latter half of 1H is affected by the residual velocity error. Fluctuates, and the length of 1H changes from the normal length as a whole.

Further, the multi-phase clock switching means converts the multi-phase clock based on the number of clocks per 1 H of the input signal of the write clock so that the number of clocks per predetermined period (regular 1 H) becomes constant. It is switched and output. Specifically, the number of clocks per 1H of the input signal is equal to the regular number of clocks of the reference clock per 1H.
By controlling the timing of switching of the multi-phase clock to change the clock phase in accordance with the increment or decrement against number of clocks per 1H regular constant clock is created.

Therefore, when the input signal is read from the first memory by the clock generated as described above, 1H is corrected to a normal length. Subsequently, when the input signal is written to the second memory at the same clock, the velocity error is removed at that point. When the input signal is read from the second memory at regular intervals by a stable reference clock, the velocity error is removed,
Time axis correction is performed with high accuracy.

As described above, in the above configuration, the input signal is written into the first memory using the clock synchronized with the input signal, and the increase or decrease in the number of clocks per 1 H of the input signal is used as velocity error data. The number of clocks is corrected based on this, and further, the input signal is read from the first memory and written to the second memory using the clock. Therefore, according to the above configuration,
Velocity errors can be reliably removed.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to a VTR time axis correcting apparatus will be described below with reference to FIGS.

As shown in FIG. 1, the time axis correction device according to the present embodiment includes an A / D converter (A / D in FIG. 1), memories 2 and 3, and a D / A converter (FIG. D / A) 4, write address generators 5 and 6, read address generators 7 and 8, write clock generator 9, and polyphase clock switcher 10.

The A / D converter 1 is a circuit for converting a reproduced signal as an input signal into a digital signal. The A / D converter 1 performs sampling with a write clock WCK generated by a write clock generator 9. Memory 2 as first memory
Is a semiconductor memory for holding digital data output from the A / D converter 1, and a memory 3 as a second memory is a semiconductor memory for holding digital data read from the memory 2. The memories 2 and 3 perform writing and reading of digital data in line units. The D / A converter 4 is a circuit that converts digital data read from the memory 3 to analog with a reference clock.

The write address generator 5 is an address counter that generates a write address to be given to the memory 2 based on a write clock WCK when writing digital data to the memory 2. The write address generator 5 is cleared at the timing of the tape H detected by the reference signal detector 11 of the write clock generator 9 described later, and controls the generation start timing of the write address every 1H. .

The read address generator 7 is an address counter that generates a read address to be given to the memory 2 based on the correction clock fCK generated by the multi-phase clock switching unit 10 when reading digital data from the memory 2. The read address generator 7 is cleared at the timing of the reference H, and controls the generation start timing of the write address every 1H.

The write address generator 6 is an address counter that generates a write address to be given to the memory 3 based on the correction clock fCK. The read address generator 8 is an address counter that generates a read address to be given to the memory 3 based on a reference clock. The write address generator 6 and the read address generator 8 are both cleared at the reference H timing, and control the start timing of generation of read and write addresses every 1H.

The write clock generator 9 as a write clock generator includes a reference signal detector 11, a multi-phase clock generator 12, and a clock selector 13.

The reference signal detecting section 11 is a circuit for taking out the tape H as a reference signal added to the reproduced signal. The multi-phase clock generator 12 is a circuit that generates n multi-phase clocks nCK having different phases by slightly delaying the phase of the reference clock equally. Clock selector 13
Is the tape H detected by the reference signal detection unit 11 from the multi-phase clock nCK generated by the multi-phase clock generation unit 12.
Is a circuit which selects the clock closest in phase to the write clock WCK.

A polyphase clock switching unit 10 as a polyphase clock switching means switches the polyphase clock nCK generated by the polyphase clock generation unit 12 based on the number of write clocks WCK per 1 H of an input signal. ,
It is configured to generate a correction clock fCK serving as a read clock applied to the memory 2 and a write clock applied to the memory 3.

As shown in FIG. 2, the multi-phase clock switching section 10 includes a reference pulse creating section 14, a gate clock generating section 15, a gate creating section 16, a multiplexer 17
And an output gate unit 18. The reference pulse generator 14 is a circuit that generates a negative reference pulse having a pulse width equal to one clock of the reference clock and a 1H cycle based on the reference H.

The gate clock generator 15 generates a gate generator 16 based on the write clock WCK and the tape H.
Is a circuit for generating a gate clock GCK to be applied to the gate.
The gate clock generator 15 includes a 1H counter 19, a latch 20, a ROM 21, a latch 22, a control counter 23,
NOT gates 24 and 25 and INH (INHIBI
T) A gate 26 is provided.

In the 1H counter 19, the write clock WCK is input to the clock terminal CK, and the tape H is input to the clear terminal CLR via the NOT gate 24. Is a counter that counts the number of clocks of the write clock WCK during 1H. The latch 20 holds the count value b of the 1H counter 19 at the timing of the tape H.

The ROM 21 constitutes a calculation table using the count value b of the 1H counter as input data, and stores output data α of a calculation result by the equation (1) based on the count value b. In equation (1),
It is assumed that a regular count value of the reference clock per 1H is a, a maximum count value from when a control counter 23 described later counts up from 0 to an output of the carry-out terminal CO becomes “H” level is C, and n is Polyphase clock n
The number of CK phases is used. The maximum count value C is, for example,
When the control counter 23 is a 12-bit counter $ FFF
Becomes α = Ca / {n | ab |} (1) In the above equation, α = 0 when ab = 0.

Here, a / n is the gate clock GC when the count value b deviates from the count value a by one clock.
This represents the number of reference clocks that determine the interval at which K (the output of the carry-out terminal CO) is output.

For example, if the count value a is 1530 and the number of phases n is 30, a / n = 51, and the control counter 23 outputs the gate clock G every 51 reference clocks.
CK is output. Therefore, a / {n | ab |}
With respect to the difference between the count value a and the count value b,
The number of reference clocks that determines the interval at which the gate clock GCK is output is obtained. Further, according to the calculation of Expression (1), the output data α increases as the deviation of the count value b from the count value a increases, and becomes a value that causes the gate clock GCK to be output at shorter intervals.

The ROM 21 outputs a select signal according to the magnitude of the count value b such that the select signal goes high when ab <0, and goes low when ab ≧ 0. β is output. It is sufficient that the state of select signal β is different between ab <0 and ab ≧ 0, so that the state can be switched in the reverse relationship to the above. .

The latch 22 stores the output data α of the ROM 21
And the select signal β is held at the timing of the reference pulse inverted by the NOT gate 25. The control counter 23 is a counter that counts the correction clock fCK, and an output pulse of the INH gate 26 is input to the load terminal LOAD.
The control counter 23 loads the output data α that has passed through the latch 22 by the output pulse of the INH gate 26, and outputs a signal from the carry-out terminal CO every time the counting from the loaded output data α to the maximum count value C is completed. An "H" level gate clock GCK is output. The INH gate 26 is a gate that takes a logical sum of the reference pulse and the gate clock GCK.

As shown in FIG. 3, the gate creation unit 16
It is constituted by the flip-flop FF ₁ ~FF _n. Flip-flop FF ₁ to ff _n, together with the gate clock GCK is supplied to the clock terminal CK, and so the reference pulse is inputted to the clear terminal CLR, the flip-flop FF ₂ to ff _n is preset terminal PR Are fixed at the “H” level. The flip-flop FF ₁ is adapted to the reference pulse is also input to the preset terminal PR. The flip-flop FF ₁ to ff _n, each output terminal Q input terminal D of the next stage flip-flop FF ₂ ~FF _n · FF ₁
It is connected to the.

The gate creating unit 16 configured as described above
Generates gate pulses G _{1 to} G _n sequentially shifted from the output terminals Q of the flip-flops FF _{1 to} FF _{n by} the gate clock GCK. That is, when the reference pulse is inputted, the gate pulse G ₂ ~G with only a gate pulse G ₁ is to "H" level
_n becomes "L" level, the gate pulse G ₂ ~ becomes "H" level at every rise of the later gate clock GCK
G _n are sequentially output.

The multiplexer 17 has a gate pulse G
₁ is input to the input terminals A ₁ and B ₁ and the gate pulse G ₂
Are input to the input terminals A ₂ and B _n , and the gate pulse G
₃ ~G _n is, is inputted to the input terminals A ₃ to A _n, are input to the input terminal B _n-1 ~B _2. When the select signal SEL (β) is at the “H” level, the multiplexer 17 outputs the gate pulses G ₁ · G _n -G input to the input terminals B ₁ -B _n as shown in (A) below. ₂ while the select signal SE
When L is at the “L” level, as shown in (B) below,
Input terminals A ₁ to A _n gate pulse G ₁ is input from ~
_Gn is output. (A) GA ₁ = G ₁ , GA ₂ = G _n , GA ₃ =
G _n−1 ,..., GA _n = G ₂ (B) GA ₁ = G ₁ , GA ₂ = G ₂ , GA ₃ = G ₃ ,
.., GA _n = G _{n When} the select signal SEL switches in the opposite phase to the above, the multiplexer 17 outputs the gate pulse G
_{1 to} G _n are output in response to (A) when the select signal SEL is at “L” level, and are output in response to (B) when the select signal SEL is at “H” level.

The output gate section 18 includes AND gates & ₁ to
& _N and an OR gate 27. AND gates & ₁ ~ & _n are gate pulse GA ₁ ~GA _n of one to input terminals multiplexer 17 is input, each of the clock CK ₁ ~CK _n of the multiphase clocks nCK is input to the other input terminal It has become so. The OR gate 27 receives the output signals of the AND gates & ₁ to & _n .

In the above configuration, when an input signal is input, the reference signal detecting section 11 extracts the tape H. On the other hand, the multi-phase clock generator 12 generates the multi-phase clock nCK by delaying the reference clock. Then, the clock selecting unit 13 selects a clock synchronized with the tape H from the multi-phase clock nCK, and outputs this clock as the write clock WCK.

The input signal is digitized by the A / D converter 1 with the write clock WCK, becomes digital data, and is written into the memory 2 at the timing of the write clock WCK. At this time, the input signal is sequentially written to the addresses generated by the write address generator 5 based on the tape H and the write clock WCK. At this point, the jitter of one clock or less is removed from the input signal, but the velocity error remains without being removed. In the input signal, the length of the latter half of 1H fluctuates due to the influence of the velocity error, and the length of 1H is shorter or longer than the regular length as a whole.

In the multi-phase clock switching section 10, the 1H counter 19 counts the write clock WCK every 1H, and the count value b is output to the R
It is sent to OM21. Then, the output data α and the select signal β are read from the ROM 21 based on the count value b.
Is output. Among them, the output data α is
Is loaded into the control counter 23 as load data via the. In the control counter 23, the counter of the correction clock fCK is started from the load data, and when the counting up to the maximum count value C is completed, a gate clock GCK as shown in FIG. 4B is generated.

At this time, for example, the write clock WCK
Is set to 1530, and the n-phase clock n
When the number of phases of CK is 30, the actual count value b is 1
527, the above-mentioned a / {n | ab |}
Will output the gate clock GCK once every 17 clocks of the write clock WCK.

On the other hand, the reference pulse created by the reference pulse creating section 14 based on the reference H (shown in FIG. 7A).
Is input to the gate creation unit 16 together with the gate clock GCK. The gate creation unit 16 creates gate pulses G _{1 to} G _n that shift at the timing of the reference pulse and the gate clock GCK.

These gate pulses G _{1 to} G _n pass through the multiplexer 17, but when the select signal SEL is at the “H” level ((c) in the figure), as shown in (d) in the figure. the gate pulse G ₁ is outputted as a gate pulse GA _1, since the gate pulse G ₂ ~G _n
Are output as gate pulses GA _{n to} GA ₂ , respectively. Further, when the select signal SEL is at the "L" level, the gate pulse G ₁ is outputted as a gate pulse GA _1, since the gate pulse G ₂ ~G _n is outputted as a gate pulse GA ₂ ~GA _n respectively.

Here, the clocks CK _{1 to} CK _n of the multi-phase clock nCK are supplied to the output gate section 18 during the period when the gate pulses GA _{1 to} GA _n obtained as described above are at the “H” level. Output from AND gates & ₁ to & _n . Thus, the multi-phase clock nCK is output is switched by the gate pulse GA ₁ ~GA _n,
The signal is output as the correction clock fCK via the OR gate 27.

In the above operation, when the number of clocks of the write clock WCK per 1H of the input signal becomes larger than a reference value (normal number of clocks of the reference clock per 1H), for example, as shown in FIG. when the switches and the gate pulse GA ₁ and the gate pulse GA _n, among the multiphase clocks nCK, it switches to the clock CK _n the phase is most delayed clock CK ₁ to the most advanced, the correction clock fCK phase Changes. Such a phenomenon occurs even when the other gate pulses GA _{2 to} GA _n−1 are switched. Therefore, the correction clock fCK is determined based on the switching interval of the gate pulses GA _{2 to} GA _n−1 according to the count value b. Is corrected so that the regular number of clocks per 1H becomes the reference value.

[0044] Conversely, when the clock number of the write clock WCK per 1H of the input signal becomes smaller than the reference value, for example, as shown in FIG. 6, when switching is a gate pulse GA ₁ and the gate pulse GA ₂ , the correction clock fCK is switched from the clock CK ₁ to the clock CK _2, a pulse width at this time is wider. As a result, the correction clock fCK is corrected so that the normal number of clocks per 1H becomes the reference value.

The correction clock f thus created
CK is sent to memories 2 and 3, read address generator 7 and write address generator 6. Then, the digital data is sequentially read from the address of the memory 2 designated by the read address generator 7 at the timing of the correction clock fCK. At this time, the interval at which the digital data is read is partially changed because the phase of the correction clock fCK is changed as described above.
This digital data is stored in the same correction clock f.
At the timing of CK, the data is sequentially written to the address of the memory 3 specified by the write address generator 6. At this point, the input signal is 1H
Is corrected to the regular length.

Further, the above-mentioned digital data is sequentially read from the address of the memory 3 designated by the read address generation section 8 at a predetermined interval at the timing of the reference clock. Is converted to As described above, the input signal passes through the two memories 2 and 3 to stabilize the time axis, and is output as an output signal to a next-stage circuit (not shown).

As described above, in the configuration of this embodiment,
When the number of clocks of the write clock WCK per 1 H of the input signal deviates from the reference value, the deviated number of clocks is used as velocity error data, and the correct number of clocks per 1 H of the correction clock fCK becomes constant accordingly. Thus, the multi-phase clock nCK is switched and output. Thus, it is possible to remove a velocity error included in the input signal with high accuracy, and to eliminate a disturbance in a reproduced image due to the velocity error.

[0048]

As described above, the time axis correction device of the present invention has the first memory for holding the input signal and the second memory for holding the input signal read from the first memory and reading it with the reference clock. A memory, a multi-phase clock generating means for generating a plurality of clocks having different phases based on the reference clock, and a clock substantially synchronized with the reference signal added to the input signal from the clock generated by the multi-phase clock generating means a clock selecting means for selecting as the clock for writing the input signal to the first memory, the number of clock per period delimited by the reference signal of the clock selected by the clock selecting means, a regular reference signal Separation
The number of reference clocks per period
By switching the clocks generated by the multi-phase clock generating means at intervals corresponding to the increase or decrease, a clock is generated in which the number of clocks per predetermined period is constant, and this clock is read from the first memory as an input signal. And a multi-phase clock switching means for outputting as a clock for writing an input signal to the second memory.

As a result, the number of clocks for reading the input signal from the first memory and writing the input signal to the second memory is corrected so that the number of clocks is constant during the above-mentioned period. Errors can be removed with high accuracy. Therefore, the length of 1H of the input signal that fluctuates due to the velocity error is accurately corrected,
There is an effect that it is possible to eliminate peculiar disorder generated in the reproduced image.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a time axis correction device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a multiphase clock switching unit in the time axis correction device of FIG.

FIG. 3 is a circuit diagram showing a configuration of a gate creation unit in the multi-phase clock switching unit of FIG.

FIG. 4 is a time chart illustrating an operation of the multi-phase clock switching unit in FIG. 2;

FIG. 5 is a time chart showing a multi-phase clock switching operation of the multi-phase clock switching unit in FIG. 2 when the number of write clocks is larger than a reference value.

FIG. 6 is a time chart showing a multi-phase clock switching operation of the multi-phase clock switching unit in FIG. 2 when the number of write clocks is smaller than a reference value.

FIG. 7 is a block diagram showing a configuration of a conventional time axis correction device.

[Explanation of symbols]

2 Memory (First Memory) 3 Memory (Second Memory) 5.6 Write Address Generator 7.8 Read Address Generator 10 Multi-Phase Clock Switch (Multi-Phase Clock Switch) 11 Reference Signal Detector 12 Multi-Phase Clock Creation unit (polyphase clock creation unit) 13 Clock selection unit (clock selection unit)

──────────────────────────────────────────────────の Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 5/91-5/956 G11B 20/06 302 H04N 9/79-9/898

Claims (1)

(57) [Claims] A first memory for holding an input signal, a second memory for holding an input signal read from the first memory and reading it with a reference clock, and a clock having a different phase based on the reference clock. A plurality of polyphase clock generating means, and a clock for writing an input signal to the first memory, the clock being substantially synchronized with a reference signal added to the input signal from the clock generated by the multiphase clock generating means. Clock selection means for selecting a clock signal as the clock signal, and the number of clocks per period divided by the reference signal of the clock selected by the clock selection means.
Number of reference clocks per period, separated by symbols
By switching the clock created by the multi-phase clock creating means at intervals according to the increase or decrease with respect to
Multiphase clock switching means for generating a clock having a constant number of clocks per predetermined period, reading the input signal from the first memory, and outputting the clock as a clock for writing the input signal to the second memory And a time axis correcting device.