JPH0236615A - Clock generating system - Google Patents

Abstract

PURPOSE:To reduce the fluctuation of jitter of a clock signal due to a ripple of control input by obtaining a phase difference between an external synchronizing circuit and an internal synchronizing pulse as a direct analog quantity. CONSTITUTION:A reference signal generating means 4 generates a reference signal 24 increasing monotonously smoothly by a prescribed time only before an appearance time expected by an external synchronizing pulse 21. Moreover, a sample-and-hold means 6 holds the reference signal 24 in the timing receiving the external synchronizing pulse 21. Then a differential amplifier means 7 takes a difference between an output 50 of the sample-and-hold means 5 and a reference potential Vc to generate a phase error signal 25 between the external synchronizing pulse 21 and the internal synchronizing pulse 28. Thus, the phase difference between the external synchronizing pulse 21 and the internal synchronizing pulse 28 is obtained as a direct analog quantity by the sample-and-hold means 5. Thus, the fluctuation of jitter in the clock signal due to a ripple of control input of a voltage controlled oscillator 11 is reduced.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a clock generation method, and in particular, to detecting lock information from a recording medium, which is necessary for recording and reproducing data in optical disk devices and the like. The present invention relates to a clock generation method that generates a clock for recording and reproducing based on detected clock information υ.

[Conventional technology]

In an optical disk device or the like, a control information area including lock bits and servo bits necessary for recording/reproducing information and detecting servo information, and a data area for recording information are shown in FIG. 5(a). As shown, the clock information read from the recording medium is arranged alternately radially in the information trunk on the recording medium, that is, the control information area A and the data area A are sequentially set along the circumferential direction as shown in the figure. A method of generating a clock signal with a frequency N times as high as 1, and detecting a servo signal and recording/reproducing information according to the timing of this clock signal is known as the sample servo method.

In the sample servo method, the detection of servo bits in the control information area AC and the timing of recording and reproducing information are defined by clock information, that is, the detection timing of the clock bit and the timing of a clock signal synchronized therewith. FIG. 5(b) shows the relationship between the arrangement of bits on the information track centered on the control information area Ac, the reproduced signal 20, the clock signal 27, and the clock information detected from the optical disc as a recording medium. In FIG. 5(b), symbol P indicates a servo bit, PC indicates a clock bit, and P indicates a data bit.

Signal detection from the disk is performed using (b) and (b) in Figure 5(b).
This is done by sampling the reproduced signal 20 at the timing of the clock signal 27, as in c). When a phase shift occurs between the clock signal 27 and the clock information on the disk, the sample of the reproduced signal 20 deviates from the peak of the reproduced signal 20, causing an error in the detected information. In the sample servo method, in order to perform accurate signal detection, it is required to generate a clock signal 27 that is accurately phase-synchronized with clock information detected from the disk when recording and reproducing data on the optical disk.

Conventionally, when clock information is detected from a reproduction signal of a disk and an external synchronization pulse 21 is generated at the detection timing of the clock information, a clock signal whose phase is synchronized with the detected external synchronization pulse 21 is generated. As shown in FIG. 6(a), the clock signal 27, which is the oscillation output of the voltage controlled oscillator 601, is divided into 1/N by a 1/N frequency divider 602.
An internal synchronization pulse 2B whose frequency is divided into N is generated, and an external synchronization pulse 21 and an internal synchronization pulse 28 detected from the recording medium are generated.
The phase comparison means 603 detects the phase difference between the
4 as a control voltage 48 to the control input of the voltage controlled oscillator 601 to perform phase tracking operation of the internal synchronizing pulse 28 with respect to the external synchronizing pulse 21, and to output the clock signal of the voltage controlled oscillator 601 and the external synchronizing pulse 21.
A method was used to match the phases of the

An example of the configuration of the phase comparison means 603 in the conventional clock generation method is shown in FIG. 6(b). In the figure, an external synchronization pulse 21 is applied as a clock input to a first D flip-flop 40 and an internal synchronization pulse 28 is applied as a clock input to a second D flip-flop 41. Logic level 1 is input to the D inputs of the two D flip-flops 40 and 41.

Q output of two D flip-flops 40.41 42.4
4 are respectively input to the NAND gate 47, and the NAN
The output 43 of the D gate 47 is connected to two D flip-flops 4
0.41 clear input (CLR), respectively. Furthermore, the Q outputs 42 and 44 of the two D flip-flops 40 and 41 are simultaneously input to the differential amplifier 45 and output as a phase error signal 46.

When the two D flip-flops 40 and 41 are cleared in the initial state, when the external synchronization pulse 21 is input as shown in FIG. 7(a), the first D flip-flop 40 and 41 are cleared as shown in FIG. 7(b). The Q output 42 of the D flip-flop 40 becomes "1". As shown in FIG. 7(c), when the internal synchronizing pulse 28 is input to the second D flip-flop 41 with a delay of time t2 from the external synchronizing pulse 21, the second D flip-flop 41 is input as shown in FIG. 7(d). The Q output 44 of the d flip-flop 41 becomes "1". At this time, as shown in FIG. 7(e), N
The output 43 of the AND gate 47 becomes "0", and the first . The second D flip-flop 40.41 is cleared and 2
The Q output 42.44 of the two D free knob flops becomes 0''.

The phase error signal 46 output from the differential amplifier 45 is detected as a pulse with an amplitude Va having a width of the appearance time difference t2 between the external synchronization pulse 21 and the internal synchronization pulse 28, as shown in FIG. 7(f). . The detected phase error signal 46 is
It is applied to the control input of the voltage controlled oscillator 601 via a filter 604 having an integral characteristic as shown in FIG. 6(a), and phase tracking is realized by controlling the oscillation output frequency.

[Problem to be solved by the invention]

However, when performing phase tracking by controlling the oscillator output frequency in this way, conventional methods do not detect jitter fluctuations in the clock signal due to ripples in the control input of the voltage-controlled oscillator or external synchronization pulses. There are drawbacks such as disturbances in the phase tracking operation when

In the conventional method, the external synchronization pulse 21 shown in FIG.
On the other hand, when the internal synchronization pulse 28 shown in FIG. 8(b) is tracked, the phase error is detected as the energy of the pulse of the phase error signal 46 as shown in FIG. 8(c), so the integral characteristic is The control voltage 48 output from the filter 604 includes a ripple component corresponding to the pulse, as shown in FIG. 8(d). When the voltage controlled oscillator 601 changes its output frequency according to such a control voltage 48, the jitter of the clock signal within the period in which the external synchronization pulse 21 is input is equal to the jitter of the clock signal within the period of the external synchronization pulse 210. Since the frequency fluctuation is integrated, it fluctuates greatly during time t3 corresponding to the pulse of the phase error signal 46, as shown in FIG. 8(e). For this reason, there is a problem in that jitter occurs in the clock signal as the reference timing for recording and reproducing, which causes errors. Also, if no external synchronization pulse is detected,
There is a problem in that an abnormal phase error signal is generated and disturbs the phase tracking operation.

It is an object of the present invention to solve such problems, to reduce fluctuations in clock signal jitter due to ripples in the control input of the internal oscillator with variable frequency, and to enable phase tracking operation even when no external synchronization pulse is detected. An object of the present invention is to provide a clock generation method that can prevent disturbances.

[Means to solve the problem]

In the present invention, the output of an internal oscillator with a variable frequency is set to 1 in response to an external synchronization pulse of a generally constant frequency input from the outside.
/H, generates an internal sync pulse whose frequency is divided into A clock generation method in which the phase of the pulse is synchronized and an internal oscillator generates a clock signal with N times the frequency whose phase is synchronized with the external synchronization pulse Monotonically increases from a certain time before the expected appearance time of the external synchronization pulse It is characterized in that it generates a reference signal, samples and holds the reference signal at the timing when an external synchronization pulse is input, and subtracts a constant comparison voltage from the held output, and uses the result as a phase error signal.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a clock generation device to which a clock generation method according to the present invention is applied.

In addition, FIGS. 2(a) and 2(b) are for explaining phase difference detection by this method, and FIG. 2(a) shows a part of FIG. 1, and furthermore, Figure 2 (
b) shows an example of the configuration of the reference signal generating means in FIGS. 1 and 2(a).

In FIG. 1, this embodiment includes a clock extraction means 1, a timing generation means 2, an N-ary counter 3, a reference signal generation means 4, a sample hold means 5, a differential calculation means 7, and a switch 9. , a filter lO, a voltage controlled oscillator 11 as an internal oscillator, a reference oscillator 12, and a phase comparison means 13.

The clock extraction means 1 detects an external synchronization pulse 21 from the reproduced signal 20 and supplies this to the timing generation means 2. The timing generating means 2 is further supplied with a control signal 22, a count output 29 from the N-ary counter 3, and an internal synchronization pulse 28.

A clock signal 27 is applied to the N-ary counter 3 from a voltage controlled oscillator 11 connected to a filter 10 . The internal pulse 28 converts the clock signal 27 into the N-ary counter 3.
This is obtained by dividing the frequency by 1/H.

The internal synchronization pulse 28 is also supplied as one input of the phase comparison means 13, and the reference pulse 34 from the reference oscillator 12 is applied as the other input of the phase comparison means 13.

The phase comparison means 13 is connected to the terminal B of the switch 9 which can be controlled to switch between the terminals A, B, and C.
selects the terminal B side as shown in FIG.
0.

The timing generating means 2 supplies a reference gate signal 23 to the reference signal generating means 4, a sample control signal 30 to the sample hold means 5, a switching signal 33 to the switch 9, and an N-ary counter 3. A clear signal 35 for each is sent out at a predetermined timing.

The sample and hold means 5 is supplied with the reference signal 24 from the reference signal generation means 4, and the sample and hold output 50 is supplied to the differential calculation means 7.

The output of the differential calculation means 7 is applied as a phase error signal 25 to the terminal A side of the switch 9.

Specifically, the reference signal generating means 4 is as shown in FIG. 2(b).
As shown in the figure, switches 51, 52, a resistor R2, and a capacitor C are connected between the output terminal and the inverting input terminal, and an operational amplifier 53, which is connected to the switch 51 via a resistor R1, and a reference power supply. It is possible to have a configuration consisting of V. This reference signal generating means 4 constitutes a means for generating a reference signal 24 that smoothly and monotonically increases from a predetermined time period before the expected appearance time of the external synchronizing pulse 21.

The sample hold means 5 holds the reference signal 24 at the timing when the external synchronization pulse 21 is input.

The differential amplification means 7 receives the output 50 of the sample hold means 5.
A phase error signal 25 between the external synchronizing pulse 21 and the internal synchronizing pulse 28 is generated by taking the difference between the external synchronizing pulse 21 and the reference potential VC.

The timing generating means 2 is shown in FIG.
FIG. 2(a) shows the input/output relationship, which can be easily and variously realized using standard logic elements, and it is not the purpose of the present invention to show the details of the timing generating means 2. , details regarding the configuration are omitted.

Next, regarding the operation of this embodiment, FIG. 3 shows the waveforms of each part when performing a phase pulling operation of the clock signal 27 with respect to the external synchronization pulse 21, and FIG. This will be explained with reference to FIG.

The following explanation is for the case where it is applied to an optical disk device, and as shown in FIG. It is separated by the extraction means 1 and output as an external synchronization pulse 21 to the timing generation means 2.
is input. The timing generation means 2 is an element that controls the entire system, and controls the phase tracking operation and generates the reference gate signal 2.
3 and generates sample timing for the sample hold means 5. A control signal 22 for synchronizing clock signals is inputted to the timing generating means 2 by an external control device, and the control signal 22 is "
l”, the clock signal 27 whose phase is synchronized with the external synchronization pulse 21 is generated, and the control signal 22 is “0”.
”, the reference pulse output from the reference oscillator 12,
That is, the components are controlled so as to generate a clock signal 27 whose phase is synchronized with the reference pulse 34 having a period approximately equal to that of the external synchronization pulse 21 .

First, in the initial state, while the control signal 22 is "0", the switch 9 is controlled to select the terminal B by the switching signal 33 output from the timing generating means 2. A phase comparator 13 is connected to the terminal B of the switch 9. The reference pulse 34 output from the reference oscillator 12 and the internal synchronization pulse 28 generated by dividing the clock signal 27 by 1/N by the N-ary counter 3 are input to the phase comparison means 13, and the switch 9 is set to The clock signal output of the voltage controlled oscillator 11 is controlled to be phase synchronized with the reference pulse 34 during the terminal selection period.

Next, the operation of making the phase of the clock signal 27 follow the external synchronization pulse 21 will be explained. control signal 2
When "11" is input to 2, the timing generating means 2 controls the switch 9 to select the C terminal by the switching signal 33. Furthermore, the timing generating means 2 controls the switch 9 to select the C terminal after the control signal 22 changes to "1". A clear signal 35 is generated to clear the N-ary counter 3 to 0' with the first external synchronization pulse 21 of
Generates phase difference detection operation timing such as generation of .

Clearing N-ary counter 3 and reference gate signal 23
The occurrence of this will be explained using FIG.

FIG. 3 shows the clock signal 2 relative to the external synchronization pulse 21.
7 shows the waveforms of each part when performing the phase pull-in operation. FIG. 3(a) shows the waveform of the control signal 22, which changes from "0" to "1" at time TO. Figure 3(b) shows the count output 29 of the N-ary counter 3.
The N-ary counter 3 repeatedly counts from O to N-1 by counting the clock signal 27. At this time, as shown in FIG. 3(c), when the count output 29 becomes "0", the internal synchronization pulse 28 is output. In the initial state, internal synchronization pulse 28
operates in phase synchronization with the reference pulse 34 shown in FIG. 3(d). FIG. 3(e) shows an external synchronization pulse 21 detected from the reproduction signal 20 of the optical disc. Time T
After the control signal 22 becomes "1" at O, the clear signal 35 is outputted from the timing generating means 2 at the time TI when the external synchronization pulse 21 first appears, as shown in FIG. 3(f). The N-ary counter 3 is cleared by this clear signal 35 and starts counting from "0". In the initial state, the oscillation frequency of the clock signal 27 is controlled so as to be synchronized in phase with the reference pulse 34, which has approximately the same period as the external synchronization pulse 21. Therefore, the next timing when the external synchronization pulse 21 is input is based on the N-ary counter. It is expected that at time T2, the output 29 will perform the counting operation N times and the count output 29 will become 0 again. Letting the period of the clock signal 27 be Δt, the time t1. Assuming that t3 is tl=pXΔt and t3=qxΔt, the timing for changing the reference gate signal 23 from “0” to “1” a time tl before time T2 is as follows.
As shown in FIG. 3(g), this is the time when the count output of the N-ary counter 3 becomes N-p (see FIG. 3(b)),
Similarly, the timing at which the reference gate signal 23 is changed from "1" to "10" after time t3 from time T2 is determined as the timing when the count output 29 of the N-ary counter 3 becomes q (see FIG. 3(b)). In this way, input of the predicted external synchronization pulse 21 such as the reference gate signal 23 is performed for the second and subsequent external synchronization pulses 21 after the control signal 22 changes from "0" to "L". Let the relative time timing to the timing be N
It can be detected from the count output 29 of the advance counter 3 using a digital comparator or the like.

In FIG. 1, the timing generating means 2 controls the switch 9 to select the A terminal by the switching signal 33 after the external synchronizing pulse 21 is input during the period when the reference gate signal 23 is "L". conduct. When the external synchronizing pulse 21 is input to the sample and hold means 5 during the period when the reference gate signal 23 is "1", a signal corresponding to the phase error is sampled as described above. Therefore, the phase error signal 25 is input to the voltage controlled oscillator 11 via the switch 9 and the filter 10, and the external synchronization pulse 2
The frequency of the clock signal 27 is controlled so that the phases of the clock signal 1 and the internal synchronization pulse 28 match.

The method of detecting the phase difference between the external synchronization pulse 21 and the internal synchronization pulse 28 is performed as follows.

The clock generating device according to this system comprises a phase comparison means as shown in FIG. 2(a) to detect the phase difference between the external synchronizing pulse 21 and the internal synchronizing pulse 28.

The reference signal generating means 4 shown in FIG.
The reference gate signal 23 is applied from the timing generating means 2 from before to after the time t3. Reference gate signal 23
The generation of is performed as explained in FIG. The reference signal generating means 4 outputs a reference signal 24 that increases smoothly and monotonically. As shown in FIG. 2(b), the reference signal generating means 4 generates a ramp waveform using an integrator 53 constituted by an operational amplifier, and uses this as the reference signal 24. The switch 51 and the switch 52 are controlled by the reference gate signal 23. When the reference gate signal is "0", the switch 51 is connected to the GND side, the switch 52 is in a closed state, and the reference gate signal 23 is controlled.
0■ is output to 4. Reference gate signal 23 is “1”
At this time, the switch 51 is connected to the reference potential vr side, the switch 52 is in an open state, and a ramp waveform is output.

FIG. 4 shows the waveforms of each part during phase difference detection. Figure 4 (a
) When the reference gate signal 23 is inputted as shown in FIG. 4(b), the reference signal 24 is outputted as shown in FIG. 4(b). As shown in FIG. 4(C), when the external synchronizing pulse 21 is input, the timing generating means 2 generates the sample control 1 corresponding to the external synchronizing pulse 21 as shown in FIG. 4(d).
The signal 30 is output, and the reference signal 24 is held by the sample and hold means 5 as shown in FIG. 4(e). Set the hold value to ■8. At the timing T when the external synchronization pulse 21 is predicted, the reference signal 24 has a ramp waveform that increases in a - manner during the time t1, so the reference signal 24 always has a constant value (2). is equal to Therefore, Figure 4 (
f), the output 50 of the sample hold means 5 which samples the reference signal 24 is converted to V by the differential calculation means 7. The result of subtracting the value can be used as the phase error signal 25.

As described above, in the clock generation method of the present invention, the phase difference between the external synchronization pulse 21 and the internal synchronization pulse 28 is reduced to 1.
It can be obtained directly as an analog quantity using two sample and hold means.

In this way, in this embodiment, the output of the voltage controlled oscillator 11 as a frequency variable internal oscillator is set to 1/N with respect to the external synchronizing pulse 21 of approximately constant frequency input from the outside.
generates an internal synchronization pulse 28 whose frequency is divided into In a clock generation method in which the phases of the pulse 28 and the external synchronization pulse 21 are synchronized, and the voltage controlled oscillator 11 generates a clock signal 27 of N times the frequency whose phase is synchronized with the external synchronization pulse 21, the external synchronization pulse 21 A certain time t1 from the expected appearance time of
generates a reference signal 24 that increases smoothly and monotonically from the front, and holds the reference signal 24 by the sample and hold means 5 at the timing when the external synchronization pulse 21 is input;
By subtracting a constant comparison voltage from the held output and using it as the phase error signal 25, the phase difference can be obtained directly as an analog quantity, and the clock signal generated by the ripple of the control input of a voltage controlled oscillator as in the conventional case can be obtained. jitter fluctuations can be reduced, and errors caused by this can be prevented.

〔Effect of the invention〕

As explained above, in the clock generation method of the present invention,
The phase difference between the external synchronization pulse and the internal synchronization pulse can be obtained directly as an analog quantity, making it possible to reduce fluctuations in clock signal jitter due to control input ripples. Further, even if an external synchronization pulse is not detected within the expected period, it is possible to hold the previous phase error information, so there is little disturbance in the phase tracking operation. In this way, by using the clock detection method of this system, a highly accurate and stable clock can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a clock generation device to which the clock generation method of the present invention is applied, FIG. 2 is a partial configuration diagram of FIG. 1 for explaining the phase detection method, and FIG. 3 is an external Figure 4 shows the waveforms of each part when the phase pull-in starts in response to a synchronization pulse. Figure 4 shows the waveforms of each part to explain the operation when detecting the phase difference. Figure 5 shows the clock information recorded on the disk and the clock. Figure 6 is a diagram showing the relationship between signals. Figure 6 is a diagram showing the conventional clock generation method. Figure 7 is a diagram explaining the principle of phase difference detection using the conventional method. Figure 8 is the jitter and phase tracking in the conventional method. FIG. 3 is a diagram for explaining disturbances in motion. 1... Clock extraction means 2 ・ 3 ・ 4 ・ 5 ・ 10 ・ 11 ・ 21 ・ 23 ・ 27 ・ 28 ・ Timing generation means ・ N-ary counter ・ Reference signal generation means ・ Sample and hold means ・ Filter ・ Voltage Controlled oscillator, external synchronization pulse, reference gate signal, clock signal, internal synchronization pulse

Claims (1)

[Claims] (1) The output of the internal oscillator, which has a variable frequency, is set to 1/N in response to the external synchronization pulse of approximately constant frequency input from the outside.
generates an internal synchronization pulse whose frequency is divided into In a clock generation method that synchronizes the phase and generates a clock signal of N times the frequency from an internal oscillator with the phase synchronized to the external synchronization pulse,
Generates a reference signal that monotonically increases from a certain time before the expected appearance time of the external synchronization pulse, samples and holds the reference signal at the timing when the external synchronization pulse is input, and subtracts a certain comparison voltage from the held output. A clock generation method characterized by using the result as a phase error signal.