JP2663696B2 - Automatic frequency control method - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an automatic frequency control system used for a video signal recording / reproducing apparatus or the like.

FIG. 2 is a block diagram showing an example of a conventional automatic frequency control system.

The synchronization signal detection circuit 5 outputs a synchronization signal 6 detected from the video signal to the phase detector 1. The phase detector 1 outputs a signal having a pulse width proportional to the phase error between the synchronization signal 6 and the feedback signal 4a from the frequency divider 4. Error amplifier 2
Converts the signal from the phase detector 1 into a DC voltage so that the voltage-controlled oscillator 3 can receive the signal as control information. The voltage controlled oscillator 3 outputs a clock 7 having an oscillation frequency corresponding to the DC voltage, and the frequency dividing circuit 4 divides the clock 7 and outputs it as a feedback signal 4a.
As the output oscillation frequency, a clock 7 synchronized with the synchronization signal 6 detected from the reproduced video signal is obtained, and this clock 7 is used as a sampling clock used for quantization of the reproduced video signal.

[Problems to be solved by the invention]

In this conventional automatic frequency control method, the phase of the feedback signal and the synchronization signal via the feedback loops of the circuits 1 to 4 are compared with each other until a sampling clock phase-synchronized with the reproduced video signal is obtained. Must be converted to a voltage error, and a series of operations to perform oscillation control based on the voltage error must be repeated, so that the response speed required to obtain a sampling clock synchronized with the reproduced video signal is slow, and Since the response speed of returning from the synchronous state to the synchronous state is slow, if a disturbance such as dropout occurs within the response time for generating the sampling clock whose phase is synchronized with the reproduced video signal, a stable synchronous state cannot be created. In particular, this state may frequently occur when trying to obtain a clock synchronized with a reproduced video signal at the time of high-speed reproduction having a reproduced video signal lacking portion due to crossing of tracks of a magnetic recording / reproducing tape.

[Means for solving the problem]

The automatic frequency control method according to the present invention comprises: a reference clock generating means having an integral multiple of a frequency of a sampling clock used for quantization of a reproduced video signal; and counting a cycle of one line of the reproduced video signal by the reference clock. A calculating means for deriving a reference clock number corresponding to the sampling clock cycle; and a variable means for varying the sampling clock cycle based on the reference clock number corresponding to the sampling clock cycle derived by the calculating means.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. Reference numeral 8 denotes a reference clock generator, reference numeral 9 denotes a reference clock frequency division amount detection circuit, reference numeral 10 denotes a data hold circuit, reference numeral 11 denotes an accumulation operation circuit, reference numeral 12 denotes a difference detection circuit, and reference numeral 13 denotes a frequency division circuit.

The reference clock generator 8 generates a reference clock having a frequency that is an integral multiple of the sampling clock used for quantizing the reproduced video signal. At this time, the higher the number of times the sampling clock is multiplied, the more accurate the control can be performed.

In the arithmetic circuit section which counts the cycle of one line of the reproduced video signal by the reference clock and derives the number of reference clocks corresponding to the sampling clock cycle, the latch circuit 10 counts from the desired counting start point to the end point one line before. The reference clock number is held, and the held data is sent to the reference signal frequency division amount detection circuit 9 as the reference clock number included in the next one line. The reference signal frequency division amount detection circuit 9 divides the held data by the sampling number to be included in one line of the video signal, and outputs a reference clock number corresponding to a sampling clock cycle. At this time, the output data is a real value having an accuracy capable of transmitting this information to the next stage even if the number of reference clocks included in one line changes by one from a desired reference number.

The accumulation operation circuit 11 initializes the data starting point of the real value, which is the output of the reference signal frequency division amount detection circuit 9, by the clear pulse 15 detected from the reproduced video signal by the synchronization signal detection circuit 5, and then resets the sampling clock. Cumulative calculation for each
Outputs an integer value that includes carry information to the integer part. Then, the result of the cumulative calculation is sent to the reference signal frequency division amount detection circuit 9 and the difference detection circuit 12. The output of the accumulation operation circuit 11 sent to the reference signal frequency division amount detection circuit 9 is used as the reference clock number included in one line after one line, and the same processing as described above is performed using this. As described above, each of the circuits 9 to 11 constitutes the feedback loop 14, and generates a sampling clock synchronized with the reference clock cycle for a reproduced video signal input from the outside.

For example, a sampling clock of 28.998 MHz
Uses a reference signal with a frequency of 347.976 megahealth multiplied by 12, and the standard sampling number of one line with a sampling clock used for quantization of a video signal is 1800.
The number of reference clocks in one line is 21
The number is 600 and is calculated by the reference signal frequency division amount detection circuit 9 (216
00 [number] / 1800 [times]), the accuracy with which this information can be transmitted to the next stage even if the number of reference clocks included in one line changes by one from the desired standard number. In order to output as a real value having, it is necessary to have precision of 11 bits after the decimal point. In addition, the cumulative operation result using the output of the reference signal frequency division amount detection circuit 9 having an accuracy of 11 bits after the decimal point indicates that the time axis error of one line of the reproduced video signal is always less than 28.7 nanoseconds which is one cycle of the reference signal. Is output as the value to be held down.

In the variable circuit unit that varies the period of the sampling clock according to the number of reference clocks corresponding to the period of the sampling clock derived by the arithmetic means,
Then, a difference is detected between the integer value data received from the accumulating operation circuit 11 and the sampling clock of the immediately preceding integer value data, and the frequency dividing circuit 13 corresponds to the sampling clock cycle output from the difference detecting circuit 12. A frequency division operation is performed to adjust the period of the sampling clock according to the number of reference clocks to be generated, and a sampling clock is generated.

By doing so, the present embodiment reduces the convergence time of the control loop to the reference frequency for returning from the out-of-synchronization state of the control loop to the synchronization state due to frequency fluctuations and the incorporation of disturbance, and at the same time, adds the reference clock to the reproduced video signal. By generating the sampling clock synchronized with the cycle accuracy, the time axis error of the reproduced video signal can always be suppressed to less than one cycle of the reference clock, and the frequency tracking performance can be improved.

〔The invention's effect〕

As described above, the present invention provides a reference clock generating means having a frequency which is an integral multiple of a sampling clock used for quantization of a reproduced video signal, a sampling clock cycle which counts a period of one line of the reproduced video signal by the reference clock. And a variable means for adjusting the period of the sampling clock according to the number of reference clocks corresponding to the sampling clock period derived by the operation means, thereby obtaining sampling synchronized with the reproduced video signal. A clock can be generated to improve the frequency tracking performance, and the convergence time for returning from the out-of-synchronization state of the control loop to the synchronization state due to frequency fluctuations and disturbances can be reduced. is there.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram showing an example of a conventional automatic frequency control system. DESCRIPTION OF SYMBOLS 1 ... Phase detector, 2 ... Error amplifier, 3 ... Voltage controlled oscillator, 4,13 ... Division circuit, 5 ... Synchronous signal detection circuit, 6 ... Synchronous signal, 7 ... Sampling clock, 8
... A reference clock generator, 9 a reference signal frequency division amount detection circuit, 10 a latch circuit, 11 an accumulation operation circuit, and 12 a difference detection circuit.

Claims (1)

(57) [Claims] 1. A means for generating a reference clock having a frequency which is an integral multiple of a sampling clock used for quantization of a reproduced video signal, and a sampling clock which counts a cycle of one line of the reproduced video signal by the reference clock. And a variable means for varying the period of the sampling clock by the number of reference clocks corresponding to the period of the sampling clock derived by the computing unit. Automatic frequency control method.