JP2692669B2 - Clock generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generation circuit, and more particularly to a clock having a PLL (Phase Locked Loop) circuit configuration which generates a clock synchronized with this reference time by using a reference time information periodically given from the outside as a trigger. It relates to a generation circuit.

[0002]

2. Description of the Related Art An apparatus for decoding encoded video signals or audio signals requires a reproduction clock for reproducing these encoded signals. In order to generate this reproduction clock, reproduction reference time information that is periodically given is used, and a clock synchronized with this reference time information is generated by the PLL circuit.

As an example of this type of circuit, 1994 August
P. Of "Latest MPEG Textbook with Point Diagram" (written by Hiroshi Fujiwara) issued by ASCII Corporation on March 1st. 2
36-239.

FIG. 3 is a block diagram of a conventional clock generation circuit of this type. In FIG. 3, an oscillation clock of a VCO (voltage controlled oscillator) 34 is counted by a time counter 35 to measure time. This time output is subtracted from the reference time information given from the outside by the subtracter 31, and this subtracted output is converted into an analog voltage by the D / A (digital / analog) converter.

This analog voltage is applied to the low-pass filter 33.
Becomes the control voltage of the VCO 34 via
The oscillating clock of is the target generated clock.

The operation of clock generation will be described below with reference to FIG. First, the reference time information is given, and the subtracter 31 subtracts between this value and the count value of the time counter 35. At the same time, the reference time information is preset in the time counter 35, and thereafter the time counter 35 counts up with the generated clock.

The result of the subtraction by the subtractor 31 is the D / A converter 3
Converted into an analog signal by 2 and low-pass filter 3
The steep fluctuation is suppressed by 3, and the error voltage (control voltage) is input to the VCO 34. The oscillation frequency of the VCO 34 increases / decreases as the error voltage increases / decreases.

According to this configuration, when the oscillation frequency of the VCO 34 is low, the time counter 35 with respect to the reference time information.
Becomes smaller, the difference becomes a positive value, the error voltage to the VCO 34 rises, and its oscillation frequency rises. On the contrary, when the oscillation frequency of the VCO 34 is high, the error voltage to the VCO 34 is lowered by the opposite action, and the oscillation frequency is lowered. Therefore, it becomes possible to generate a clock in synchronization with the reference time information from the outside.

[0009]

In the conventional clock generation circuit shown in FIG. 3, since the difference between the reference time information and the time information of the time counter 35 is used as it is as the error voltage of the VCO 34, the oscillation frequency of the VCO is increased. Is deviated from the reference time, the longer the cycle in which the reference time information is given, the larger the difference from the time counter, and the larger the error voltage to the VCO, and the stability of the generated clock changes. It will be.

That is, when the cycle in which the reference time information is given changes, the error voltage given to the VCO changes and the stability of the generated clock changes.

An object of the present invention is to provide a clock generation circuit in which the stability of the generated clock does not change even if the cycle in which the reference time information is given changes.

[0012]

According to the present invention, a voltage-controlled oscillating means whose oscillation clock frequency is controllable in accordance with a control voltage, a clocking means for clocking in synchronization with the oscillating clock, and this clocking output And a control voltage generation means for generating the control voltage according to a time difference between externally given reference time information and a clock generation adapted to generate a clock synchronized with the reference time information by the voltage controlled oscillation means. A circuit is provided, wherein the control voltage generating means is configured to convert the time difference into a time difference per unit time to obtain the control voltage.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The operation of the present invention will be described. In addition to the time counter that counts the generated clock to count the time, a cycle counter that counts the input cycle of the reference time information given from the outside is also provided, which is the difference between the time count information of the time counter and the reference time information. The time difference is divided by the above cycle to calculate the time difference per unit time, and the VCO is controlled according to the calculation result.

More specifically, the reference time information given at a certain time is preset in the time counter and thereafter counted up by the clock generated by this circuit.
When the reference time information is given, the cycle counter counts up from 1 with the next generated clock as a trigger. When the reference time information is given again, the subtracter calculates the difference between the reference time and the time counter. The subtraction result is divided by the value of the cycle counter, the division result is D / A converted, and becomes a control signal to the VCO.

If there is a difference between the frequency of the clock on the information source side which gives the reference time information and the frequency of the clock of this circuit, the subtraction result by the subtractor changes depending on the period at which the reference time information is given. For example, the subtraction result at the cycle T is A
, The subtraction result in the cycle 2T is 2A. This subtraction result A or 2A is D / A converted to VCO
If used as a control signal of the VCO, even if the frequency difference between the information source side that gives the reference time and the clock of this circuit is a constant value, there is a difference in the fluctuation of the VCO oscillation frequency due to the difference in the cycle at which the reference time information is given. I will end up.

However, a value obtained by synchronously dividing the subtraction result, for example, A / T in the case of the cycle T in the above example, 2A / 2T = A / T in the case of the cycle 2T, is D / A converted to VCO. By using a control signal to the VCO, it is possible to eliminate the fluctuation of the oscillation frequency of the VCO due to the cycle in which the reference time information is given,
The stability of the oscillation frequency is improved.

Embodiments of the present invention will be described below in detail with reference to the drawings.

In FIG. 1, reference numeral 1 is a time counter that counts up with a generated clock, and a value obtained by incrementing +1 by the incrementer 3 is preset to the given reference time information. Reference numeral 2 is a cycle counter that counts the cycle in which the reference time information is given, using the generated clock. Reference numeral 4 is a subtracter for subtracting the value of the time counter from the reference time information.
Reference numeral 5 is a divider that divides the subtraction result of the subtractor 4 by the value of the cycle counter 2. Reference numeral 6 is a latch for holding the division result.

Reference numeral 7 is a D / A converter for converting the division result held in the latch 6 into an analog signal. Reference numeral 8 is a low-pass filter that suppresses a sharp change in the analog-converted signal. Reference numeral 9 is a voltage-controlled oscillator (Vo that is controlled by the output frequency of the low-pass filter 8).
ltage Controlled Oscillat
er).

Next, the operation of the embodiment of the present invention will be described with reference to the time chart of FIG. 2 together with FIG. First, the reference time information is given at the timing T1 in FIG. In this example, the value is “100”. This value is incremented by "1" by the incrementer 3 and preset in the time counter 1 by the strobe signal. At the same time, the cycle counter 2 also starts counting up from "1".

Next, assume that "200" is given as reference time information at the timing of T2 in FIG. 2, and the value of the time counter 1 at this time is "190". That is, it is assumed that the time counter 1 advances only by "90" while the reference time information advances by "100". In this case, the output of the subtractor 4 becomes “10”, and the divider 5 divides this value by the value “90” of the cycle counter, and as a result, “0.111 ...” Is held in the latch 6. This value is converted into an analog signal by the D / A converter 7, passed through the low pass filter 8, and
It serves as a control signal for the VCO 9 and serves to increase the oscillation frequency of the VCO 9.

In this embodiment, for convenience of explaining the features of the present invention, the following timing example will be described with the oscillation frequency of the VCO remaining constant.

If "400" is given as the reference time information at the timing of T3 in FIG.
Therefore, if the oscillation frequency of the VCO 9 is constant, the value of the time counter 1 becomes "380". That is, while the reference time information advances from "200" to "400", that is, "200", the time counter 1 advances from "200" to "380", that is, only "180".

In this case, since the output of the subtracter 4 is "20" and the period counter 2 is "180", the division result by the divider is "0.111 ...", and the same result as at the timing T2 is obtained. To be

Therefore, the VCOs of the reference time information source side and the VCO of this circuit are purely irrespective of the cycle in which the reference time information is given.
Therefore, the VCO 9 can be controlled by the frequency deviation from the VCO 9.

[0026]

As described above, according to the present invention, the frequency deviation per unit time (time difference) is calculated by dividing the difference between the reference time information and the time counter by the period in which the reference time information is given. Since this is used as the VCO control voltage, V is controlled regardless of the cycle in which the reference time information is given.
Since CO can be controlled, there is an effect that the stability of the oscillation frequency is improved.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a time chart showing the operation of the embodiment of the present invention.

FIG. 3 is a block diagram showing an example of a conventional clock generation circuit.

[Explanation of symbols]

 1 Time Counter 2 Cycle Counter 3 Incrementer 4 Subtractor 5 Divider 6 Latch 7 D / A Converter 8 LPF (Low Pass Filter) 9 VCO (Voltage Controlled Oscillator)

Claims (4)

(57) [Claims] 1. A voltage-controlled oscillating means, whose oscillation clock frequency is controllable in accordance with a control voltage, a time-measuring means for measuring time in synchronization with the oscillation clock, and a time-measuring output and reference time information given from the outside. A clock generation circuit including a control voltage generation means for generating the control voltage according to a time difference, wherein a clock synchronized with the reference time information is generated by the voltage controlled oscillation means,
The clock generation circuit, wherein the control voltage generation means is configured to convert the time difference into a time difference per unit time to obtain the control voltage. 2. The control voltage generating means, a subtracting means for subtracting the time output of the time measuring means and the reference time information, a cycle counting means for counting a cycle to which the reference time information is given, and a result of the subtraction. 2. The clock generation circuit according to claim 1, further comprising: a dividing unit that divides the clock by the period. 3. The clock generation circuit according to claim 2, wherein the cycle counting means has counting means for counting the oscillation clock between certain reference time information and subsequent reference time information. 4. The control voltage generating means includes an analog converting means for converting the output of the dividing means into an analog signal, and a low-pass filter having the analog converted output as an input. The output of the low-pass filter is the control voltage. 4. The clock generation circuit according to claim 2, wherein: