JPH0758978A - Frame pulse continuity holding circuit - Google Patents

Abstract

PURPOSE:To provide a circuit holding the continuity of a frame pulse, which fits to a digital video signal processing related to a display device that mainly uses PDP. CONSTITUTION:A discontinuity detection part 2 generating a discontinuity detection pulse of a prescribed polarity when a frame pulse P1 becomes discontinuous, a counter 4 executing prescribed counting after resetting with the discontinuity detection pulse, a decoder 5 generating the pulse of a prescribed polarity after the counter count 'n', a flip flop 3 outputting the pulse of a prescribed polarity when a system is reset with the discontinuity detection pulse, a virtual frame pulse generation part 6 generating a pulse whose period is the same as that of the frame pulse from a vertical synchronizing signal P2, a phase matching of the frame pulse in a regular state and a switching circuit which is changed over so that the virtual frame pulse is selected when the discontinuity of the frame pulse and the virtual frame pulse is detected are provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame pulse continuity holding circuit suitable for digital video signal processing mainly in a display device using a PDP (plasma display panel).

[0002]

2. Description of the Related Art A frame pulse is often required in a digital circuit using a video memory such as a PDP.
The frame pulse is a pulse that repeats, for example, "L" (low) in an odd field and "H" (high) in an even field in an interlaced signal. The frame pulse can be generated by observing the phase of the horizontal synchronizing signal (H-SYNC) with respect to the vertical synchronizing signal (V-SYNC). This is shown in FIG. In FIG.
A signal obtained by shifting V-SYNC (a) by a predetermined phase (θ) is used as a clock signal (d), and H-SYNC in an odd field at the rising timing (arrow portion) of the clock signal
See (b) and H-SYNC (c) for even fields. Specifically, as shown in FIG.
(Flip-flop) is provided, H-SYNC of each of the odd / even fields is input to the D input terminal, and the clock signal (d) is input to the clock (CLK) terminal. As a result, a pulse having "L" in the odd field and "H" in the even field is obtained at the output terminal Q as shown.

In the past, only the frame pulse thus obtained was used. However, in a VTR reproduction signal or the like, the phase relationship between V-SYNC and H-SYNC may become unstable due to jitter, and in such a case, the frame pulse cannot be generated normally. That is,
As described above, when pulses of “L” in the odd field and “H” in the even field should be alternately repeated, the L and H pulses of the same level are continuous (discontinuous state). Become. In the case of a frame pulse in a discontinuous state in which the continuity is cut off in this way, in the PDP, for example, in the case of a video signal having a horizontal frequency fh of 15.734 KHz, the screen becomes half in the vertical direction, or It becomes an abnormal state where it disappears. This is because in the case of the horizontal frequency fh, the writing should be performed twice, but when the frame pulse is in the discontinuous state, the writing is not performed twice.

[0004]

DISCLOSURE OF THE INVENTION The present invention provides a VDP for a PDP.
An object of the present invention is to provide a frame pulse continuity holding circuit in which the above-mentioned abnormal state does not occur even when a TR reproduction signal or the like is displayed.

[0005]

DISCLOSURE OF THE INVENTION The present invention uses a vertical synchronizing signal as a clock signal and generates a discontinuity detecting pulse of a predetermined polarity when the continuity of frame pulses becomes irregular. A counter that is reset by the discontinuity detection pulse and that performs a predetermined count after the reset, a decoder that generates a pulse of a predetermined polarity after the counter has counted n, and a pulse from the decoder at one input terminal. A flip-flop that is input, grounds the other input terminal, is reset by the discontinuity detection pulse input to the clear terminal, and outputs a pulse of a predetermined polarity when reset, and the frame pulse from the vertical synchronization signal. And a virtual frame pulse generation unit that generates a virtual frame pulse of the same period as Phase matching section that matches the phase of the frame pulse in the state, and the frame pulse and the virtual frame pulse from the phase matching section based on the output signal from the flip-flop, the discontinuity of the frame pulse in the discontinuity detecting section. When the frame pulse is not detected, the frame pulse is selected, and when the discontinuity of the frame pulse is detected, the frame pulse continuity holding circuit configured by a switching circuit that switches to select the virtual frame pulse is provided. .

[0006]

Function: The discontinuity detecting section detects discontinuity of the frame pulse. When this discontinuity is detected, a detection pulse of L (low) is output. On the other hand, a virtual frame pulse having the same period as the frame pulse is generated from the vertical synchronizing signal. A switching circuit switches between the frame pulse and the virtual frame pulse, and normally selects the frame pulse. Then, when the discontinuity is detected, the switching circuit is switched to the virtual frame pulse side. This switching is performed by the output signal of the flip-flop. Further, the phase matching unit performs phase matching so that the phase of the virtual frame pulse matches the phase of the frame pulse. As a result, the continuity between the frame pulse and the switched virtual frame pulse is maintained. Further, after a predetermined time has passed after the above switching, the frame pulse is switched back to the frame pulse side which has returned to the normal state. The predetermined time is counted by the counter based on the detection pulse.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A frame pulse continuity holding circuit according to the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of essential parts showing an embodiment of a frame pulse continuity holding circuit according to the present invention, and FIG. 2 is a time chart of waveforms of respective parts for explaining FIG. In FIG. 1, P1 is a frame pulse, P2 is a vertical synchronization signal (V-SYNC), and 1 is a vertical synchronization signal.
An inverter for inverting the phase of P2, 2 includes a latch circuit 2a and an exclusive OR gate 2b, and a discontinuity detection unit for detecting discontinuity of the frame pulse P1 is detected for 3 discontinuity of the frame pulse P1. Sometimes a JK flip-flop that outputs a pulse of L (low) for a predetermined period is reset by a pulse from the discontinuity detection unit 2, a counter that performs a predetermined count after the reset, and a reference number 5 after n counts of the counter 4. , A virtual frame pulse generator 6 generates a virtual frame pulse from the vertical synchronizing signal from the inverter 1, and a decoder 7 includes an exclusive NOR gate 7a, an exclusive OR gate 7b and a latch circuit 7c. The phase matching part that matches the phase of the virtual frame pulse with the phase of the normal frame pulse, 8 is a virtual frame from the frame pulse P1 and the phase matching part. A switching circuit for switching between the pulse P10. In this embodiment, the flip-flop 3
Is a JK type, but other flip-flops (RS type, etc.) may be used.

Next, the operation of the present invention will be described. The waveforms of the frame pulse P1 and the vertical synchronizing signal P2 are shown in FIG.
The frame pulse P1 is the exclusive OR gate of the discontinuity detector 2.
Input to one end of 2b. The phase of the vertical synchronizing signal P2 is inverted by the inverter 1 to become P3 (Fig. 2). The latch circuit 2a latches the frame pulse P1 using the phase-inverted vertical synchronizing signal P3 from the inverter 1 as a clock signal. This allows
The latch circuit 2a outputs a pulse P4 delayed by 1V (one vertical period) from the frame pulse P1, and the exclusive OR gate 2b.
Sent to the other end of. Then, if the exclusive OR of the two inputs is taken by the exclusive OR gate 2b, the output becomes P5. It is assumed that the frame pulse P1 normally maintains continuity from time T1 to T2, but L (low) and H (high) are inverted between T2 and T3 to cause discontinuity. Due to this discontinuity, the output P5 of the exclusive OR gate 2b changes from H to L (T2 to T4).

The pulse P5 is sent to the clear terminals (CLR) of the JK flip-flop 3 and the counter 4, respectively,
Reset each. That is, the reset is applied at the timing of T2 of the pulse P5. As a result, the output terminal Q of the JK-flip-flop 3 becomes a pulse which turns to L at T2 as shown at P6. This pulse P6 is used as a switching signal for the switching circuit 8. On the other hand, the pulse P3 is also sent to the virtual frame pulse generator 6. The virtual frame pulse generator 6 has P8a in which L and H are inverted for each vertical synchronizing signal.
Or P8b is generated. Where P8a or P8b
Means that the phase relationship with the frame pulse P1 is either, and is determined by the phase relationship between the pulse P3 and the frame pulse P1. Therefore, if the generated pulse is P8a, it has the same phase as the frame pulse, and if it is P8b, it has the opposite phase.
Therefore, the phase matching unit 7 is required. For the pulse (P8a or P8b), for example, a D-FF (flip-flop) is used, and the pulse P3 is divided in half to obtain a duty of 50.
This can be achieved by generating% pulses.

The latch circuit 7c of the phase matching section 7 latches the output P11 using the pulse P3 as a clock signal, and its output P9 is delayed by 1V (one vertical cycle) from the output P11 as shown in FIG. This pulse P9 and either P8a or P8b are subjected to an exclusive NOR (7a), and the output of the exclusive NOR 7a and either P8a or P8b are subjected to an exclusive OR (7b) to obtain the exclusive NOR. Output P10 of OR7b is P11
It is in phase with the current state of (L or H). That is, the phase matching is achieved. The virtual pulse P10 and the frame pulse P1 thus phase-matched are switched and selected by the switching circuit 8. While the frame pulse P1 is normal (T1 to T
In 2), the switching circuit 8 is set to the side for selecting the frame pulse P1. This setting is performed when the Q output of the JK-flip-flop 3 is at the H level during the period (T1 to T2).

However, when the discontinuity occurs at T2 as described above, the pulse P5 becomes L, and thereby P6 also becomes L, and the switching circuit 8 is switched to the side of the virtual pulse P10 (symbol A point). In this case, since the virtual pulse P10 and the frame pulse P1 have the same phase as described above, the output pulse P1
The continuity of 1 is maintained. On the other hand, the counter 4 starts counting from the timing of T4, and after n counts, the decoder 5 generates a pulse P7 which becomes H. Since the pulse P7 is sent to the J terminal (set terminal) of the JK-flip-flop 3,
Is set, and its Q output P6 returns to the original state H again (T5). When the pulse P6 returns to H, the switching circuit 8 also switches to the original state, and the frame pulse P1 is selected again. When the discontinuity is detected again (within n counts) from the time when the discontinuity is once detected to the return to the original state, the reset is applied again at that point, and the reset is performed after n counts from that point. .

[0012]

As described above, according to the present invention, V
When the continuity of the frame pulse is cut off due to jitter or the like and becomes discontinuous like the reproduced video signal of TR, the virtual frame pulse generated separately from the vertical sync signal is switched while maintaining the continuity, so that it is always normal. It is possible to obtain a frame pulse that maintains excellent continuity. Therefore, PD
Like P, when the frame pulse becomes discontinuous, the conventional adverse effects such as the screen being halved in the vertical direction or the image disappearing can be solved, and the PDP can be applied. This can contribute to improving the performance of the digital video processing circuit.

[Brief description of drawings]

FIG. 1 is a block diagram of a main part of an embodiment of a frame pulse continuity holding circuit according to the present invention.

FIG. 2 is a time chart of waveforms of various parts for explaining FIG.

FIG. 3 is an explanatory diagram of frame pulse generation.

[Explanation of symbols]

 P1 Frame pulse P2 Vertical sync signal (V-SYNC) 1 Inverter 2 Discontinuity detector 2a Latch circuit 2b Exclusive OR gate 3 JK-Flip-flop 4 Counter 5 Decoder 6 Virtual pulse generator 7 Phase matching unit 7a Exclusive NOR gate 7b Exclusive OR gate 7c Latch circuit 8 Switching circuit

Claims (3)

[Claims] 1. A discontinuity detection section for generating a discontinuity detection pulse having a predetermined polarity when a vertical synchronization signal is used as a clock signal and the continuity of frame pulses becomes non-normal. A counter that is reset and performs a predetermined count after the reset, a decoder that generates a pulse of a predetermined polarity after the counter has counted n, and a pulse from the decoder is input to one input terminal,
A flip-flop that grounds the other input terminal and is reset by the discontinuity detection pulse input to the clear terminal, and outputs a pulse of a predetermined polarity when reset, and the same period as the frame pulse from the vertical synchronization signal. A virtual frame pulse generation unit that generates a virtual frame pulse, a phase matching unit that matches the phase of the virtual frame pulse with the phase of the frame pulse in a normal state, and the frame pulse and the virtual frame pulse from the phase matching unit Based on the output signal from the flip-flop, the frame pulse is selected when the discontinuity detecting section detects no frame pulse discontinuity, and the virtual frame pulse is selected when the frame pulse discontinuity is detected. And a switching circuit that switches so that Muparusu continuity holding circuit. 2. A latch circuit to which the frame pulse is inputted, the frame pulse being inputted to one end, and an output signal of the latch circuit being inputted to the other end of the discontinuity detector, 2. The frame pulse continuity holding circuit according to claim 1, wherein the frame pulse continuity holding circuit comprises an exclusive OR gate that outputs a continuous detection pulse. 3. A latch circuit for latching an output of the switching circuit by using the vertical synchronizing signal as a clock signal, and a virtual frame pulse from the virtual frame pulse generating section is input to one end of the phase matching section. , An exclusive NOR gate to which the signal from the latch circuit is input at the other end,
The virtual pulse is input to one end and the exclusive NO is input to the other end.
2. An exclusive OR gate, which receives a signal from the R gate and outputs a virtual frame pulse that matches the phase of the frame pulse in a normal state from the output end, and the frame pulse continuation according to claim 1. Sex retention circuit.