JPH10242850A - Clock generating pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock generating PLL circuit in which a phase shift of a clock signal is improved without the need for adjusting the range in phase control of the clock signal even when the operating condition is changed. SOLUTION: A phase comparator 1 compares a phase of a reference signal with that of a signal to be compared to provide an output of a control voltage. The control voltage is given to an LPF 2 and a VCO 3, from which a clock signal is generated. A frequency divider 4 frequency-divides the clock signal. An inverter 6 inverts the clock signal and the inverted clock is given to a DFF 7. An output of the frequency divider 4 is given to the DFF 7 and driven by the clock signal from the inverter 6. An output of the frequency divider 4 is given to an input terminal (a) of a changeover circuit 8 and an output of the DFF 7 is given to an input terminal (b). The changeover circuit 8 outputs them selectively and the result is fed to the phase comparator 1 as a signal to be compared.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generating PL for generating a clock locked to an input reference signal.
The present invention relates to an L circuit, and particularly to a clock generator for generating a clock locked to a horizontal synchronization signal, which is suitable for use in a display device or a television receiver which performs digital signal processing by inputting a signal from a personal computer (personal computer). It relates to a PLL circuit.

[0002]

2. Description of the Related Art An analog personal computer signal output from a personal computer is converted into a digital signal by an A / D converter or the like, and subjected to digital signal processing required for display on a display device such as a display device or a television receiver. , On the display device. The conversion of an analog signal to a digital signal by the A / D converter is as follows.
This is performed by sampling an analog signal. At this time, it is necessary that the frequency and phase of the sampling clock be correctly matched with the input analog personal computer signal as the original signal.

For example, in the case of an SVGA standard personal computer signal, the number of display pixels is 800 (horizontal) × 600 (vertical). Since the total number of pixels in one horizontal period is 1056,
Sampling by the A / D converter is normally performed by a clock in which one horizontal period is locked to 1056 horizontal synchronization signals. At this time, if not only the clock frequency but also the phase of the clock does not properly match the data phase of the personal computer signal, correct data cannot be obtained, and the following problems occur.

If the clock frequency is not correct (one horizontal period is not 1056), characters and the like may be partially unclear or unstable. The clock frequency is correct,
If the clock phase is not appropriate, characters and the like become thinner as a whole, the hue changes, and data error-like noise occurs.

Now, here, a conventional clock generating PL is described.
The structure and operation of an example of the L circuit will be described with reference to FIG.
FIG. 3 shows a PLL circuit which receives a video horizontal synchronization signal as a reference signal and obtains a clock locked to the horizontal synchronization signal.

In FIG. 3, one input terminal of the phase comparator 1 has a horizontal synchronizing signal (frequency Fref) as a reference signal.
) Is input, and a horizontal synchronous reproduction signal (frequency Fvari) obtained as described later is input to the other input terminal. The phase comparator 1 compares the phases of the input horizontal synchronization signal and the input horizontal synchronization reproduction signal, and outputs a detection voltage (error signal) corresponding to the phase difference to a low-pass filter (LPF) 2.
To enter. LPF2 smoothes the output of phase comparator 1,
Outputs control voltage. The control voltage output from LPF 2 is input to voltage shift circuit 5. Voltage shift circuit 5
Arbitrarily offsets the control voltage by a predetermined value and inputs the offset to a voltage controlled oscillator (VCO) 3. The offset voltage by the voltage shift circuit 5 is externally controlled. The voltage shift circuit 5 is generally realized by a combination of differential amplifiers using transistors.

The VCO 3 has a control voltage input terminal, and the control voltage from the voltage shift circuit 5 is input to the control voltage input terminal. The VCO 3 oscillates according to the input control voltage and outputs a clock. This clock is input to the frequency divider 4, and the frequency divider 4 divides (ie, counts) the input clock. If the count value of the frequency divider 4 is N, the clock frequency Fck is given by Fck = N × Fref.

The frequency-divided output of the frequency divider 4 is input to the phase comparator 1 as the above-mentioned horizontal synchronous reproduction signal (signal to be compared). In the PLL circuit configured as described above, when a voltage shift is applied by the voltage shift circuit 5, the phase comparator 1 generates an output voltage that cancels the shift voltage. , The phase of the reference pulse (horizontal synchronization signal) and the comparison pulse (horizontal synchronization reproduction signal) from the frequency divider 4 change relatively,
The phase of the clock output from the VCO 3 changes. As described above, the PLL circuit shown in FIG. 3 can obtain a clock locked to the horizontal synchronization signal and can control the phase of this clock. The voltage shift circuit 5 does not need to be provided in a normal PLL circuit that does not need to perform clock phase control.

[0009]

By the way, if the phase of the clock is generally changed in the range of 0 ° to 180 °,
The input analog PC signal can be sampled at the optimum phase. The shift voltage for controlling the phase of the clock changes according to the period of the reference pulse and the pulse width, or the frequency of the clock and the count number of the frequency divider 4.

Therefore, the shift voltages need to be individually set with high accuracy according to the operating conditions of the PLL circuit. Therefore, 0 ° to 180 ° corresponding to each mode (operating condition).
180 ° phase shift to achieve a phase shift of 180 °
The maximum value Vmax of the shift voltage for obtaining
For memory functions such as microcomputers,
It is necessary to store the maximum value Vmax for each operating condition.
Then, it is necessary to generate an arbitrary shift voltage in the range of the minimum value 0 to the maximum value Vmax for each mode.

Thus, in the PLL circuit shown in FIG.
Although phase control can be performed from the outside, it is necessary to obtain a preset value corresponding to each mode and store it in advance, so that there is a problem that adjustment work is involved and productivity is poor. In addition, a memory for storing the preset value is required, which increases the cost. Further, since the maximum value Vmax of the shift voltage varies depending on each mode, the control structure becomes complicated. This control is executed by the microcomputer program and D
When using the / A converter, the program becomes complicated.

The present invention has been made in view of such a problem, and it is possible to improve the clock phase shift without adjusting the range of clock phase control even when the operating conditions change. An object of the present invention is to provide a clock generation PLL circuit.

[0013]

According to the present invention, there is provided a clock generating PLL circuit for generating a clock locked to an input reference signal. A phase comparator (1) for comparing a phase with a signal; a low-pass filter (2) for obtaining a control voltage by smoothing an output of the phase comparator; and a clock to which the control voltage is input and corresponding to the control voltage A voltage-controlled oscillator (3) for generating and outputting a clock, a frequency divider (4) for dividing the clock, an inverter (6) for inverting the phase of the clock, and an output of the divider. ,
A data flip-flop (7) driven by a clock output from the inverter, an output of the frequency divider being input to one input terminal, and an output of the data flip-flop being input to the other input terminal; A clock generating PLL circuit characterized by comprising a switching circuit (8) for inputting a selective output of these inputs to the phase comparator as the signal to be compared.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a clock generation P according to the present invention will be described.
The LL circuit will be described with reference to the accompanying drawings. FIG.
FIG. 2 is a block diagram showing an embodiment of the clock generating PLL circuit of the present invention, and FIG. 2 is a timing chart for explaining the operation of the clock generating PLL circuit of the present invention. In FIG. 1, the same parts as those in FIG. 3 are denoted by the same reference numerals. Will be described with reference to the accompanying drawings.

In FIG. 1, one input terminal of a phase comparator 1 has a horizontal synchronizing signal (frequency Fref) as a reference signal.
) Is input, and a horizontal synchronous reproduction signal (frequency Fvari) obtained as described later is input to the other input terminal. The phase comparator 1 compares the phases of the input horizontal synchronization signal and the input horizontal synchronization reproduction signal, and outputs a detection voltage (error signal) corresponding to the phase difference to a low-pass filter (LPF) 2.
To enter. LPF2 smoothes the output of phase comparator 1,
Outputs control voltage. The control voltage output from the LPF 2 is input to a voltage controlled oscillator (VCO) 3.

The VCO 3 has a control voltage input terminal, and the control voltage from the LPF 2 is input to the control voltage input terminal. The VCO 3 oscillates according to the input control voltage and outputs a clock. This clock is input to the frequency divider 4, and the frequency divider 4 divides (ie, counts) the input clock. Note that the count value of the frequency divider 4 is N
Then, the clock frequency Fck is given by Fck = N × Fref.

The frequency-divided output of the frequency divider 4 is input to an input terminal a of a data flip-flop (DFF) 7 and a switching circuit 8. The clock output from the VCO 3 is input to the inverter 6.
Input to F7. The DFF 7 is driven by a clock input from the inverter 6. The output of DFF7 is
The signal is input to the input terminal b of the switching circuit 8. This switching circuit 8
Is selectively inputted to the phase comparator 1 as the above-described horizontal synchronous reproduction signal (compared signal).

FIG. 2 shows the operation of the PLL circuit of the present invention.
This will be described with reference to the timing chart shown in FIG. In FIG.
(A) is a horizontal synchronizing signal (reference signal) input to the phase comparator 1, and (B) is a horizontal synchronizing reproduction signal (input) to the phase comparator 1 when the switching circuit 8 selects the input terminal a. (C) the clock output from the VCO 3 when the switching circuit 8 selects the input terminal a, and (D) the frequency divider 4 when the switching circuit 8 selects the input terminal a. (E) shows the output of the inverter 6 when the switching circuit 8 selects the input terminal a, and (F) shows the output of the DFF 7 when the switching circuit 8 selects the input terminal a.
(G) is a horizontal synchronous reproduction signal (compared signal) input to the phase comparator 1 when the switching circuit 8 selects the input terminal b, and (H) is the switching circuit 8 selects the input terminal b. (I) is the clock output from the VCO 3 when the switching circuit 8 selects the input terminal b, and (J) is the clock output from the VCO 3 when the switching circuit 8 selects the input terminal b. 3 shows the output of the inverter 6.

First, when the switching circuit 8 selects the input terminal a by external control, the phase comparator 1, the LPF 2, the VCO 3, and the frequency divider 4 constitute a loop of the PLL circuit. The phase comparator 1 compares the reference signal shown in FIG. 2A with the compared signal shown in FIG. The clock from the VCO 3 and the output of the frequency divider 4 are shown in FIG.
The waveforms shown in (C) and (D) are obtained. At this time, the output of the inverter 6 and the output of the DFF 7 have the waveforms shown in FIGS.

On the other hand, when the switching circuit 8 selects the input terminal b by external control, the loop of the PLL circuit is constituted by the phase comparator 1, LPF2, VCO 3, frequency divider 4, inverter 6, DFF 7 Becomes At this time, the compared signal shown in FIG. 2 (G) input to the phase comparator 1 is obtained by converting the output of the frequency divider 4 shown in FIG. 2 (H) to the clock shown in FIG. Is an output latched by the clock shown in FIG.

That is, the switching circuit 8 selects the input terminal b,
When the PLL circuit is locked, the phase comparator 1 operates so that the phase relationship between the input signals (the reference signal and the signal to be compared) is the same as when the switching circuit 8 selects the input terminal a. Therefore, when the switching circuit 8 selects the input terminal b, the clock generated by the PLL circuit has an inverted phase with respect to the clock when the switching circuit selects the input terminal a. As described above, the PLL circuit of the present invention can generate two clocks that are shifted from each other by half a clock.

The phases of the generated clocks are 180 °
For example, since one of the compared signals is selected by the switching circuit 8 because of the phase relationship, it is assumed that the phase of the sampling clock to be converted into digital data is shifted by 180 ° with respect to the phase of the analog personal computer signal. Also, by selecting the other signal to be compared, the phase of the sampling clock can be switched to the optimum phase.

[0023]

As described in detail above, the clock generating PLL circuit of the present invention compares the phase of the reference signal with the phase of the signal to be compared, and smoothes the output of the phase comparator. A low-pass filter that obtains a control voltage, a voltage-controlled oscillator that receives the control voltage, generates and outputs a clock corresponding to the control voltage, a frequency divider that divides the clock, and an inverter that inverts the phase of the clock. The output of the frequency divider is input and the data flip-flop driven by the clock output from the inverter, and the output of the frequency divider is input to one input terminal, and the output of the data flip-flop is input to the other input terminal. And a switching circuit for inputting a selective output of these inputs to the phase comparator as a signal to be compared. There is no need to adjust, it is possible to improve a deviation of the sampling clock phase to be converted to phase and digital data of the analog computer signals. Further, this configuration can be realized with a very simple circuit configuration.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the present invention.

FIG. 3 is a block diagram showing a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Phase comparator 2 Low pass filter 3 Voltage controlled oscillator 4 Divider 6 Inverter 7 Data flip-flop 8 Switching circuit

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[Procedure amendment]

[Submission date] July 9, 1997

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0014

[Correction method] Change

[Correction contents]

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a clock generation P according to the present invention will be described.
The LL circuit will be described with reference to the accompanying drawings. FIG.
FIG. 2 is a block diagram showing an embodiment of the clock generating PLL circuit of the present invention, and FIG. 2 is a timing chart for explaining the operation of the clock generating PLL circuit of the present invention. In FIG. 1, the same parts as those in FIG. 3 are denoted by the same reference numerals .

Claims (1)

[Claims] 1. A clock generation PLL circuit for generating a clock locked to an input reference signal, a phase comparator for comparing the phases of the reference signal and a signal to be compared, and smoothing an output of the phase comparator. A low-pass filter that receives the control voltage, generates and outputs a clock corresponding to the control voltage, a frequency divider that divides the clock, and a phase of the clock. An inverter for inverting the output of the frequency divider, a data flip-flop driven by a clock output from the inverter, and an output of the frequency divider input to one input terminal;
A clock generating circuit for inputting an output of the data flip-flop to the other input terminal and inputting a selective output of these inputs to the phase comparator as the signal to be compared. PLL circuit.